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-rw-r--r--arch/arm/plat-omap/include/plat/clock.h2
-rw-r--r--arch/arm/plat-omap/include/plat/common.h13
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h108
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h233
-rw-r--r--arch/arm/plat-omap/include/plat/io.h2
-rw-r--r--arch/arm/plat-omap/include/plat/iommu.h78
-rw-r--r--arch/arm/plat-omap/include/plat/iommu2.h4
-rw-r--r--arch/arm/plat-omap/include/plat/iopgtable.h120
-rw-r--r--arch/arm/plat-omap/include/plat/iovmm.h30
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h208
-rw-r--r--arch/arm/plat-omap/include/plat/mmc.h19
-rw-r--r--arch/arm/plat-omap/include/plat/omap_device.h30
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h3
-rw-r--r--arch/arm/plat-omap/include/plat/voltage.h20
14 files changed, 479 insertions, 391 deletions
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index df4b9683f17f..197ca03c3f7d 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -80,8 +80,6 @@ struct clkops {
80 * 80 *
81 * @div is the divisor that should be applied to the parent clock's rate 81 * @div is the divisor that should be applied to the parent clock's rate
82 * to produce the current clock's rate. 82 * to produce the current clock's rate.
83 *
84 * XXX @flags probably should be replaced with an struct omap_chip.
85 */ 83 */
86struct clksel_rate { 84struct clksel_rate {
87 u32 val; 85 u32 val;
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 4564cc697d7f..abda2c7e499b 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -45,6 +45,15 @@ extern unsigned long long notrace omap_32k_sched_clock(void);
45 45
46extern void omap_reserve(void); 46extern void omap_reserve(void);
47 47
48void omap2420_init_early(void);
49void omap2430_init_early(void);
50void omap3430_init_early(void);
51void omap35xx_init_early(void);
52void omap3630_init_early(void);
53void am35xx_init_early(void);
54void ti816x_init_early(void);
55void omap4430_init_early(void);
56
48/* 57/*
49 * IO bases for various OMAP processors 58 * IO bases for various OMAP processors
50 * Except the tap base, rest all the io bases 59 * Except the tap base, rest all the io bases
@@ -74,7 +83,11 @@ void omap2_set_globals_sdrc(struct omap_globals *);
74void omap2_set_globals_control(struct omap_globals *); 83void omap2_set_globals_control(struct omap_globals *);
75void omap2_set_globals_prcm(struct omap_globals *); 84void omap2_set_globals_prcm(struct omap_globals *);
76 85
86void omap242x_map_io(void);
87void omap243x_map_io(void);
77void omap3_map_io(void); 88void omap3_map_io(void);
89void omap4_map_io(void);
90
78 91
79/** 92/**
80 * omap_test_timeout - busy-loop, testing a condition 93 * omap_test_timeout - busy-loop, testing a condition
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 67b3d75884cd..2f9026942229 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -44,13 +44,6 @@
44 44
45int omap_type(void); 45int omap_type(void);
46 46
47struct omap_chip_id {
48 u16 oc;
49 u8 type;
50};
51
52#define OMAP_CHIP_INIT(x) { .oc = x }
53
54/* 47/*
55 * omap_rev bits: 48 * omap_rev bits:
56 * CPU id bits (0730, 1510, 1710, 2422...) [31:16] 49 * CPU id bits (0730, 1510, 1710, 2422...) [31:16]
@@ -60,19 +53,6 @@ struct omap_chip_id {
60unsigned int omap_rev(void); 53unsigned int omap_rev(void);
61 54
62/* 55/*
63 * Define CPU revision bits
64 *
65 * Verbose meaning of the revision bits may be different for a silicon
66 * family. This difference can be handled separately.
67 */
68#define OMAP_REVBITS_00 0x00
69#define OMAP_REVBITS_01 0x01
70#define OMAP_REVBITS_02 0x02
71#define OMAP_REVBITS_03 0x03
72#define OMAP_REVBITS_04 0x04
73#define OMAP_REVBITS_05 0x05
74
75/*
76 * Get the CPU revision for OMAP devices 56 * Get the CPU revision for OMAP devices
77 */ 57 */
78#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff) 58#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
@@ -262,7 +242,7 @@ IS_OMAP_TYPE(2422, 0x2422)
262IS_OMAP_TYPE(2423, 0x2423) 242IS_OMAP_TYPE(2423, 0x2423)
263IS_OMAP_TYPE(2430, 0x2430) 243IS_OMAP_TYPE(2430, 0x2430)
264IS_OMAP_TYPE(3430, 0x3430) 244IS_OMAP_TYPE(3430, 0x3430)
265IS_OMAP_TYPE(3505, 0x3505) 245IS_OMAP_TYPE(3505, 0x3517)
266IS_OMAP_TYPE(3517, 0x3517) 246IS_OMAP_TYPE(3517, 0x3517)
267 247
268#define cpu_is_omap310() 0 248#define cpu_is_omap310() 0
@@ -354,8 +334,9 @@ IS_OMAP_TYPE(3517, 0x3517)
354 (!omap3_has_sgx()) && \ 334 (!omap3_has_sgx()) && \
355 (omap3_has_iva())) 335 (omap3_has_iva()))
356# define cpu_is_omap3530() (cpu_is_omap3430()) 336# define cpu_is_omap3530() (cpu_is_omap3430())
357# define cpu_is_omap3505() is_omap3505()
358# define cpu_is_omap3517() is_omap3517() 337# define cpu_is_omap3517() is_omap3517()
338# define cpu_is_omap3505() (cpu_is_omap3517() && \
339 !omap3_has_sgx())
359# undef cpu_is_omap3630 340# undef cpu_is_omap3630
360# define cpu_is_omap3630() is_omap363x() 341# define cpu_is_omap3630() is_omap363x()
361# define cpu_is_ti816x() is_ti816x() 342# define cpu_is_ti816x() is_ti816x()
@@ -379,35 +360,31 @@ IS_OMAP_TYPE(3517, 0x3517)
379/* Various silicon revisions for omap2 */ 360/* Various silicon revisions for omap2 */
380#define OMAP242X_CLASS 0x24200024 361#define OMAP242X_CLASS 0x24200024
381#define OMAP2420_REV_ES1_0 OMAP242X_CLASS 362#define OMAP2420_REV_ES1_0 OMAP242X_CLASS
382#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (OMAP_REVBITS_01 << 8)) 363#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (0x1 << 8))
383 364
384#define OMAP243X_CLASS 0x24300024 365#define OMAP243X_CLASS 0x24300024
385#define OMAP2430_REV_ES1_0 OMAP243X_CLASS 366#define OMAP2430_REV_ES1_0 OMAP243X_CLASS
386 367
387#define OMAP343X_CLASS 0x34300034 368#define OMAP343X_CLASS 0x34300034
388#define OMAP3430_REV_ES1_0 OMAP343X_CLASS 369#define OMAP3430_REV_ES1_0 OMAP343X_CLASS
389#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (OMAP_REVBITS_01 << 8)) 370#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (0x1 << 8))
390#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (OMAP_REVBITS_02 << 8)) 371#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (0x2 << 8))
391#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (OMAP_REVBITS_03 << 8)) 372#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (0x3 << 8))
392#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (OMAP_REVBITS_04 << 8)) 373#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (0x4 << 8))
393#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (OMAP_REVBITS_05 << 8)) 374#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (0x5 << 8))
394 375
395#define OMAP363X_CLASS 0x36300034 376#define OMAP363X_CLASS 0x36300034
396#define OMAP3630_REV_ES1_0 OMAP363X_CLASS 377#define OMAP3630_REV_ES1_0 OMAP363X_CLASS
397#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8)) 378#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (0x1 << 8))
398#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8)) 379#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (0x2 << 8))
399 380
400#define OMAP35XX_CLASS 0x35000034 381#define OMAP3517_CLASS 0x35170034
401#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) 382#define OMAP3517_REV_ES1_0 OMAP3517_CLASS
402#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8)) 383#define OMAP3517_REV_ES1_1 (OMAP3517_CLASS | (0x1 << 8))
403#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
404#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
405#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
406#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
407 384
408#define TI816X_CLASS 0x81600034 385#define TI816X_CLASS 0x81600034
409#define TI8168_REV_ES1_0 TI816X_CLASS 386#define TI8168_REV_ES1_0 TI816X_CLASS
410#define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8)) 387#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8))
411 388
412#define OMAP443X_CLASS 0x44300044 389#define OMAP443X_CLASS 0x44300044
413#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8)) 390#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
@@ -418,61 +395,6 @@ IS_OMAP_TYPE(3517, 0x3517)
418#define OMAP446X_CLASS 0x44600044 395#define OMAP446X_CLASS 0x44600044
419#define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8)) 396#define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8))
420 397
421/*
422 * omap_chip bits
423 *
424 * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
425 * valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates
426 * something that is only valid on that particular ES revision.
427 *
428 * These bits may be ORed together to indicate structures that are
429 * available on multiple chip types.
430 *
431 * To test whether a particular structure matches the current OMAP chip type,
432 * use omap_chip_is().
433 *
434 */
435#define CHIP_IS_OMAP2420 (1 << 0)
436#define CHIP_IS_OMAP2430 (1 << 1)
437#define CHIP_IS_OMAP3430 (1 << 2)
438#define CHIP_IS_OMAP3430ES1 (1 << 3)
439#define CHIP_IS_OMAP3430ES2 (1 << 4)
440#define CHIP_IS_OMAP3430ES3_0 (1 << 5)
441#define CHIP_IS_OMAP3430ES3_1 (1 << 6)
442#define CHIP_IS_OMAP3630ES1 (1 << 7)
443#define CHIP_IS_OMAP4430ES1 (1 << 8)
444#define CHIP_IS_OMAP3630ES1_1 (1 << 9)
445#define CHIP_IS_OMAP3630ES1_2 (1 << 10)
446#define CHIP_IS_OMAP4430ES2 (1 << 11)
447#define CHIP_IS_OMAP4430ES2_1 (1 << 12)
448#define CHIP_IS_OMAP4430ES2_2 (1 << 13)
449#define CHIP_IS_TI816X (1 << 14)
450#define CHIP_IS_OMAP4460ES1_0 (1 << 15)
451
452#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
453
454#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \
455 CHIP_IS_OMAP4430ES2 | \
456 CHIP_IS_OMAP4430ES2_1 | \
457 CHIP_IS_OMAP4430ES2_2 | \
458 CHIP_IS_OMAP4460ES1_0)
459
460/*
461 * "GE" here represents "greater than or equal to" in terms of ES
462 * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
463 * chips at ES2 and beyond, but not, for example, any OMAP lines after
464 * OMAP3.
465 */
466#define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \
467 CHIP_IS_OMAP3430ES3_0 | \
468 CHIP_GE_OMAP3430ES3_1)
469#define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1 | \
470 CHIP_IS_OMAP3630ES1 | \
471 CHIP_GE_OMAP3630ES1_1)
472#define CHIP_GE_OMAP3630ES1_1 (CHIP_IS_OMAP3630ES1_1 | \
473 CHIP_IS_OMAP3630ES1_2)
474
475int omap_chip_is(struct omap_chip_id oci);
476void omap2_check_revision(void); 398void omap2_check_revision(void);
477 399
478/* 400/*
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index eb5d16c60cd9..d11025e6e7a4 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/plat-omap/include/mach/dmtimer.h 2 * arch/arm/plat-omap/include/plat/dmtimer.h
3 * 3 *
4 * OMAP Dual-Mode Timers 4 * OMAP Dual-Mode Timers
5 * 5 *
@@ -35,6 +35,7 @@
35#include <linux/clk.h> 35#include <linux/clk.h>
36#include <linux/delay.h> 36#include <linux/delay.h>
37#include <linux/io.h> 37#include <linux/io.h>
38#include <linux/platform_device.h>
38 39
39#ifndef __ASM_ARCH_DMTIMER_H 40#ifndef __ASM_ARCH_DMTIMER_H
40#define __ASM_ARCH_DMTIMER_H 41#define __ASM_ARCH_DMTIMER_H
@@ -59,12 +60,56 @@
59 * in OMAP4 can be distinguished. 60 * in OMAP4 can be distinguished.
60 */ 61 */
61#define OMAP_TIMER_IP_VERSION_1 0x1 62#define OMAP_TIMER_IP_VERSION_1 0x1
63
64/* timer capabilities used in hwmod database */
65#define OMAP_TIMER_SECURE 0x80000000
66#define OMAP_TIMER_ALWON 0x40000000
67#define OMAP_TIMER_HAS_PWM 0x20000000
68
69struct omap_timer_capability_dev_attr {
70 u32 timer_capability;
71};
72
62struct omap_dm_timer; 73struct omap_dm_timer;
63struct clk; 74struct clk;
64 75
76struct timer_regs {
77 u32 tidr;
78 u32 tiocp_cfg;
79 u32 tistat;
80 u32 tisr;
81 u32 tier;
82 u32 twer;
83 u32 tclr;
84 u32 tcrr;
85 u32 tldr;
86 u32 ttrg;
87 u32 twps;
88 u32 tmar;
89 u32 tcar1;
90 u32 tsicr;
91 u32 tcar2;
92 u32 tpir;
93 u32 tnir;
94 u32 tcvr;
95 u32 tocr;
96 u32 towr;
97};
98
99struct dmtimer_platform_data {
100 int (*set_timer_src)(struct platform_device *pdev, int source);
101 int timer_ip_version;
102 u32 needs_manual_reset:1;
103 bool reserved;
104
105 bool loses_context;
106
107 u32 (*get_context_loss_count)(struct device *dev);
108};
109
65struct omap_dm_timer *omap_dm_timer_request(void); 110struct omap_dm_timer *omap_dm_timer_request(void);
66struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id); 111struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
67void omap_dm_timer_free(struct omap_dm_timer *timer); 112int omap_dm_timer_free(struct omap_dm_timer *timer);
68void omap_dm_timer_enable(struct omap_dm_timer *timer); 113void omap_dm_timer_enable(struct omap_dm_timer *timer);
69void omap_dm_timer_disable(struct omap_dm_timer *timer); 114void omap_dm_timer_disable(struct omap_dm_timer *timer);
70 115
@@ -73,23 +118,23 @@ int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
73u32 omap_dm_timer_modify_idlect_mask(u32 inputmask); 118u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
74struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer); 119struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
75 120
76void omap_dm_timer_trigger(struct omap_dm_timer *timer); 121int omap_dm_timer_trigger(struct omap_dm_timer *timer);
77void omap_dm_timer_start(struct omap_dm_timer *timer); 122int omap_dm_timer_start(struct omap_dm_timer *timer);
78void omap_dm_timer_stop(struct omap_dm_timer *timer); 123int omap_dm_timer_stop(struct omap_dm_timer *timer);
79 124
80int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source); 125int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
81void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value); 126int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
82void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value); 127int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
83void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match); 128int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
84void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger); 129int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
85void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler); 130int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
86 131
87void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value); 132int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
88 133
89unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer); 134unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
90void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value); 135int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
91unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer); 136unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
92void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value); 137int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
93 138
94int omap_dm_timers_active(void); 139int omap_dm_timers_active(void);
95 140
@@ -98,12 +143,30 @@ int omap_dm_timers_active(void);
98 * used by dmtimer.c and sys_timer related code. 143 * used by dmtimer.c and sys_timer related code.
99 */ 144 */
100 145
101/* register offsets */ 146/*
102#define _OMAP_TIMER_ID_OFFSET 0x00 147 * The interrupt registers are different between v1 and v2 ip.
103#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10 148 * These registers are offsets from timer->iobase.
104#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14 149 */
105#define _OMAP_TIMER_STAT_OFFSET 0x18 150#define OMAP_TIMER_ID_OFFSET 0x00
106#define _OMAP_TIMER_INT_EN_OFFSET 0x1c 151#define OMAP_TIMER_OCP_CFG_OFFSET 0x10
152
153#define OMAP_TIMER_V1_SYS_STAT_OFFSET 0x14
154#define OMAP_TIMER_V1_STAT_OFFSET 0x18
155#define OMAP_TIMER_V1_INT_EN_OFFSET 0x1c
156
157#define OMAP_TIMER_V2_IRQSTATUS_RAW 0x24
158#define OMAP_TIMER_V2_IRQSTATUS 0x28
159#define OMAP_TIMER_V2_IRQENABLE_SET 0x2c
160#define OMAP_TIMER_V2_IRQENABLE_CLR 0x30
161
162/*
163 * The functional registers have a different base on v1 and v2 ip.
164 * These registers are offsets from timer->func_base. The func_base
165 * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
166 *
167 */
168#define OMAP_TIMER_V2_FUNC_OFFSET 0x14
169
107#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20 170#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
108#define _OMAP_TIMER_CTRL_OFFSET 0x24 171#define _OMAP_TIMER_CTRL_OFFSET 0x24
109#define OMAP_TIMER_CTRL_GPOCFG (1 << 14) 172#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
@@ -147,21 +210,6 @@ int omap_dm_timers_active(void);
147/* register offsets with the write pending bit encoded */ 210/* register offsets with the write pending bit encoded */
148#define WPSHIFT 16 211#define WPSHIFT 16
149 212
150#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
151 | (WP_NONE << WPSHIFT))
152
153#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
154 | (WP_NONE << WPSHIFT))
155
156#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
157 | (WP_NONE << WPSHIFT))
158
159#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
160 | (WP_NONE << WPSHIFT))
161
162#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
163 | (WP_NONE << WPSHIFT))
164
165#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \ 213#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
166 | (WP_NONE << WPSHIFT)) 214 | (WP_NONE << WPSHIFT))
167 215
@@ -209,49 +257,88 @@ int omap_dm_timers_active(void);
209 257
210struct omap_dm_timer { 258struct omap_dm_timer {
211 unsigned long phys_base; 259 unsigned long phys_base;
260 int id;
212 int irq; 261 int irq;
213#ifdef CONFIG_ARCH_OMAP2PLUS
214 struct clk *iclk, *fclk; 262 struct clk *iclk, *fclk;
215#endif 263
216 void __iomem *io_base; 264 void __iomem *io_base;
265 void __iomem *sys_stat; /* TISTAT timer status */
266 void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */
267 void __iomem *irq_ena; /* irq enable */
268 void __iomem *irq_dis; /* irq disable, only on v2 ip */
269 void __iomem *pend; /* write pending */
270 void __iomem *func_base; /* function register base */
271
217 unsigned long rate; 272 unsigned long rate;
218 unsigned reserved:1; 273 unsigned reserved:1;
219 unsigned enabled:1;
220 unsigned posted:1; 274 unsigned posted:1;
275 struct timer_regs context;
276 bool loses_context;
277 int ctx_loss_count;
278 int revision;
279 struct platform_device *pdev;
280 struct list_head node;
281
282 u32 (*get_context_loss_count)(struct device *dev);
221}; 283};
222 284
223extern u32 sys_timer_reserved; 285int omap_dm_timer_prepare(struct omap_dm_timer *timer);
224void omap_dm_timer_prepare(struct omap_dm_timer *timer);
225 286
226static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg, 287static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
227 int posted) 288 int posted)
228{ 289{
229 if (posted) 290 if (posted)
230 while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)) 291 while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
231 & (reg >> WPSHIFT))
232 cpu_relax(); 292 cpu_relax();
233 293
234 return __raw_readl(base + (reg & 0xff)); 294 return __raw_readl(timer->func_base + (reg & 0xff));
235} 295}
236 296
237static inline void __omap_dm_timer_write(void __iomem *base, u32 reg, u32 val, 297static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
238 int posted) 298 u32 reg, u32 val, int posted)
239{ 299{
240 if (posted) 300 if (posted)
241 while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)) 301 while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
242 & (reg >> WPSHIFT))
243 cpu_relax(); 302 cpu_relax();
244 303
245 __raw_writel(val, base + (reg & 0xff)); 304 __raw_writel(val, timer->func_base + (reg & 0xff));
305}
306
307static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
308{
309 u32 tidr;
310
311 /* Assume v1 ip if bits [31:16] are zero */
312 tidr = __raw_readl(timer->io_base);
313 if (!(tidr >> 16)) {
314 timer->revision = 1;
315 timer->sys_stat = timer->io_base +
316 OMAP_TIMER_V1_SYS_STAT_OFFSET;
317 timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
318 timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
319 timer->irq_dis = 0;
320 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
321 timer->func_base = timer->io_base;
322 } else {
323 timer->revision = 2;
324 timer->sys_stat = 0;
325 timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
326 timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
327 timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
328 timer->pend = timer->io_base +
329 _OMAP_TIMER_WRITE_PEND_OFFSET +
330 OMAP_TIMER_V2_FUNC_OFFSET;
331 timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
332 }
246} 333}
247 334
248/* Assumes the source clock has been set by caller */ 335/* Assumes the source clock has been set by caller */
249static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle, 336static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
250 int wakeup) 337 int autoidle, int wakeup)
251{ 338{
252 u32 l; 339 u32 l;
253 340
254 l = __omap_dm_timer_read(base, OMAP_TIMER_OCP_CFG_REG, 0); 341 l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
255 l |= 0x02 << 3; /* Set to smart-idle mode */ 342 l |= 0x02 << 3; /* Set to smart-idle mode */
256 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */ 343 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
257 344
@@ -261,10 +348,10 @@ static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle,
261 if (wakeup) 348 if (wakeup)
262 l |= 1 << 2; 349 l |= 1 << 2;
263 350
264 __omap_dm_timer_write(base, OMAP_TIMER_OCP_CFG_REG, l, 0); 351 __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
265 352
266 /* Match hardware reset default of posted mode */ 353 /* Match hardware reset default of posted mode */
267 __omap_dm_timer_write(base, OMAP_TIMER_IF_CTRL_REG, 354 __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
268 OMAP_TIMER_CTRL_POSTED, 0); 355 OMAP_TIMER_CTRL_POSTED, 0);
269} 356}
270 357
@@ -286,18 +373,18 @@ static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
286 return ret; 373 return ret;
287} 374}
288 375
289static inline void __omap_dm_timer_stop(void __iomem *base, int posted, 376static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
290 unsigned long rate) 377 int posted, unsigned long rate)
291{ 378{
292 u32 l; 379 u32 l;
293 380
294 l = __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted); 381 l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
295 if (l & OMAP_TIMER_CTRL_ST) { 382 if (l & OMAP_TIMER_CTRL_ST) {
296 l &= ~0x1; 383 l &= ~0x1;
297 __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, l, posted); 384 __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
298#ifdef CONFIG_ARCH_OMAP2PLUS 385#ifdef CONFIG_ARCH_OMAP2PLUS
299 /* Readback to make sure write has completed */ 386 /* Readback to make sure write has completed */
300 __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted); 387 __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
301 /* 388 /*
302 * Wait for functional clock period x 3.5 to make sure that 389 * Wait for functional clock period x 3.5 to make sure that
303 * timer is stopped 390 * timer is stopped
@@ -307,34 +394,34 @@ static inline void __omap_dm_timer_stop(void __iomem *base, int posted,
307 } 394 }
308 395
309 /* Ack possibly pending interrupt */ 396 /* Ack possibly pending interrupt */
310 __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG, 397 __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
311 OMAP_TIMER_INT_OVERFLOW, 0);
312} 398}
313 399
314static inline void __omap_dm_timer_load_start(void __iomem *base, u32 ctrl, 400static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
315 unsigned int load, int posted) 401 u32 ctrl, unsigned int load,
402 int posted)
316{ 403{
317 __omap_dm_timer_write(base, OMAP_TIMER_COUNTER_REG, load, posted); 404 __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
318 __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, ctrl, posted); 405 __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
319} 406}
320 407
321static inline void __omap_dm_timer_int_enable(void __iomem *base, 408static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
322 unsigned int value) 409 unsigned int value)
323{ 410{
324 __omap_dm_timer_write(base, OMAP_TIMER_INT_EN_REG, value, 0); 411 __raw_writel(value, timer->irq_ena);
325 __omap_dm_timer_write(base, OMAP_TIMER_WAKEUP_EN_REG, value, 0); 412 __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
326} 413}
327 414
328static inline unsigned int __omap_dm_timer_read_counter(void __iomem *base, 415static inline unsigned int
329 int posted) 416__omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
330{ 417{
331 return __omap_dm_timer_read(base, OMAP_TIMER_COUNTER_REG, posted); 418 return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
332} 419}
333 420
334static inline void __omap_dm_timer_write_status(void __iomem *base, 421static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
335 unsigned int value) 422 unsigned int value)
336{ 423{
337 __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG, value, 0); 424 __raw_writel(value, timer->irq_stat);
338} 425}
339 426
340#endif /* __ASM_ARCH_DMTIMER_H */ 427#endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index ebe67ea8d068..a93a00db93da 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -300,7 +300,7 @@ static inline void omap44xx_map_common_io(void)
300#endif 300#endif
301 301
302extern void omap2_init_common_infrastructure(void); 302extern void omap2_init_common_infrastructure(void);
303extern void omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, 303extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
304 struct omap_sdrc_params *sdrc_cs1); 304 struct omap_sdrc_params *sdrc_cs1);
305 305
306#define __arch_ioremap omap_ioremap 306#define __arch_ioremap omap_ioremap
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 174f1b9c8c03..a1d79ee19250 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -25,16 +25,17 @@ struct iotlb_entry {
25 }; 25 };
26}; 26};
27 27
28struct iommu { 28struct omap_iommu {
29 const char *name; 29 const char *name;
30 struct module *owner; 30 struct module *owner;
31 struct clk *clk; 31 struct clk *clk;
32 void __iomem *regbase; 32 void __iomem *regbase;
33 struct device *dev; 33 struct device *dev;
34 void *isr_priv; 34 void *isr_priv;
35 struct iommu_domain *domain;
35 36
36 unsigned int refcount; 37 unsigned int refcount;
37 struct mutex iommu_lock; /* global for this whole object */ 38 spinlock_t iommu_lock; /* global for this whole object */
38 39
39 /* 40 /*
40 * We don't change iopgd for a situation like pgd for a task, 41 * We don't change iopgd for a situation like pgd for a task,
@@ -48,8 +49,6 @@ struct iommu {
48 struct list_head mmap; 49 struct list_head mmap;
49 struct mutex mmap_lock; /* protect mmap */ 50 struct mutex mmap_lock; /* protect mmap */
50 51
51 int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, void *priv);
52
53 void *ctx; /* iommu context: registres saved area */ 52 void *ctx; /* iommu context: registres saved area */
54 u32 da_start; 53 u32 da_start;
55 u32 da_end; 54 u32 da_end;
@@ -81,25 +80,27 @@ struct iotlb_lock {
81struct iommu_functions { 80struct iommu_functions {
82 unsigned long version; 81 unsigned long version;
83 82
84 int (*enable)(struct iommu *obj); 83 int (*enable)(struct omap_iommu *obj);
85 void (*disable)(struct iommu *obj); 84 void (*disable)(struct omap_iommu *obj);
86 void (*set_twl)(struct iommu *obj, bool on); 85 void (*set_twl)(struct omap_iommu *obj, bool on);
87 u32 (*fault_isr)(struct iommu *obj, u32 *ra); 86 u32 (*fault_isr)(struct omap_iommu *obj, u32 *ra);
88 87
89 void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr); 88 void (*tlb_read_cr)(struct omap_iommu *obj, struct cr_regs *cr);
90 void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr); 89 void (*tlb_load_cr)(struct omap_iommu *obj, struct cr_regs *cr);
91 90
92 struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e); 91 struct cr_regs *(*alloc_cr)(struct omap_iommu *obj,
92 struct iotlb_entry *e);
93 int (*cr_valid)(struct cr_regs *cr); 93 int (*cr_valid)(struct cr_regs *cr);
94 u32 (*cr_to_virt)(struct cr_regs *cr); 94 u32 (*cr_to_virt)(struct cr_regs *cr);
95 void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e); 95 void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
96 ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf); 96 ssize_t (*dump_cr)(struct omap_iommu *obj, struct cr_regs *cr,
97 char *buf);
97 98
98 u32 (*get_pte_attr)(struct iotlb_entry *e); 99 u32 (*get_pte_attr)(struct iotlb_entry *e);
99 100
100 void (*save_ctx)(struct iommu *obj); 101 void (*save_ctx)(struct omap_iommu *obj);
101 void (*restore_ctx)(struct iommu *obj); 102 void (*restore_ctx)(struct omap_iommu *obj);
102 ssize_t (*dump_ctx)(struct iommu *obj, char *buf, ssize_t len); 103 ssize_t (*dump_ctx)(struct omap_iommu *obj, char *buf, ssize_t len);
103}; 104};
104 105
105struct iommu_platform_data { 106struct iommu_platform_data {
@@ -150,40 +151,31 @@ struct iommu_platform_data {
150/* 151/*
151 * global functions 152 * global functions
152 */ 153 */
153extern u32 iommu_arch_version(void); 154extern u32 omap_iommu_arch_version(void);
154 155
155extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e); 156extern void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
156extern u32 iotlb_cr_to_virt(struct cr_regs *cr); 157
157 158extern int
158extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e); 159omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e);
159extern void iommu_set_twl(struct iommu *obj, bool on); 160
160extern void flush_iotlb_page(struct iommu *obj, u32 da); 161extern int omap_iommu_set_isr(const char *name,
161extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end); 162 int (*isr)(struct omap_iommu *obj, u32 da, u32 iommu_errs,
162extern void flush_iotlb_all(struct iommu *obj);
163
164extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
165extern void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd,
166 u32 **ppte);
167extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
168
169extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end);
170extern struct iommu *iommu_get(const char *name);
171extern void iommu_put(struct iommu *obj);
172extern int iommu_set_isr(const char *name,
173 int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs,
174 void *priv), 163 void *priv),
175 void *isr_priv); 164 void *isr_priv);
176 165
177extern void iommu_save_ctx(struct iommu *obj); 166extern void omap_iommu_save_ctx(struct omap_iommu *obj);
178extern void iommu_restore_ctx(struct iommu *obj); 167extern void omap_iommu_restore_ctx(struct omap_iommu *obj);
179 168
180extern int install_iommu_arch(const struct iommu_functions *ops); 169extern int omap_install_iommu_arch(const struct iommu_functions *ops);
181extern void uninstall_iommu_arch(const struct iommu_functions *ops); 170extern void omap_uninstall_iommu_arch(const struct iommu_functions *ops);
182 171
183extern int foreach_iommu_device(void *data, 172extern int omap_foreach_iommu_device(void *data,
184 int (*fn)(struct device *, void *)); 173 int (*fn)(struct device *, void *));
185 174
186extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len); 175extern ssize_t
187extern size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t len); 176omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len);
177extern size_t
178omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len);
179struct device *omap_find_iommu_device(const char *name);
188 180
189#endif /* __MACH_IOMMU_H */ 181#endif /* __MACH_IOMMU_H */
diff --git a/arch/arm/plat-omap/include/plat/iommu2.h b/arch/arm/plat-omap/include/plat/iommu2.h
index 10ad05f410e9..d4116b595e40 100644
--- a/arch/arm/plat-omap/include/plat/iommu2.h
+++ b/arch/arm/plat-omap/include/plat/iommu2.h
@@ -83,12 +83,12 @@
83/* 83/*
84 * register accessors 84 * register accessors
85 */ 85 */
86static inline u32 iommu_read_reg(struct iommu *obj, size_t offs) 86static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
87{ 87{
88 return __raw_readl(obj->regbase + offs); 88 return __raw_readl(obj->regbase + offs);
89} 89}
90 90
91static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs) 91static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
92{ 92{
93 __raw_writel(val, obj->regbase + offs); 93 __raw_writel(val, obj->regbase + offs);
94} 94}
diff --git a/arch/arm/plat-omap/include/plat/iopgtable.h b/arch/arm/plat-omap/include/plat/iopgtable.h
new file mode 100644
index 000000000000..66a813977d52
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/iopgtable.h
@@ -0,0 +1,120 @@
1/*
2 * omap iommu: pagetable definitions
3 *
4 * Copyright (C) 2008-2010 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __PLAT_OMAP_IOMMU_H
14#define __PLAT_OMAP_IOMMU_H
15
16/*
17 * "L2 table" address mask and size definitions.
18 */
19#define IOPGD_SHIFT 20
20#define IOPGD_SIZE (1UL << IOPGD_SHIFT)
21#define IOPGD_MASK (~(IOPGD_SIZE - 1))
22
23/*
24 * "section" address mask and size definitions.
25 */
26#define IOSECTION_SHIFT 20
27#define IOSECTION_SIZE (1UL << IOSECTION_SHIFT)
28#define IOSECTION_MASK (~(IOSECTION_SIZE - 1))
29
30/*
31 * "supersection" address mask and size definitions.
32 */
33#define IOSUPER_SHIFT 24
34#define IOSUPER_SIZE (1UL << IOSUPER_SHIFT)
35#define IOSUPER_MASK (~(IOSUPER_SIZE - 1))
36
37#define PTRS_PER_IOPGD (1UL << (32 - IOPGD_SHIFT))
38#define IOPGD_TABLE_SIZE (PTRS_PER_IOPGD * sizeof(u32))
39
40/*
41 * "small page" address mask and size definitions.
42 */
43#define IOPTE_SHIFT 12
44#define IOPTE_SIZE (1UL << IOPTE_SHIFT)
45#define IOPTE_MASK (~(IOPTE_SIZE - 1))
46
47/*
48 * "large page" address mask and size definitions.
49 */
50#define IOLARGE_SHIFT 16
51#define IOLARGE_SIZE (1UL << IOLARGE_SHIFT)
52#define IOLARGE_MASK (~(IOLARGE_SIZE - 1))
53
54#define PTRS_PER_IOPTE (1UL << (IOPGD_SHIFT - IOPTE_SHIFT))
55#define IOPTE_TABLE_SIZE (PTRS_PER_IOPTE * sizeof(u32))
56
57#define IOPAGE_MASK IOPTE_MASK
58
59/**
60 * omap_iommu_translate() - va to pa translation
61 * @d: omap iommu descriptor
62 * @va: virtual address
63 * @mask: omap iommu descriptor mask
64 *
65 * va to pa translation
66 */
67static inline phys_addr_t omap_iommu_translate(u32 d, u32 va, u32 mask)
68{
69 return (d & mask) | (va & (~mask));
70}
71
72/*
73 * some descriptor attributes.
74 */
75#define IOPGD_TABLE (1 << 0)
76#define IOPGD_SECTION (2 << 0)
77#define IOPGD_SUPER (1 << 18 | 2 << 0)
78
79#define iopgd_is_table(x) (((x) & 3) == IOPGD_TABLE)
80#define iopgd_is_section(x) (((x) & (1 << 18 | 3)) == IOPGD_SECTION)
81#define iopgd_is_super(x) (((x) & (1 << 18 | 3)) == IOPGD_SUPER)
82
83#define IOPTE_SMALL (2 << 0)
84#define IOPTE_LARGE (1 << 0)
85
86#define iopte_is_small(x) (((x) & 2) == IOPTE_SMALL)
87#define iopte_is_large(x) (((x) & 3) == IOPTE_LARGE)
88
89/* to find an entry in a page-table-directory */
90#define iopgd_index(da) (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1))
91#define iopgd_offset(obj, da) ((obj)->iopgd + iopgd_index(da))
92
93#define iopgd_page_paddr(iopgd) (*iopgd & ~((1 << 10) - 1))
94#define iopgd_page_vaddr(iopgd) ((u32 *)phys_to_virt(iopgd_page_paddr(iopgd)))
95
96/* to find an entry in the second-level page table. */
97#define iopte_index(da) (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1))
98#define iopte_offset(iopgd, da) (iopgd_page_vaddr(iopgd) + iopte_index(da))
99
100static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa,
101 u32 flags)
102{
103 memset(e, 0, sizeof(*e));
104
105 e->da = da;
106 e->pa = pa;
107 e->valid = 1;
108 /* FIXME: add OMAP1 support */
109 e->pgsz = flags & MMU_CAM_PGSZ_MASK;
110 e->endian = flags & MMU_RAM_ENDIAN_MASK;
111 e->elsz = flags & MMU_RAM_ELSZ_MASK;
112 e->mixed = flags & MMU_RAM_MIXED_MASK;
113
114 return iopgsz_to_bytes(e->pgsz);
115}
116
117#define to_iommu(dev) \
118 (struct omap_iommu *)platform_get_drvdata(to_platform_device(dev))
119
120#endif /* __PLAT_OMAP_IOMMU_H */
diff --git a/arch/arm/plat-omap/include/plat/iovmm.h b/arch/arm/plat-omap/include/plat/iovmm.h
index e992b9655fbc..6af1a91c0f36 100644
--- a/arch/arm/plat-omap/include/plat/iovmm.h
+++ b/arch/arm/plat-omap/include/plat/iovmm.h
@@ -13,8 +13,10 @@
13#ifndef __IOMMU_MMAP_H 13#ifndef __IOMMU_MMAP_H
14#define __IOMMU_MMAP_H 14#define __IOMMU_MMAP_H
15 15
16#include <linux/iommu.h>
17
16struct iovm_struct { 18struct iovm_struct {
17 struct iommu *iommu; /* iommu object which this belongs to */ 19 struct omap_iommu *iommu; /* iommu object which this belongs to */
18 u32 da_start; /* area definition */ 20 u32 da_start; /* area definition */
19 u32 da_end; 21 u32 da_end;
20 u32 flags; /* IOVMF_: see below */ 22 u32 flags; /* IOVMF_: see below */
@@ -70,20 +72,18 @@ struct iovm_struct {
70#define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT)) 72#define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT))
71 73
72 74
73extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da); 75extern struct iovm_struct *omap_find_iovm_area(struct omap_iommu *obj, u32 da);
74extern u32 iommu_vmap(struct iommu *obj, u32 da, 76extern u32
77omap_iommu_vmap(struct iommu_domain *domain, struct omap_iommu *obj, u32 da,
75 const struct sg_table *sgt, u32 flags); 78 const struct sg_table *sgt, u32 flags);
76extern struct sg_table *iommu_vunmap(struct iommu *obj, u32 da); 79extern struct sg_table *omap_iommu_vunmap(struct iommu_domain *domain,
77extern u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, 80 struct omap_iommu *obj, u32 da);
78 u32 flags); 81extern u32
79extern void iommu_vfree(struct iommu *obj, const u32 da); 82omap_iommu_vmalloc(struct iommu_domain *domain, struct omap_iommu *obj,
80extern u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes, 83 u32 da, size_t bytes, u32 flags);
81 u32 flags); 84extern void
82extern void iommu_kunmap(struct iommu *obj, u32 da); 85omap_iommu_vfree(struct iommu_domain *domain, struct omap_iommu *obj,
83extern u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, 86 const u32 da);
84 u32 flags); 87extern void *omap_da_to_va(struct omap_iommu *obj, u32 da);
85extern void iommu_kfree(struct iommu *obj, u32 da);
86
87extern void *da_to_va(struct iommu *obj, u32 da);
88 88
89#endif /* __IOMMU_MMAP_H */ 89#endif /* __IOMMU_MMAP_H */
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 9882c657b2d4..8fa74e2c9d6e 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -25,9 +25,7 @@
25#define __ASM_ARCH_OMAP_MCBSP_H 25#define __ASM_ARCH_OMAP_MCBSP_H
26 26
27#include <linux/spinlock.h> 27#include <linux/spinlock.h>
28 28#include <linux/clk.h>
29#include <mach/hardware.h>
30#include <plat/clock.h>
31 29
32/* macro for building platform_device for McBSP ports */ 30/* macro for building platform_device for McBSP ports */
33#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \ 31#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \
@@ -40,104 +38,60 @@ static struct platform_device omap_mcbsp##port_nr = { \
40#define MCBSP_CONFIG_TYPE3 0x3 38#define MCBSP_CONFIG_TYPE3 0x3
41#define MCBSP_CONFIG_TYPE4 0x4 39#define MCBSP_CONFIG_TYPE4 0x4
42 40
43#define OMAP7XX_MCBSP1_BASE 0xfffb1000 41/* McBSP register numbers. Register address offset = num * reg_step */
44#define OMAP7XX_MCBSP2_BASE 0xfffb1800 42enum {
45 43 /* Common registers */
46#define OMAP1510_MCBSP1_BASE 0xe1011800 44 OMAP_MCBSP_REG_SPCR2 = 4,
47#define OMAP1510_MCBSP2_BASE 0xfffb1000 45 OMAP_MCBSP_REG_SPCR1,
48#define OMAP1510_MCBSP3_BASE 0xe1017000 46 OMAP_MCBSP_REG_RCR2,
49 47 OMAP_MCBSP_REG_RCR1,
50#define OMAP1610_MCBSP1_BASE 0xe1011800 48 OMAP_MCBSP_REG_XCR2,
51#define OMAP1610_MCBSP2_BASE 0xfffb1000 49 OMAP_MCBSP_REG_XCR1,
52#define OMAP1610_MCBSP3_BASE 0xe1017000 50 OMAP_MCBSP_REG_SRGR2,
53 51 OMAP_MCBSP_REG_SRGR1,
54#ifdef CONFIG_ARCH_OMAP1 52 OMAP_MCBSP_REG_MCR2,
55 53 OMAP_MCBSP_REG_MCR1,
56#define OMAP_MCBSP_REG_DRR2 0x00 54 OMAP_MCBSP_REG_RCERA,
57#define OMAP_MCBSP_REG_DRR1 0x02 55 OMAP_MCBSP_REG_RCERB,
58#define OMAP_MCBSP_REG_DXR2 0x04 56 OMAP_MCBSP_REG_XCERA,
59#define OMAP_MCBSP_REG_DXR1 0x06 57 OMAP_MCBSP_REG_XCERB,
60#define OMAP_MCBSP_REG_DRR 0x02 58 OMAP_MCBSP_REG_PCR0,
61#define OMAP_MCBSP_REG_DXR 0x06 59 OMAP_MCBSP_REG_RCERC,
62#define OMAP_MCBSP_REG_SPCR2 0x08 60 OMAP_MCBSP_REG_RCERD,
63#define OMAP_MCBSP_REG_SPCR1 0x0a 61 OMAP_MCBSP_REG_XCERC,
64#define OMAP_MCBSP_REG_RCR2 0x0c 62 OMAP_MCBSP_REG_XCERD,
65#define OMAP_MCBSP_REG_RCR1 0x0e 63 OMAP_MCBSP_REG_RCERE,
66#define OMAP_MCBSP_REG_XCR2 0x10 64 OMAP_MCBSP_REG_RCERF,
67#define OMAP_MCBSP_REG_XCR1 0x12 65 OMAP_MCBSP_REG_XCERE,
68#define OMAP_MCBSP_REG_SRGR2 0x14 66 OMAP_MCBSP_REG_XCERF,
69#define OMAP_MCBSP_REG_SRGR1 0x16 67 OMAP_MCBSP_REG_RCERG,
70#define OMAP_MCBSP_REG_MCR2 0x18 68 OMAP_MCBSP_REG_RCERH,
71#define OMAP_MCBSP_REG_MCR1 0x1a 69 OMAP_MCBSP_REG_XCERG,
72#define OMAP_MCBSP_REG_RCERA 0x1c 70 OMAP_MCBSP_REG_XCERH,
73#define OMAP_MCBSP_REG_RCERB 0x1e 71
74#define OMAP_MCBSP_REG_XCERA 0x20 72 /* OMAP1-OMAP2420 registers */
75#define OMAP_MCBSP_REG_XCERB 0x22 73 OMAP_MCBSP_REG_DRR2 = 0,
76#define OMAP_MCBSP_REG_PCR0 0x24 74 OMAP_MCBSP_REG_DRR1,
77#define OMAP_MCBSP_REG_RCERC 0x26 75 OMAP_MCBSP_REG_DXR2,
78#define OMAP_MCBSP_REG_RCERD 0x28 76 OMAP_MCBSP_REG_DXR1,
79#define OMAP_MCBSP_REG_XCERC 0x2A 77
80#define OMAP_MCBSP_REG_XCERD 0x2C 78 /* OMAP2430 and onwards */
81#define OMAP_MCBSP_REG_RCERE 0x2E 79 OMAP_MCBSP_REG_DRR = 0,
82#define OMAP_MCBSP_REG_RCERF 0x30 80 OMAP_MCBSP_REG_DXR = 2,
83#define OMAP_MCBSP_REG_XCERE 0x32 81 OMAP_MCBSP_REG_SYSCON = 35,
84#define OMAP_MCBSP_REG_XCERF 0x34 82 OMAP_MCBSP_REG_THRSH2,
85#define OMAP_MCBSP_REG_RCERG 0x36 83 OMAP_MCBSP_REG_THRSH1,
86#define OMAP_MCBSP_REG_RCERH 0x38 84 OMAP_MCBSP_REG_IRQST = 40,
87#define OMAP_MCBSP_REG_XCERG 0x3A 85 OMAP_MCBSP_REG_IRQEN,
88#define OMAP_MCBSP_REG_XCERH 0x3C 86 OMAP_MCBSP_REG_WAKEUPEN,
89 87 OMAP_MCBSP_REG_XCCR,
90/* Dummy defines, these are not available on omap1 */ 88 OMAP_MCBSP_REG_RCCR,
91#define OMAP_MCBSP_REG_XCCR 0x00 89 OMAP_MCBSP_REG_XBUFFSTAT,
92#define OMAP_MCBSP_REG_RCCR 0x00 90 OMAP_MCBSP_REG_RBUFFSTAT,
93 91 OMAP_MCBSP_REG_SSELCR,
94#else 92};
95
96#define OMAP_MCBSP_REG_DRR2 0x00
97#define OMAP_MCBSP_REG_DRR1 0x04
98#define OMAP_MCBSP_REG_DXR2 0x08
99#define OMAP_MCBSP_REG_DXR1 0x0C
100#define OMAP_MCBSP_REG_DRR 0x00
101#define OMAP_MCBSP_REG_DXR 0x08
102#define OMAP_MCBSP_REG_SPCR2 0x10
103#define OMAP_MCBSP_REG_SPCR1 0x14
104#define OMAP_MCBSP_REG_RCR2 0x18
105#define OMAP_MCBSP_REG_RCR1 0x1C
106#define OMAP_MCBSP_REG_XCR2 0x20
107#define OMAP_MCBSP_REG_XCR1 0x24
108#define OMAP_MCBSP_REG_SRGR2 0x28
109#define OMAP_MCBSP_REG_SRGR1 0x2C
110#define OMAP_MCBSP_REG_MCR2 0x30
111#define OMAP_MCBSP_REG_MCR1 0x34
112#define OMAP_MCBSP_REG_RCERA 0x38
113#define OMAP_MCBSP_REG_RCERB 0x3C
114#define OMAP_MCBSP_REG_XCERA 0x40
115#define OMAP_MCBSP_REG_XCERB 0x44
116#define OMAP_MCBSP_REG_PCR0 0x48
117#define OMAP_MCBSP_REG_RCERC 0x4C
118#define OMAP_MCBSP_REG_RCERD 0x50
119#define OMAP_MCBSP_REG_XCERC 0x54
120#define OMAP_MCBSP_REG_XCERD 0x58
121#define OMAP_MCBSP_REG_RCERE 0x5C
122#define OMAP_MCBSP_REG_RCERF 0x60
123#define OMAP_MCBSP_REG_XCERE 0x64
124#define OMAP_MCBSP_REG_XCERF 0x68
125#define OMAP_MCBSP_REG_RCERG 0x6C
126#define OMAP_MCBSP_REG_RCERH 0x70
127#define OMAP_MCBSP_REG_XCERG 0x74
128#define OMAP_MCBSP_REG_XCERH 0x78
129#define OMAP_MCBSP_REG_SYSCON 0x8C
130#define OMAP_MCBSP_REG_THRSH2 0x90
131#define OMAP_MCBSP_REG_THRSH1 0x94
132#define OMAP_MCBSP_REG_IRQST 0xA0
133#define OMAP_MCBSP_REG_IRQEN 0xA4
134#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
135#define OMAP_MCBSP_REG_XCCR 0xAC
136#define OMAP_MCBSP_REG_RCCR 0xB0
137#define OMAP_MCBSP_REG_XBUFFSTAT 0xB4
138#define OMAP_MCBSP_REG_RBUFFSTAT 0xB8
139#define OMAP_MCBSP_REG_SSELCR 0xBC
140 93
94/* OMAP3 sidetone control registers */
141#define OMAP_ST_REG_REV 0x00 95#define OMAP_ST_REG_REV 0x00
142#define OMAP_ST_REG_SYSCONFIG 0x10 96#define OMAP_ST_REG_SYSCONFIG 0x10
143#define OMAP_ST_REG_IRQSTATUS 0x18 97#define OMAP_ST_REG_IRQSTATUS 0x18
@@ -146,8 +100,6 @@ static struct platform_device omap_mcbsp##port_nr = { \
146#define OMAP_ST_REG_SFIRCR 0x28 100#define OMAP_ST_REG_SFIRCR 0x28
147#define OMAP_ST_REG_SSELCR 0x2C 101#define OMAP_ST_REG_SSELCR 0x2C
148 102
149#endif
150
151/************************** McBSP SPCR1 bit definitions ***********************/ 103/************************** McBSP SPCR1 bit definitions ***********************/
152#define RRST 0x0001 104#define RRST 0x0001
153#define RRDY 0x0002 105#define RRDY 0x0002
@@ -344,20 +296,20 @@ typedef enum {
344struct omap_mcbsp_ops { 296struct omap_mcbsp_ops {
345 void (*request)(unsigned int); 297 void (*request)(unsigned int);
346 void (*free)(unsigned int); 298 void (*free)(unsigned int);
347 int (*set_clks_src)(u8, u8);
348}; 299};
349 300
350struct omap_mcbsp_platform_data { 301struct omap_mcbsp_platform_data {
351 unsigned long phys_base;
352 u8 dma_rx_sync, dma_tx_sync;
353 u16 rx_irq, tx_irq;
354 struct omap_mcbsp_ops *ops; 302 struct omap_mcbsp_ops *ops;
355#ifdef CONFIG_ARCH_OMAP3
356 /* Sidetone block for McBSP 2 and 3 */
357 unsigned long phys_base_st;
358#endif
359 u16 buffer_size; 303 u16 buffer_size;
360 unsigned int mcbsp_config_type; 304 u8 reg_size;
305 u8 reg_step;
306
307 /* McBSP platform and instance specific features */
308 bool has_wakeup; /* Wakeup capability */
309 bool has_ccr; /* Transceiver has configuration control registers */
310 int (*enable_st_clock)(unsigned int, bool);
311 int (*set_clk_src)(struct device *dev, struct clk *clk, const char *src);
312 int (*mux_signal)(struct device *dev, const char *signal, const char *src);
361}; 313};
362 314
363struct omap_mcbsp_st_data { 315struct omap_mcbsp_st_data {
@@ -389,14 +341,12 @@ struct omap_mcbsp {
389 spinlock_t lock; 341 spinlock_t lock;
390 struct omap_mcbsp_platform_data *pdata; 342 struct omap_mcbsp_platform_data *pdata;
391 struct clk *fclk; 343 struct clk *fclk;
392#ifdef CONFIG_ARCH_OMAP3
393 struct omap_mcbsp_st_data *st_data; 344 struct omap_mcbsp_st_data *st_data;
394 int dma_op_mode; 345 int dma_op_mode;
395 u16 max_tx_thres; 346 u16 max_tx_thres;
396 u16 max_rx_thres; 347 u16 max_rx_thres;
397#endif
398 void *reg_cache; 348 void *reg_cache;
399 unsigned int mcbsp_config_type; 349 int reg_cache_size;
400}; 350};
401 351
402/** 352/**
@@ -408,16 +358,10 @@ struct omap_mcbsp_dev_attr {
408}; 358};
409 359
410extern struct omap_mcbsp **mcbsp_ptr; 360extern struct omap_mcbsp **mcbsp_ptr;
411extern int omap_mcbsp_count, omap_mcbsp_cache_size; 361extern int omap_mcbsp_count;
412
413#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
414#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
415 362
416int omap_mcbsp_init(void); 363int omap_mcbsp_init(void);
417void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
418 struct omap_mcbsp_platform_data *config, int size);
419void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); 364void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
420#ifdef CONFIG_ARCH_OMAP3
421void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); 365void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
422void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold); 366void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
423u16 omap_mcbsp_get_max_tx_threshold(unsigned int id); 367u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
@@ -426,18 +370,6 @@ u16 omap_mcbsp_get_fifo_size(unsigned int id);
426u16 omap_mcbsp_get_tx_delay(unsigned int id); 370u16 omap_mcbsp_get_tx_delay(unsigned int id);
427u16 omap_mcbsp_get_rx_delay(unsigned int id); 371u16 omap_mcbsp_get_rx_delay(unsigned int id);
428int omap_mcbsp_get_dma_op_mode(unsigned int id); 372int omap_mcbsp_get_dma_op_mode(unsigned int id);
429#else
430static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
431{ }
432static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
433{ }
434static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
435static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
436static inline u16 omap_mcbsp_get_fifo_size(unsigned int id) { return 0; }
437static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; }
438static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; }
439static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
440#endif
441int omap_mcbsp_request(unsigned int id); 373int omap_mcbsp_request(unsigned int id);
442void omap_mcbsp_free(unsigned int id); 374void omap_mcbsp_free(unsigned int id);
443void omap_mcbsp_start(unsigned int id, int tx, int rx); 375void omap_mcbsp_start(unsigned int id, int tx, int rx);
@@ -453,21 +385,11 @@ void omap2_mcbsp1_mux_fsr_src(u8 mux);
453int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream); 385int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
454int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream); 386int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
455 387
456#ifdef CONFIG_ARCH_OMAP3
457/* Sidetone specific API */ 388/* Sidetone specific API */
458int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); 389int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
459int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain); 390int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
460int omap_st_enable(unsigned int id); 391int omap_st_enable(unsigned int id);
461int omap_st_disable(unsigned int id); 392int omap_st_disable(unsigned int id);
462int omap_st_is_enabled(unsigned int id); 393int omap_st_is_enabled(unsigned int id);
463#else
464static inline int omap_st_set_chgain(unsigned int id, int channel,
465 s16 chgain) { return 0; }
466static inline int omap_st_get_chgain(unsigned int id, int channel,
467 s16 *chgain) { return 0; }
468static inline int omap_st_enable(unsigned int id) { return 0; }
469static inline int omap_st_disable(unsigned int id) { return 0; }
470static inline int omap_st_is_enabled(unsigned int id) { return 0; }
471#endif
472 394
473#endif 395#endif
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index c7b874186c27..94cf70afb236 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -31,7 +31,24 @@
31 31
32#define OMAP_MMC_MAX_SLOTS 2 32#define OMAP_MMC_MAX_SLOTS 2
33 33
34#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(1) 34/*
35 * struct omap_mmc_dev_attr.flags possibilities
36 *
37 * OMAP_HSMMC_SUPPORTS_DUAL_VOLT: Some HSMMC controller instances can
38 * operate with either 1.8Vdc or 3.0Vdc card voltages; this flag
39 * should be set if this is the case. See for example Section 22.5.3
40 * "MMC/SD/SDIO1 Bus Voltage Selection" of the OMAP34xx Multimedia
41 * Device Silicon Revision 3.1.x Revision ZR (July 2011) (SWPU223R).
42 *
43 * OMAP_HSMMC_BROKEN_MULTIBLOCK_READ: Multiple-block read transfers
44 * don't work correctly on some MMC controller instances on some
45 * OMAP3 SoCs; this flag should be set if this is the case. See
46 * for example Advisory 2.1.1.128 "MMC: Multiple Block Read
47 * Operation Issue" in _OMAP3530/3525/3515/3503 Silicon Errata_
48 * Revision F (October 2010) (SPRZ278F).
49 */
50#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
51#define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ BIT(1)
35 52
36struct omap_mmc_dev_attr { 53struct omap_mmc_dev_attr {
37 u8 flags; 54 u8 flags;
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index ee405b36df4b..d4d9b96f961e 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -68,7 +68,7 @@ extern struct device omap_device_parent;
68 * 68 *
69 */ 69 */
70struct omap_device { 70struct omap_device {
71 struct platform_device pdev; 71 struct platform_device *pdev;
72 struct omap_hwmod **hwmods; 72 struct omap_hwmod **hwmods;
73 struct omap_device_pm_latency *pm_lats; 73 struct omap_device_pm_latency *pm_lats;
74 u32 dev_wakeup_lat; 74 u32 dev_wakeup_lat;
@@ -88,24 +88,18 @@ int omap_device_shutdown(struct platform_device *pdev);
88 88
89/* Core code interface */ 89/* Core code interface */
90 90
91int omap_device_count_resources(struct omap_device *od); 91struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
92int omap_device_fill_resources(struct omap_device *od, struct resource *res);
93
94struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
95 struct omap_hwmod *oh, void *pdata, 92 struct omap_hwmod *oh, void *pdata,
96 int pdata_len, 93 int pdata_len,
97 struct omap_device_pm_latency *pm_lats, 94 struct omap_device_pm_latency *pm_lats,
98 int pm_lats_cnt, int is_early_device); 95 int pm_lats_cnt, int is_early_device);
99 96
100struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, 97struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
101 struct omap_hwmod **oh, int oh_cnt, 98 struct omap_hwmod **oh, int oh_cnt,
102 void *pdata, int pdata_len, 99 void *pdata, int pdata_len,
103 struct omap_device_pm_latency *pm_lats, 100 struct omap_device_pm_latency *pm_lats,
104 int pm_lats_cnt, int is_early_device); 101 int pm_lats_cnt, int is_early_device);
105 102
106int omap_device_register(struct omap_device *od);
107int omap_early_device_register(struct omap_device *od);
108
109void __iomem *omap_device_get_rt_va(struct omap_device *od); 103void __iomem *omap_device_get_rt_va(struct omap_device *od);
110 104
111/* OMAP PM interface */ 105/* OMAP PM interface */
@@ -122,11 +116,6 @@ int omap_device_enable_hwmods(struct omap_device *od);
122int omap_device_disable_clocks(struct omap_device *od); 116int omap_device_disable_clocks(struct omap_device *od);
123int omap_device_enable_clocks(struct omap_device *od); 117int omap_device_enable_clocks(struct omap_device *od);
124 118
125static inline void omap_device_disable_idle_on_suspend(struct omap_device *od)
126{
127 od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
128}
129
130/* 119/*
131 * Entries should be kept in latency order ascending 120 * Entries should be kept in latency order ascending
132 * 121 *
@@ -157,6 +146,17 @@ struct omap_device_pm_latency {
157#define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1) 146#define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1)
158 147
159/* Get omap_device pointer from platform_device pointer */ 148/* Get omap_device pointer from platform_device pointer */
160#define to_omap_device(x) container_of((x), struct omap_device, pdev) 149static inline struct omap_device *to_omap_device(struct platform_device *pdev)
150{
151 return pdev ? pdev->archdata.od : NULL;
152}
153
154static inline
155void omap_device_disable_idle_on_suspend(struct platform_device *pdev)
156{
157 struct omap_device *od = to_omap_device(pdev);
158
159 od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
160}
161 161
162#endif 162#endif
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 0e329ca88a70..5419f1a2aaa4 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -496,7 +496,6 @@ struct omap_hwmod_class {
496 * @_state: internal-use hwmod state 496 * @_state: internal-use hwmod state
497 * @_postsetup_state: internal-use state to leave the hwmod in after _setup() 497 * @_postsetup_state: internal-use state to leave the hwmod in after _setup()
498 * @flags: hwmod flags (documented below) 498 * @flags: hwmod flags (documented below)
499 * @omap_chip: OMAP chips this hwmod is present on
500 * @_lock: spinlock serializing operations on this hwmod 499 * @_lock: spinlock serializing operations on this hwmod
501 * @node: list node for hwmod list (internal use) 500 * @node: list node for hwmod list (internal use)
502 * 501 *
@@ -526,7 +525,6 @@ struct omap_hwmod {
526 char *clkdm_name; 525 char *clkdm_name;
527 struct clockdomain *clkdm; 526 struct clockdomain *clkdm;
528 char *vdd_name; 527 char *vdd_name;
529 struct voltagedomain *voltdm;
530 struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ 528 struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
531 struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ 529 struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */
532 void *dev_attr; 530 void *dev_attr;
@@ -545,7 +543,6 @@ struct omap_hwmod {
545 u8 _int_flags; 543 u8 _int_flags;
546 u8 _state; 544 u8 _state;
547 u8 _postsetup_state; 545 u8 _postsetup_state;
548 const struct omap_chip_id omap_chip;
549}; 546};
550 547
551int omap_hwmod_register(struct omap_hwmod **ohs); 548int omap_hwmod_register(struct omap_hwmod **ohs);
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
new file mode 100644
index 000000000000..0a6a482ec014
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/voltage.h
@@ -0,0 +1,20 @@
1/*
2 * OMAP Voltage Management Routines
3 *
4 * Copyright (C) 2011, Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ARCH_ARM_OMAP_VOLTAGE_H
12#define __ARCH_ARM_OMAP_VOLTAGE_H
13
14struct voltagedomain;
15
16struct voltagedomain *voltdm_lookup(const char *name);
17int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
18unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
19
20#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-22 01:57:33 -0500