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-rw-r--r--arch/arm/plat-omap/include/plat/blizzard.h12
-rw-r--r--arch/arm/plat-omap/include/plat/board-ams-delta.h76
-rw-r--r--arch/arm/plat-omap/include/plat/board-sx1.h52
-rw-r--r--arch/arm/plat-omap/include/plat/board-voiceblue.h19
-rw-r--r--arch/arm/plat-omap/include/plat/board.h160
-rw-r--r--arch/arm/plat-omap/include/plat/clkdev.h13
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h163
-rw-r--r--arch/arm/plat-omap/include/plat/clockdomain.h111
-rw-r--r--arch/arm/plat-omap/include/plat/common.h74
-rw-r--r--arch/arm/plat-omap/include/plat/control.h288
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h426
-rw-r--r--arch/arm/plat-omap/include/plat/dma.h680
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h84
-rw-r--r--arch/arm/plat-omap/include/plat/dsp_common.h40
-rw-r--r--arch/arm/plat-omap/include/plat/fpga.h197
-rw-r--r--arch/arm/plat-omap/include/plat/gpio-switch.h54
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h129
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc-smc91x.h42
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc.h115
-rw-r--r--arch/arm/plat-omap/include/plat/hardware.h290
-rw-r--r--arch/arm/plat-omap/include/plat/hwa742.h8
-rw-r--r--arch/arm/plat-omap/include/plat/io.h287
-rw-r--r--arch/arm/plat-omap/include/plat/iommu.h168
-rw-r--r--arch/arm/plat-omap/include/plat/iommu2.h96
-rw-r--r--arch/arm/plat-omap/include/plat/iovmm.h94
-rw-r--r--arch/arm/plat-omap/include/plat/irda.h33
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h492
-rw-r--r--arch/arm/plat-omap/include/plat/keypad.h45
-rw-r--r--arch/arm/plat-omap/include/plat/lcd_mipid.h29
-rw-r--r--arch/arm/plat-omap/include/plat/led.h24
-rw-r--r--arch/arm/plat-omap/include/plat/mailbox.h96
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h462
-rw-r--r--arch/arm/plat-omap/include/plat/mcspi.h15
-rw-r--r--arch/arm/plat-omap/include/plat/memory.h96
-rw-r--r--arch/arm/plat-omap/include/plat/menelaus.h49
-rw-r--r--arch/arm/plat-omap/include/plat/mmc.h157
-rw-r--r--arch/arm/plat-omap/include/plat/mux.h864
-rw-r--r--arch/arm/plat-omap/include/plat/nand.h24
-rw-r--r--arch/arm/plat-omap/include/plat/omap-alsa.h123
-rw-r--r--arch/arm/plat-omap/include/plat/omap-pm.h301
-rw-r--r--arch/arm/plat-omap/include/plat/omap1510.h50
-rw-r--r--arch/arm/plat-omap/include/plat/omap16xx.h202
-rw-r--r--arch/arm/plat-omap/include/plat/omap24xx.h89
-rw-r--r--arch/arm/plat-omap/include/plat/omap34xx.h87
-rw-r--r--arch/arm/plat-omap/include/plat/omap44xx.h44
-rw-r--r--arch/arm/plat-omap/include/plat/omap730.h102
-rw-r--r--arch/arm/plat-omap/include/plat/omap7xx.h104
-rw-r--r--arch/arm/plat-omap/include/plat/omap850.h102
-rw-r--r--arch/arm/plat-omap/include/plat/omap_device.h141
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h447
-rw-r--r--arch/arm/plat-omap/include/plat/omapfb.h398
-rw-r--r--arch/arm/plat-omap/include/plat/onenand.h43
-rw-r--r--arch/arm/plat-omap/include/plat/param.h8
-rw-r--r--arch/arm/plat-omap/include/plat/powerdomain.h182
-rw-r--r--arch/arm/plat-omap/include/plat/prcm.h39
-rw-r--r--arch/arm/plat-omap/include/plat/sdrc.h151
-rw-r--r--arch/arm/plat-omap/include/plat/serial.h68
-rw-r--r--arch/arm/plat-omap/include/plat/smp.h51
-rw-r--r--arch/arm/plat-omap/include/plat/sram.h78
-rw-r--r--arch/arm/plat-omap/include/plat/system.h51
-rw-r--r--arch/arm/plat-omap/include/plat/tc.h106
-rw-r--r--arch/arm/plat-omap/include/plat/timer-gp.h17
-rw-r--r--arch/arm/plat-omap/include/plat/timex.h41
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h84
-rw-r--r--arch/arm/plat-omap/include/plat/usb.h145
65 files changed, 9318 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/blizzard.h b/arch/arm/plat-omap/include/plat/blizzard.h
new file mode 100644
index 000000000000..8d160f171372
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/blizzard.h
@@ -0,0 +1,12 @@
1#ifndef _BLIZZARD_H
2#define _BLIZZARD_H
3
4struct blizzard_platform_data {
5 void (*power_up)(struct device *dev);
6 void (*power_down)(struct device *dev);
7 unsigned long (*get_clock_rate)(struct device *dev);
8
9 unsigned te_connected : 1;
10};
11
12#endif
diff --git a/arch/arm/plat-omap/include/plat/board-ams-delta.h b/arch/arm/plat-omap/include/plat/board-ams-delta.h
new file mode 100644
index 000000000000..51b102dc906b
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/board-ams-delta.h
@@ -0,0 +1,76 @@
1/*
2 * arch/arm/plat-omap/include/mach/board-ams-delta.h
3 *
4 * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#ifndef __ASM_ARCH_OMAP_AMS_DELTA_H
27#define __ASM_ARCH_OMAP_AMS_DELTA_H
28
29#if defined (CONFIG_MACH_AMS_DELTA)
30
31#define AMS_DELTA_LATCH1_PHYS 0x01000000
32#define AMS_DELTA_LATCH1_VIRT 0xEA000000
33#define AMS_DELTA_MODEM_PHYS 0x04000000
34#define AMS_DELTA_MODEM_VIRT 0xEB000000
35#define AMS_DELTA_LATCH2_PHYS 0x08000000
36#define AMS_DELTA_LATCH2_VIRT 0xEC000000
37
38#define AMS_DELTA_LATCH1_LED_CAMERA 0x01
39#define AMS_DELTA_LATCH1_LED_ADVERT 0x02
40#define AMS_DELTA_LATCH1_LED_EMAIL 0x04
41#define AMS_DELTA_LATCH1_LED_HANDSFREE 0x08
42#define AMS_DELTA_LATCH1_LED_VOICEMAIL 0x10
43#define AMS_DELTA_LATCH1_LED_VOICE 0x20
44
45#define AMS_DELTA_LATCH2_LCD_VBLEN 0x0001
46#define AMS_DELTA_LATCH2_LCD_NDISP 0x0002
47#define AMS_DELTA_LATCH2_NAND_NCE 0x0004
48#define AMS_DELTA_LATCH2_NAND_NRE 0x0008
49#define AMS_DELTA_LATCH2_NAND_NWP 0x0010
50#define AMS_DELTA_LATCH2_NAND_NWE 0x0020
51#define AMS_DELTA_LATCH2_NAND_ALE 0x0040
52#define AMS_DELTA_LATCH2_NAND_CLE 0x0080
53#define AMD_DELTA_LATCH2_KEYBRD_PWR 0x0100
54#define AMD_DELTA_LATCH2_KEYBRD_DATA 0x0200
55#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400
56#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800
57#define AMS_DELTA_LATCH2_MODEM_NRESET 0x1000
58#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000
59
60#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0
61#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK 1
62#define AMS_DELTA_GPIO_PIN_MODEM_IRQ 2
63#define AMS_DELTA_GPIO_PIN_HOOK_SWITCH 4
64#define AMS_DELTA_GPIO_PIN_SCARD_NOFF 6
65#define AMS_DELTA_GPIO_PIN_SCARD_IO 7
66#define AMS_DELTA_GPIO_PIN_CONFIG 11
67#define AMS_DELTA_GPIO_PIN_NAND_RB 12
68
69#ifndef __ASSEMBLY__
70void ams_delta_latch1_write(u8 mask, u8 value);
71void ams_delta_latch2_write(u16 mask, u16 value);
72#endif
73
74#endif /* CONFIG_MACH_AMS_DELTA */
75
76#endif /* __ASM_ARCH_OMAP_AMS_DELTA_H */
diff --git a/arch/arm/plat-omap/include/plat/board-sx1.h b/arch/arm/plat-omap/include/plat/board-sx1.h
new file mode 100644
index 000000000000..355adbdaae33
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/board-sx1.h
@@ -0,0 +1,52 @@
1/*
2 * Siemens SX1 board definitions
3 *
4 * Copyright: Vovan888 at gmail com
5 *
6 * This package is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13 */
14
15#ifndef __ASM_ARCH_SX1_I2C_CHIPS_H
16#define __ASM_ARCH_SX1_I2C_CHIPS_H
17
18#define SOFIA_MAX_LIGHT_VAL 0x2B
19
20#define SOFIA_I2C_ADDR 0x32
21/* Sofia reg 3 bits masks */
22#define SOFIA_POWER1_REG 0x03
23
24#define SOFIA_USB_POWER 0x01
25#define SOFIA_MMC_POWER 0x04
26#define SOFIA_BLUETOOTH_POWER 0x08
27#define SOFIA_MMILIGHT_POWER 0x20
28
29#define SOFIA_POWER2_REG 0x04
30#define SOFIA_BACKLIGHT_REG 0x06
31#define SOFIA_KEYLIGHT_REG 0x07
32#define SOFIA_DIMMING_REG 0x09
33
34
35/* Function Prototypes for SX1 devices control on I2C bus */
36
37int sx1_setbacklight(u8 backlight);
38int sx1_getbacklight(u8 *backlight);
39int sx1_setkeylight(u8 keylight);
40int sx1_getkeylight(u8 *keylight);
41
42int sx1_setmmipower(u8 onoff);
43int sx1_setusbpower(u8 onoff);
44int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value);
45int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value);
46
47/* MMC prototypes */
48
49extern void sx1_mmc_init(void);
50extern void sx1_mmc_slot_cover_handler(void *arg, int state);
51
52#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */
diff --git a/arch/arm/plat-omap/include/plat/board-voiceblue.h b/arch/arm/plat-omap/include/plat/board-voiceblue.h
new file mode 100644
index 000000000000..27916b210f57
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/board-voiceblue.h
@@ -0,0 +1,19 @@
1/*
2 * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
3 *
4 * Hardware definitions for OMAP5910 based VoiceBlue board.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_VOICEBLUE_H
12#define __ASM_ARCH_VOICEBLUE_H
13
14extern void voiceblue_wdt_enable(void);
15extern void voiceblue_wdt_disable(void);
16extern void voiceblue_wdt_ping(void);
17
18#endif /* __ASM_ARCH_VOICEBLUE_H */
19
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
new file mode 100644
index 000000000000..c4fc69f09796
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -0,0 +1,160 @@
1/*
2 * arch/arm/plat-omap/include/mach/board.h
3 *
4 * Information structures for board-specific data
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 */
9
10#ifndef _OMAP_BOARD_H
11#define _OMAP_BOARD_H
12
13#include <linux/types.h>
14
15#include <plat/gpio-switch.h>
16
17/* Different peripheral ids */
18#define OMAP_TAG_CLOCK 0x4f01
19#define OMAP_TAG_LCD 0x4f05
20#define OMAP_TAG_GPIO_SWITCH 0x4f06
21#define OMAP_TAG_FBMEM 0x4f08
22#define OMAP_TAG_STI_CONSOLE 0x4f09
23#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
24
25#define OMAP_TAG_BOOT_REASON 0x4f80
26#define OMAP_TAG_FLASH_PART 0x4f81
27#define OMAP_TAG_VERSION_STR 0x4f82
28
29struct omap_clock_config {
30 /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
31 u8 system_clock_type;
32};
33
34struct omap_serial_console_config {
35 u8 console_uart;
36 u32 console_speed;
37};
38
39struct omap_sti_console_config {
40 unsigned enable:1;
41 u8 channel;
42};
43
44struct omap_camera_sensor_config {
45 u16 reset_gpio;
46 int (*power_on)(void * data);
47 int (*power_off)(void * data);
48};
49
50struct omap_usb_config {
51 /* Configure drivers according to the connectors on your board:
52 * - "A" connector (rectagular)
53 * ... for host/OHCI use, set "register_host".
54 * - "B" connector (squarish) or "Mini-B"
55 * ... for device/gadget use, set "register_dev".
56 * - "Mini-AB" connector (very similar to Mini-B)
57 * ... for OTG use as device OR host, initialize "otg"
58 */
59 unsigned register_host:1;
60 unsigned register_dev:1;
61 u8 otg; /* port number, 1-based: usb1 == 2 */
62
63 u8 hmc_mode;
64
65 /* implicitly true if otg: host supports remote wakeup? */
66 u8 rwc;
67
68 /* signaling pins used to talk to transceiver on usbN:
69 * 0 == usbN unused
70 * 2 == usb0-only, using internal transceiver
71 * 3 == 3 wire bidirectional
72 * 4 == 4 wire bidirectional
73 * 6 == 6 wire unidirectional (or TLL)
74 */
75 u8 pins[3];
76};
77
78struct omap_lcd_config {
79 char panel_name[16];
80 char ctrl_name[16];
81 s16 nreset_gpio;
82 u8 data_lines;
83};
84
85struct device;
86struct fb_info;
87struct omap_backlight_config {
88 int default_intensity;
89 int (*set_power)(struct device *dev, int state);
90 int (*check_fb)(struct fb_info *fb);
91};
92
93struct omap_fbmem_config {
94 u32 start;
95 u32 size;
96};
97
98struct omap_pwm_led_platform_data {
99 const char *name;
100 int intensity_timer;
101 int blink_timer;
102 void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
103};
104
105/* See arch/arm/plat-omap/include/mach/gpio-switch.h for definitions */
106struct omap_gpio_switch_config {
107 char name[12];
108 u16 gpio;
109 int flags:4;
110 int type:4;
111 int key_code:24; /* Linux key code */
112};
113
114struct omap_uart_config {
115 /* Bit field of UARTs present; bit 0 --> UART1 */
116 unsigned int enabled_uarts;
117};
118
119
120struct omap_flash_part_config {
121 char part_table[0];
122};
123
124struct omap_boot_reason_config {
125 char reason_str[12];
126};
127
128struct omap_version_config {
129 char component[12];
130 char version[12];
131};
132
133struct omap_board_config_entry {
134 u16 tag;
135 u16 len;
136 u8 data[0];
137};
138
139struct omap_board_config_kernel {
140 u16 tag;
141 const void *data;
142};
143
144extern const void *__omap_get_config(u16 tag, size_t len, int nr);
145
146#define omap_get_config(tag, type) \
147 ((const type *) __omap_get_config((tag), sizeof(type), 0))
148#define omap_get_nr_config(tag, type, nr) \
149 ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
150
151extern const void *omap_get_var_config(u16 tag, size_t *len);
152
153extern struct omap_board_config_kernel *omap_board_config;
154extern int omap_board_config_size;
155
156
157/* for TI reference platforms sharing the same debug card */
158extern int debug_card_init(u32 addr, unsigned gpio);
159
160#endif
diff --git a/arch/arm/plat-omap/include/plat/clkdev.h b/arch/arm/plat-omap/include/plat/clkdev.h
new file mode 100644
index 000000000000..730c49d1ebd8
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/clkdev.h
@@ -0,0 +1,13 @@
1#ifndef __MACH_CLKDEV_H
2#define __MACH_CLKDEV_H
3
4static inline int __clk_get(struct clk *clk)
5{
6 return 1;
7}
8
9static inline void __clk_put(struct clk *clk)
10{
11}
12
13#endif
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
new file mode 100644
index 000000000000..4b8b0d65cbf2
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -0,0 +1,163 @@
1/*
2 * arch/arm/plat-omap/include/mach/clock.h
3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ARCH_ARM_OMAP_CLOCK_H
14#define __ARCH_ARM_OMAP_CLOCK_H
15
16struct module;
17struct clk;
18struct clockdomain;
19
20struct clkops {
21 int (*enable)(struct clk *);
22 void (*disable)(struct clk *);
23 void (*find_idlest)(struct clk *, void __iomem **, u8 *);
24 void (*find_companion)(struct clk *, void __iomem **, u8 *);
25};
26
27#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
28 defined(CONFIG_ARCH_OMAP4)
29
30struct clksel_rate {
31 u32 val;
32 u8 div;
33 u8 flags;
34};
35
36struct clksel {
37 struct clk *parent;
38 const struct clksel_rate *rates;
39};
40
41struct dpll_data {
42 void __iomem *mult_div1_reg;
43 u32 mult_mask;
44 u32 div1_mask;
45 struct clk *clk_bypass;
46 struct clk *clk_ref;
47 void __iomem *control_reg;
48 u32 enable_mask;
49 unsigned int rate_tolerance;
50 unsigned long last_rounded_rate;
51 u16 last_rounded_m;
52 u8 last_rounded_n;
53 u8 min_divider;
54 u8 max_divider;
55 u32 max_tolerance;
56 u16 max_multiplier;
57#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
58 u8 modes;
59 void __iomem *autoidle_reg;
60 void __iomem *idlest_reg;
61 u32 autoidle_mask;
62 u32 freqsel_mask;
63 u32 idlest_mask;
64 u8 auto_recal_bit;
65 u8 recal_en_bit;
66 u8 recal_st_bit;
67# endif
68};
69
70#endif
71
72struct clk {
73 struct list_head node;
74 const struct clkops *ops;
75 const char *name;
76 int id;
77 struct clk *parent;
78 struct list_head children;
79 struct list_head sibling; /* node for children */
80 unsigned long rate;
81 __u32 flags;
82 void __iomem *enable_reg;
83 unsigned long (*recalc)(struct clk *);
84 int (*set_rate)(struct clk *, unsigned long);
85 long (*round_rate)(struct clk *, unsigned long);
86 void (*init)(struct clk *);
87 __u8 enable_bit;
88 __s8 usecount;
89#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
90 defined(CONFIG_ARCH_OMAP4)
91 u8 fixed_div;
92 void __iomem *clksel_reg;
93 u32 clksel_mask;
94 const struct clksel *clksel;
95 struct dpll_data *dpll_data;
96 const char *clkdm_name;
97 struct clockdomain *clkdm;
98#else
99 __u8 rate_offset;
100 __u8 src_offset;
101#endif
102#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
103 struct dentry *dent; /* For visible tree hierarchy */
104#endif
105};
106
107struct cpufreq_frequency_table;
108
109struct clk_functions {
110 int (*clk_enable)(struct clk *clk);
111 void (*clk_disable)(struct clk *clk);
112 long (*clk_round_rate)(struct clk *clk, unsigned long rate);
113 int (*clk_set_rate)(struct clk *clk, unsigned long rate);
114 int (*clk_set_parent)(struct clk *clk, struct clk *parent);
115 void (*clk_allow_idle)(struct clk *clk);
116 void (*clk_deny_idle)(struct clk *clk);
117 void (*clk_disable_unused)(struct clk *clk);
118#ifdef CONFIG_CPU_FREQ
119 void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
120#endif
121};
122
123extern unsigned int mpurate;
124
125extern int clk_init(struct clk_functions *custom_clocks);
126extern void clk_preinit(struct clk *clk);
127extern int clk_register(struct clk *clk);
128extern void clk_reparent(struct clk *child, struct clk *parent);
129extern void clk_unregister(struct clk *clk);
130extern void propagate_rate(struct clk *clk);
131extern void recalculate_root_clocks(void);
132extern unsigned long followparent_recalc(struct clk *clk);
133extern void clk_enable_init_clocks(void);
134#ifdef CONFIG_CPU_FREQ
135extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
136#endif
137
138extern const struct clkops clkops_null;
139
140/* Clock flags */
141/* bit 0 is free */
142#define RATE_FIXED (1 << 1) /* Fixed clock rate */
143/* bits 2-4 are free */
144#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
145#define CLOCK_IDLE_CONTROL (1 << 7)
146#define CLOCK_NO_IDLE_PARENT (1 << 8)
147#define DELAYED_APP (1 << 9) /* Delay application of clock */
148#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
149#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
150#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
151/* bits 13-31 are currently free */
152
153/* Clksel_rate flags */
154#define DEFAULT_RATE (1 << 0)
155#define RATE_IN_242X (1 << 1)
156#define RATE_IN_243X (1 << 2)
157#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
158#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
159
160#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
161
162
163#endif
diff --git a/arch/arm/plat-omap/include/plat/clockdomain.h b/arch/arm/plat-omap/include/plat/clockdomain.h
new file mode 100644
index 000000000000..eb734826e64e
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/clockdomain.h
@@ -0,0 +1,111 @@
1/*
2 * arch/arm/plat-omap/include/mach/clockdomain.h
3 *
4 * OMAP2/3 clockdomain framework functions
5 *
6 * Copyright (C) 2008 Texas Instruments, Inc.
7 * Copyright (C) 2008 Nokia Corporation
8 *
9 * Written by Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
17#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
18
19#include <plat/powerdomain.h>
20#include <plat/clock.h>
21#include <plat/cpu.h>
22
23/* Clockdomain capability flags */
24#define CLKDM_CAN_FORCE_SLEEP (1 << 0)
25#define CLKDM_CAN_FORCE_WAKEUP (1 << 1)
26#define CLKDM_CAN_ENABLE_AUTO (1 << 2)
27#define CLKDM_CAN_DISABLE_AUTO (1 << 3)
28
29#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
30#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
31#define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
32
33/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
34#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
35#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
36
37/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
38#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
39#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
40#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2
41#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3
42
43/*
44 * struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps
45 * and sleepdeps added when a powerdomain should stay active in hwsup mode;
46 * and conversely, removed when the powerdomain should be allowed to go
47 * inactive in hwsup mode.
48 */
49struct clkdm_pwrdm_autodep {
50
51 union {
52 /* Name of the powerdomain to add a wkdep/sleepdep on */
53 const char *name;
54
55 /* Powerdomain pointer (looked up at clkdm_init() time) */
56 struct powerdomain *ptr;
57 } pwrdm;
58
59 /* OMAP chip types that this clockdomain dep is valid on */
60 const struct omap_chip_id omap_chip;
61
62};
63
64struct clockdomain {
65
66 /* Clockdomain name */
67 const char *name;
68
69 union {
70 /* Powerdomain enclosing this clockdomain */
71 const char *name;
72
73 /* Powerdomain pointer assigned at clkdm_register() */
74 struct powerdomain *ptr;
75 } pwrdm;
76
77 /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */
78 const u16 clktrctrl_mask;
79
80 /* Clockdomain capability flags */
81 const u8 flags;
82
83 /* OMAP chip types that this clockdomain is valid on */
84 const struct omap_chip_id omap_chip;
85
86 /* Usecount tracking */
87 atomic_t usecount;
88
89 struct list_head node;
90
91};
92
93void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps);
94int clkdm_register(struct clockdomain *clkdm);
95int clkdm_unregister(struct clockdomain *clkdm);
96struct clockdomain *clkdm_lookup(const char *name);
97
98int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
99 void *user);
100struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
101
102void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
103void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
104
105int omap2_clkdm_wakeup(struct clockdomain *clkdm);
106int omap2_clkdm_sleep(struct clockdomain *clkdm);
107
108int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
109int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
110
111#endif
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
new file mode 100644
index 000000000000..064f1730f43b
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -0,0 +1,74 @@
1/*
2 * arch/arm/plat-omap/include/mach/common.h
3 *
4 * Header for code common to all OMAP machines.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
28#define __ARCH_ARM_MACH_OMAP_COMMON_H
29
30#include <linux/i2c.h>
31
32struct sys_timer;
33
34/* used by omap-smp.c and board-4430sdp.c */
35extern void __iomem *gic_cpu_base_addr;
36
37extern void omap_map_common_io(void);
38extern struct sys_timer omap_timer;
39#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
40extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
41 struct i2c_board_info const *info,
42 unsigned len);
43#else
44static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
45 struct i2c_board_info const *info,
46 unsigned len)
47{
48 return 0;
49}
50#endif
51
52/* IO bases for various OMAP processors */
53struct omap_globals {
54 u32 class; /* OMAP class to detect */
55 void __iomem *tap; /* Control module ID code */
56 void __iomem *sdrc; /* SDRAM Controller */
57 void __iomem *sms; /* SDRAM Memory Scheduler */
58 void __iomem *ctrl; /* System Control Module */
59 void __iomem *prm; /* Power and Reset Management */
60 void __iomem *cm; /* Clock Management */
61};
62
63void omap2_set_globals_242x(void);
64void omap2_set_globals_243x(void);
65void omap2_set_globals_343x(void);
66void omap2_set_globals_443x(void);
67
68/* These get called from omap2_set_globals_xxxx(), do not call these */
69void omap2_set_globals_tap(struct omap_globals *);
70void omap2_set_globals_sdrc(struct omap_globals *);
71void omap2_set_globals_control(struct omap_globals *);
72void omap2_set_globals_prcm(struct omap_globals *);
73
74#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
new file mode 100644
index 000000000000..8237cb9e74fd
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -0,0 +1,288 @@
1/*
2 * arch/arm/plat-omap/include/mach/control.h
3 *
4 * OMAP2/3/4 System Control Module definitions
5 *
6 * Copyright (C) 2007-2009 Texas Instruments, Inc.
7 * Copyright (C) 2007-2008 Nokia Corporation
8 *
9 * Written by Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation.
14 */
15
16#ifndef __ASM_ARCH_CONTROL_H
17#define __ASM_ARCH_CONTROL_H
18
19#include <mach/io.h>
20
21#ifndef __ASSEMBLY__
22#define OMAP242X_CTRL_REGADDR(reg) \
23 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
24#define OMAP243X_CTRL_REGADDR(reg) \
25 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
26#define OMAP343X_CTRL_REGADDR(reg) \
27 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
28#else
29#define OMAP242X_CTRL_REGADDR(reg) \
30 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
31#define OMAP243X_CTRL_REGADDR(reg) \
32 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
33#define OMAP343X_CTRL_REGADDR(reg) \
34 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
35#endif /* __ASSEMBLY__ */
36
37/*
38 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
39 * OMAP24XX and OMAP34XX.
40 */
41
42/* Control submodule offsets */
43
44#define OMAP2_CONTROL_INTERFACE 0x000
45#define OMAP2_CONTROL_PADCONFS 0x030
46#define OMAP2_CONTROL_GENERAL 0x270
47#define OMAP343X_CONTROL_MEM_WKUP 0x600
48#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
49#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
50
51/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
52
53#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
54
55/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
56#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
57#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
58#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
59#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
60#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
61#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
62#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
63#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040)
64#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090)
65#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094)
66#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
67#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
68
69/* 242x-only CONTROL_GENERAL register offsets */
70#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
71#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
72
73/* 243x-only CONTROL_GENERAL register offsets */
74/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
75#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
76#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
77#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
78#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
79#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
80#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
81
82/* 24xx-only CONTROL_GENERAL register offsets */
83#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
84#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
85#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
86#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
87#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
88#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
89#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
90#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
91#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
92#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
93#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
94#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
95#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
96#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
97#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
98#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
99#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
100#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
101#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
102#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
103#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
104#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
105#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
106#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
107#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
108#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
109#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
110#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
111#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
112#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
113#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
114
115#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
116
117/* 34xx-only CONTROL_GENERAL register offsets */
118#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
119#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
120#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
121#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068)
122#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c)
123#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070)
124#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074)
125#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078)
126#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
127#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
128#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0)
129#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
130#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
131#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
132#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
133#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
134#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
135#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
136#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
137#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
138#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
139#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
140#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
141#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
142#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
143#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0)
144#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
145#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
146#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
147#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
148#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
149#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \
150 + ((i) >> 1) * 4 + (!(i) & 1) * 2)
151#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4)
152#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8)
153#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0)
154#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4)
155#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8)
156#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
157#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0)
158#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4)
159#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8)
160#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0)
161#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4)
162
163
164/* 34xx PADCONF register offsets */
165#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
166 (i)*2)
167#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0)
168#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1)
169#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2)
170#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3)
171#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4)
172#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5)
173#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6)
174#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7)
175#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8)
176#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9)
177#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10)
178#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11)
179#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12)
180#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13)
181#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14)
182#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15)
183#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16)
184#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17)
185
186/* 34xx GENERAL_WKUP regist offsets */
187#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
188 0x008 + (i))
189#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
190#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
191#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
192#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
193#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
194
195/* 34xx D2D idle-related pins, handled by PM core */
196#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
197#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
198
199/*
200 * REVISIT: This list of registers is not comprehensive - there are more
201 * that should be added.
202 */
203
204/*
205 * Control module register bit defines - these should eventually go into
206 * their own regbits file. Some of these will be complicated, depending
207 * on the device type (general-purpose, emulator, test, secure, bad, other)
208 * and the security mode (secure, non-secure, don't care)
209 */
210/* CONTROL_DEVCONF0 bits */
211#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
212#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
213#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
214#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
215
216/* CONTROL_DEVCONF1 bits */
217#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
218#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
219#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
220#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
221#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
222
223/* CONTROL_STATUS bits */
224#define OMAP2_DEVICETYPE_MASK (0x7 << 8)
225#define OMAP2_SYSBOOT_5_MASK (1 << 5)
226#define OMAP2_SYSBOOT_4_MASK (1 << 4)
227#define OMAP2_SYSBOOT_3_MASK (1 << 3)
228#define OMAP2_SYSBOOT_2_MASK (1 << 2)
229#define OMAP2_SYSBOOT_1_MASK (1 << 1)
230#define OMAP2_SYSBOOT_0_MASK (1 << 0)
231
232/* CONTROL_PBIAS_LITE bits */
233#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15)
234#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11)
235#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10)
236#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9)
237#define OMAP343X_PBIASLITEVMODE1 (1 << 8)
238#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7)
239#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3)
240#define OMAP2_PBIASSPEEDCTRL0 (1 << 2)
241#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
242#define OMAP2_PBIASLITEVMODE0 (1 << 0)
243
244/* CONTROL_IVA2_BOOTMOD bits */
245#define OMAP3_IVA2_BOOTMOD_SHIFT 0
246#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
247#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
248
249/* CONTROL_PADCONF_X bits */
250#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
251#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
252
253#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
254#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
255#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
256
257#ifndef __ASSEMBLY__
258#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
259 defined(CONFIG_ARCH_OMAP4)
260extern void __iomem *omap_ctrl_base_get(void);
261extern u8 omap_ctrl_readb(u16 offset);
262extern u16 omap_ctrl_readw(u16 offset);
263extern u32 omap_ctrl_readl(u16 offset);
264extern void omap_ctrl_writeb(u8 val, u16 offset);
265extern void omap_ctrl_writew(u16 val, u16 offset);
266extern void omap_ctrl_writel(u32 val, u16 offset);
267
268extern void omap3_save_scratchpad_contents(void);
269extern void omap3_clear_scratchpad_contents(void);
270extern u32 *get_restore_pointer(void);
271extern u32 *get_es3_restore_pointer(void);
272extern u32 omap3_arm_context[128];
273extern void omap3_control_save_context(void);
274extern void omap3_control_restore_context(void);
275
276#else
277#define omap_ctrl_base_get() 0
278#define omap_ctrl_readb(x) 0
279#define omap_ctrl_readw(x) 0
280#define omap_ctrl_readl(x) 0
281#define omap_ctrl_writeb(x, y) WARN_ON(1)
282#define omap_ctrl_writew(x, y) WARN_ON(1)
283#define omap_ctrl_writel(x, y) WARN_ON(1)
284#endif
285#endif /* __ASSEMBLY__ */
286
287#endif /* __ASM_ARCH_CONTROL_H */
288
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
new file mode 100644
index 000000000000..f129efb3075e
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -0,0 +1,426 @@
1/*
2 * arch/arm/plat-omap/include/mach/cpu.h
3 *
4 * OMAP cpu type detection
5 *
6 * Copyright (C) 2004, 2008 Nokia Corporation
7 *
8 * Copyright (C) 2009 Texas Instruments.
9 *
10 * Written by Tony Lindgren <tony.lindgren@nokia.com>
11 *
12 * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 */
29
30#ifndef __ASM_ARCH_OMAP_CPU_H
31#define __ASM_ARCH_OMAP_CPU_H
32
33/*
34 * Omap device type i.e. EMU/HS/TST/GP/BAD
35 */
36#define OMAP2_DEVICE_TYPE_TEST 0
37#define OMAP2_DEVICE_TYPE_EMU 1
38#define OMAP2_DEVICE_TYPE_SEC 2
39#define OMAP2_DEVICE_TYPE_GP 3
40#define OMAP2_DEVICE_TYPE_BAD 4
41
42int omap_type(void);
43
44struct omap_chip_id {
45 u8 oc;
46 u8 type;
47};
48
49#define OMAP_CHIP_INIT(x) { .oc = x }
50
51/*
52 * omap_rev bits:
53 * CPU id bits (0730, 1510, 1710, 2422...) [31:16]
54 * CPU revision (See _REV_ defined in cpu.h) [15:08]
55 * CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
56 */
57unsigned int omap_rev(void);
58
59/*
60 * Test if multicore OMAP support is needed
61 */
62#undef MULTI_OMAP1
63#undef MULTI_OMAP2
64#undef OMAP_NAME
65
66#ifdef CONFIG_ARCH_OMAP730
67# ifdef OMAP_NAME
68# undef MULTI_OMAP1
69# define MULTI_OMAP1
70# else
71# define OMAP_NAME omap730
72# endif
73#endif
74#ifdef CONFIG_ARCH_OMAP850
75# ifdef OMAP_NAME
76# undef MULTI_OMAP1
77# define MULTI_OMAP1
78# else
79# define OMAP_NAME omap850
80# endif
81#endif
82#ifdef CONFIG_ARCH_OMAP15XX
83# ifdef OMAP_NAME
84# undef MULTI_OMAP1
85# define MULTI_OMAP1
86# else
87# define OMAP_NAME omap1510
88# endif
89#endif
90#ifdef CONFIG_ARCH_OMAP16XX
91# ifdef OMAP_NAME
92# undef MULTI_OMAP1
93# define MULTI_OMAP1
94# else
95# define OMAP_NAME omap16xx
96# endif
97#endif
98#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX))
99# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
100# error "OMAP1 and OMAP2 can't be selected at the same time"
101# endif
102#endif
103#ifdef CONFIG_ARCH_OMAP2420
104# ifdef OMAP_NAME
105# undef MULTI_OMAP2
106# define MULTI_OMAP2
107# else
108# define OMAP_NAME omap2420
109# endif
110#endif
111#ifdef CONFIG_ARCH_OMAP2430
112# ifdef OMAP_NAME
113# undef MULTI_OMAP2
114# define MULTI_OMAP2
115# else
116# define OMAP_NAME omap2430
117# endif
118#endif
119#ifdef CONFIG_ARCH_OMAP3430
120# ifdef OMAP_NAME
121# undef MULTI_OMAP2
122# define MULTI_OMAP2
123# else
124# define OMAP_NAME omap3430
125# endif
126#endif
127
128/*
129 * Macros to group OMAP into cpu classes.
130 * These can be used in most places.
131 * cpu_is_omap7xx(): True for OMAP730, OMAP850
132 * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310
133 * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710
134 * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
135 * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
136 * cpu_is_omap243x(): True for OMAP2430
137 * cpu_is_omap343x(): True for OMAP3430
138 */
139#define GET_OMAP_CLASS (omap_rev() & 0xff)
140
141#define IS_OMAP_CLASS(class, id) \
142static inline int is_omap ##class (void) \
143{ \
144 return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
145}
146
147#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
148
149#define IS_OMAP_SUBCLASS(subclass, id) \
150static inline int is_omap ##subclass (void) \
151{ \
152 return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
153}
154
155IS_OMAP_CLASS(7xx, 0x07)
156IS_OMAP_CLASS(15xx, 0x15)
157IS_OMAP_CLASS(16xx, 0x16)
158IS_OMAP_CLASS(24xx, 0x24)
159IS_OMAP_CLASS(34xx, 0x34)
160
161IS_OMAP_SUBCLASS(242x, 0x242)
162IS_OMAP_SUBCLASS(243x, 0x243)
163IS_OMAP_SUBCLASS(343x, 0x343)
164
165#define cpu_is_omap7xx() 0
166#define cpu_is_omap15xx() 0
167#define cpu_is_omap16xx() 0
168#define cpu_is_omap24xx() 0
169#define cpu_is_omap242x() 0
170#define cpu_is_omap243x() 0
171#define cpu_is_omap34xx() 0
172#define cpu_is_omap343x() 0
173#define cpu_is_omap44xx() 0
174#define cpu_is_omap443x() 0
175
176#if defined(MULTI_OMAP1)
177# if defined(CONFIG_ARCH_OMAP730)
178# undef cpu_is_omap7xx
179# define cpu_is_omap7xx() is_omap7xx()
180# endif
181# if defined(CONFIG_ARCH_OMAP850)
182# undef cpu_is_omap7xx
183# define cpu_is_omap7xx() is_omap7xx()
184# endif
185# if defined(CONFIG_ARCH_OMAP15XX)
186# undef cpu_is_omap15xx
187# define cpu_is_omap15xx() is_omap15xx()
188# endif
189# if defined(CONFIG_ARCH_OMAP16XX)
190# undef cpu_is_omap16xx
191# define cpu_is_omap16xx() is_omap16xx()
192# endif
193#else
194# if defined(CONFIG_ARCH_OMAP730)
195# undef cpu_is_omap7xx
196# define cpu_is_omap7xx() 1
197# endif
198# if defined(CONFIG_ARCH_OMAP850)
199# undef cpu_is_omap7xx
200# define cpu_is_omap7xx() 1
201# endif
202# if defined(CONFIG_ARCH_OMAP15XX)
203# undef cpu_is_omap15xx
204# define cpu_is_omap15xx() 1
205# endif
206# if defined(CONFIG_ARCH_OMAP16XX)
207# undef cpu_is_omap16xx
208# define cpu_is_omap16xx() 1
209# endif
210#endif
211
212#if defined(MULTI_OMAP2)
213# if defined(CONFIG_ARCH_OMAP24XX)
214# undef cpu_is_omap24xx
215# undef cpu_is_omap242x
216# undef cpu_is_omap243x
217# define cpu_is_omap24xx() is_omap24xx()
218# define cpu_is_omap242x() is_omap242x()
219# define cpu_is_omap243x() is_omap243x()
220# endif
221# if defined(CONFIG_ARCH_OMAP34XX)
222# undef cpu_is_omap34xx
223# undef cpu_is_omap343x
224# define cpu_is_omap34xx() is_omap34xx()
225# define cpu_is_omap343x() is_omap343x()
226# endif
227#else
228# if defined(CONFIG_ARCH_OMAP24XX)
229# undef cpu_is_omap24xx
230# define cpu_is_omap24xx() 1
231# endif
232# if defined(CONFIG_ARCH_OMAP2420)
233# undef cpu_is_omap242x
234# define cpu_is_omap242x() 1
235# endif
236# if defined(CONFIG_ARCH_OMAP2430)
237# undef cpu_is_omap243x
238# define cpu_is_omap243x() 1
239# endif
240# if defined(CONFIG_ARCH_OMAP34XX)
241# undef cpu_is_omap34xx
242# define cpu_is_omap34xx() 1
243# endif
244# if defined(CONFIG_ARCH_OMAP3430)
245# undef cpu_is_omap343x
246# define cpu_is_omap343x() 1
247# endif
248#endif
249
250/*
251 * Macros to detect individual cpu types.
252 * These are only rarely needed.
253 * cpu_is_omap330(): True for OMAP330
254 * cpu_is_omap730(): True for OMAP730
255 * cpu_is_omap850(): True for OMAP850
256 * cpu_is_omap1510(): True for OMAP1510
257 * cpu_is_omap1610(): True for OMAP1610
258 * cpu_is_omap1611(): True for OMAP1611
259 * cpu_is_omap5912(): True for OMAP5912
260 * cpu_is_omap1621(): True for OMAP1621
261 * cpu_is_omap1710(): True for OMAP1710
262 * cpu_is_omap2420(): True for OMAP2420
263 * cpu_is_omap2422(): True for OMAP2422
264 * cpu_is_omap2423(): True for OMAP2423
265 * cpu_is_omap2430(): True for OMAP2430
266 * cpu_is_omap3430(): True for OMAP3430
267 */
268#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
269
270#define IS_OMAP_TYPE(type, id) \
271static inline int is_omap ##type (void) \
272{ \
273 return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
274}
275
276IS_OMAP_TYPE(310, 0x0310)
277IS_OMAP_TYPE(730, 0x0730)
278IS_OMAP_TYPE(850, 0x0850)
279IS_OMAP_TYPE(1510, 0x1510)
280IS_OMAP_TYPE(1610, 0x1610)
281IS_OMAP_TYPE(1611, 0x1611)
282IS_OMAP_TYPE(5912, 0x1611)
283IS_OMAP_TYPE(1621, 0x1621)
284IS_OMAP_TYPE(1710, 0x1710)
285IS_OMAP_TYPE(2420, 0x2420)
286IS_OMAP_TYPE(2422, 0x2422)
287IS_OMAP_TYPE(2423, 0x2423)
288IS_OMAP_TYPE(2430, 0x2430)
289IS_OMAP_TYPE(3430, 0x3430)
290
291#define cpu_is_omap310() 0
292#define cpu_is_omap730() 0
293#define cpu_is_omap850() 0
294#define cpu_is_omap1510() 0
295#define cpu_is_omap1610() 0
296#define cpu_is_omap5912() 0
297#define cpu_is_omap1611() 0
298#define cpu_is_omap1621() 0
299#define cpu_is_omap1710() 0
300#define cpu_is_omap2420() 0
301#define cpu_is_omap2422() 0
302#define cpu_is_omap2423() 0
303#define cpu_is_omap2430() 0
304#define cpu_is_omap3430() 0
305
306/*
307 * Whether we have MULTI_OMAP1 or not, we still need to distinguish
308 * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710.
309 */
310
311#if defined(CONFIG_ARCH_OMAP730)
312# undef cpu_is_omap730
313# define cpu_is_omap730() is_omap730()
314#endif
315
316#if defined(CONFIG_ARCH_OMAP850)
317# undef cpu_is_omap850
318# define cpu_is_omap850() is_omap850()
319#endif
320
321#if defined(CONFIG_ARCH_OMAP15XX)
322# undef cpu_is_omap310
323# undef cpu_is_omap1510
324# define cpu_is_omap310() is_omap310()
325# define cpu_is_omap1510() is_omap1510()
326#endif
327
328#if defined(CONFIG_ARCH_OMAP16XX)
329# undef cpu_is_omap1610
330# undef cpu_is_omap1611
331# undef cpu_is_omap5912
332# undef cpu_is_omap1621
333# undef cpu_is_omap1710
334# define cpu_is_omap1610() is_omap1610()
335# define cpu_is_omap1611() is_omap1611()
336# define cpu_is_omap5912() is_omap5912()
337# define cpu_is_omap1621() is_omap1621()
338# define cpu_is_omap1710() is_omap1710()
339#endif
340
341#if defined(CONFIG_ARCH_OMAP24XX)
342# undef cpu_is_omap2420
343# undef cpu_is_omap2422
344# undef cpu_is_omap2423
345# undef cpu_is_omap2430
346# define cpu_is_omap2420() is_omap2420()
347# define cpu_is_omap2422() is_omap2422()
348# define cpu_is_omap2423() is_omap2423()
349# define cpu_is_omap2430() is_omap2430()
350#endif
351
352#if defined(CONFIG_ARCH_OMAP34XX)
353# undef cpu_is_omap3430
354# define cpu_is_omap3430() is_omap3430()
355#endif
356
357# if defined(CONFIG_ARCH_OMAP4)
358# undef cpu_is_omap44xx
359# undef cpu_is_omap443x
360# define cpu_is_omap44xx() 1
361# define cpu_is_omap443x() 1
362# endif
363
364/* Macros to detect if we have OMAP1 or OMAP2 */
365#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
366 cpu_is_omap16xx())
367#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
368 cpu_is_omap44xx())
369
370/* Various silicon revisions for omap2 */
371#define OMAP242X_CLASS 0x24200024
372#define OMAP2420_REV_ES1_0 0x24200024
373#define OMAP2420_REV_ES2_0 0x24201024
374
375#define OMAP243X_CLASS 0x24300024
376#define OMAP2430_REV_ES1_0 0x24300024
377
378#define OMAP343X_CLASS 0x34300034
379#define OMAP3430_REV_ES1_0 0x34300034
380#define OMAP3430_REV_ES2_0 0x34301034
381#define OMAP3430_REV_ES2_1 0x34302034
382#define OMAP3430_REV_ES3_0 0x34303034
383#define OMAP3430_REV_ES3_1 0x34304034
384
385#define OMAP443X_CLASS 0x44300034
386
387/*
388 * omap_chip bits
389 *
390 * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
391 * valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates
392 * something that is only valid on that particular ES revision.
393 *
394 * These bits may be ORed together to indicate structures that are
395 * available on multiple chip types.
396 *
397 * To test whether a particular structure matches the current OMAP chip type,
398 * use omap_chip_is().
399 *
400 */
401#define CHIP_IS_OMAP2420 (1 << 0)
402#define CHIP_IS_OMAP2430 (1 << 1)
403#define CHIP_IS_OMAP3430 (1 << 2)
404#define CHIP_IS_OMAP3430ES1 (1 << 3)
405#define CHIP_IS_OMAP3430ES2 (1 << 4)
406#define CHIP_IS_OMAP3430ES3_0 (1 << 5)
407#define CHIP_IS_OMAP3430ES3_1 (1 << 6)
408
409#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
410
411/*
412 * "GE" here represents "greater than or equal to" in terms of ES
413 * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
414 * chips at ES2 and beyond, but not, for example, any OMAP lines after
415 * OMAP3.
416 */
417#define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \
418 CHIP_IS_OMAP3430ES3_0 | \
419 CHIP_IS_OMAP3430ES3_1)
420#define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1)
421
422
423int omap_chip_is(struct omap_chip_id oci);
424void omap2_check_revision(void);
425
426#endif
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
new file mode 100644
index 000000000000..1c017b29b7e9
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -0,0 +1,680 @@
1/*
2 * arch/arm/plat-omap/include/mach/dma.h
3 *
4 * Copyright (C) 2003 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_DMA_H
22#define __ASM_ARCH_DMA_H
23
24/* Hardware registers for omap1 */
25#define OMAP1_DMA_BASE (0xfffed800)
26
27#define OMAP1_DMA_GCR 0x400
28#define OMAP1_DMA_GSCR 0x404
29#define OMAP1_DMA_GRST 0x408
30#define OMAP1_DMA_HW_ID 0x442
31#define OMAP1_DMA_PCH2_ID 0x444
32#define OMAP1_DMA_PCH0_ID 0x446
33#define OMAP1_DMA_PCH1_ID 0x448
34#define OMAP1_DMA_PCHG_ID 0x44a
35#define OMAP1_DMA_PCHD_ID 0x44c
36#define OMAP1_DMA_CAPS_0_U 0x44e
37#define OMAP1_DMA_CAPS_0_L 0x450
38#define OMAP1_DMA_CAPS_1_U 0x452
39#define OMAP1_DMA_CAPS_1_L 0x454
40#define OMAP1_DMA_CAPS_2 0x456
41#define OMAP1_DMA_CAPS_3 0x458
42#define OMAP1_DMA_CAPS_4 0x45a
43#define OMAP1_DMA_PCH2_SR 0x460
44#define OMAP1_DMA_PCH0_SR 0x480
45#define OMAP1_DMA_PCH1_SR 0x482
46#define OMAP1_DMA_PCHD_SR 0x4c0
47
48/* Hardware registers for omap2 and omap3 */
49#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
50#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
51#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000)
52
53#define OMAP_DMA4_REVISION 0x00
54#define OMAP_DMA4_GCR 0x78
55#define OMAP_DMA4_IRQSTATUS_L0 0x08
56#define OMAP_DMA4_IRQSTATUS_L1 0x0c
57#define OMAP_DMA4_IRQSTATUS_L2 0x10
58#define OMAP_DMA4_IRQSTATUS_L3 0x14
59#define OMAP_DMA4_IRQENABLE_L0 0x18
60#define OMAP_DMA4_IRQENABLE_L1 0x1c
61#define OMAP_DMA4_IRQENABLE_L2 0x20
62#define OMAP_DMA4_IRQENABLE_L3 0x24
63#define OMAP_DMA4_SYSSTATUS 0x28
64#define OMAP_DMA4_OCP_SYSCONFIG 0x2c
65#define OMAP_DMA4_CAPS_0 0x64
66#define OMAP_DMA4_CAPS_2 0x6c
67#define OMAP_DMA4_CAPS_3 0x70
68#define OMAP_DMA4_CAPS_4 0x74
69
70#define OMAP1_LOGICAL_DMA_CH_COUNT 17
71#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
72
73/* Common channel specific registers for omap1 */
74#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00)
75#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00)
76#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02)
77#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04)
78#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06)
79#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10)
80#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12)
81#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14)
82#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16)
83#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */
84#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18)
85#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a)
86#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c)
87#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e)
88#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28)
89
90/* Common channel specific registers for omap2 */
91#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80)
92#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80)
93#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84)
94#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88)
95#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c)
96#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90)
97#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94)
98#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98)
99#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4)
100#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8)
101#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac)
102#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0)
103#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4)
104#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8)
105
106/* Channel specific registers only on omap1 */
107#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08)
108#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a)
109#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c)
110#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e)
111#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20)
112#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22)
113#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24)
114#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */
115#define OMAP1_DMA_CCEN(n) 0
116#define OMAP1_DMA_CCFN(n) 0
117
118/* Channel specific registers only on omap2 */
119#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c)
120#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0)
121#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc)
122#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
123#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
124
125/* Additional registers available on OMAP4 */
126#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0)
127#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4)
128#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8)
129
130/* Dummy defines to keep multi-omap compiles happy */
131#define OMAP1_DMA_REVISION 0
132#define OMAP1_DMA_IRQSTATUS_L0 0
133#define OMAP1_DMA_IRQENABLE_L0 0
134#define OMAP1_DMA_OCP_SYSCONFIG 0
135#define OMAP_DMA4_HW_ID 0
136#define OMAP_DMA4_CAPS_0_L 0
137#define OMAP_DMA4_CAPS_0_U 0
138#define OMAP_DMA4_CAPS_1_L 0
139#define OMAP_DMA4_CAPS_1_U 0
140#define OMAP_DMA4_GSCR 0
141#define OMAP_DMA4_CPC(n) 0
142
143#define OMAP_DMA4_LCH_CTRL(n) 0
144#define OMAP_DMA4_COLOR_L(n) 0
145#define OMAP_DMA4_COLOR_U(n) 0
146#define OMAP_DMA4_CCR2(n) 0
147#define OMAP1_DMA_CSSA(n) 0
148#define OMAP1_DMA_CDSA(n) 0
149#define OMAP_DMA4_CSSA_L(n) 0
150#define OMAP_DMA4_CSSA_U(n) 0
151#define OMAP_DMA4_CDSA_L(n) 0
152#define OMAP_DMA4_CDSA_U(n) 0
153#define OMAP1_DMA_COLOR(n) 0
154
155/*----------------------------------------------------------------------------*/
156
157/* DMA channels for omap1 */
158#define OMAP_DMA_NO_DEVICE 0
159#define OMAP_DMA_MCSI1_TX 1
160#define OMAP_DMA_MCSI1_RX 2
161#define OMAP_DMA_I2C_RX 3
162#define OMAP_DMA_I2C_TX 4
163#define OMAP_DMA_EXT_NDMA_REQ 5
164#define OMAP_DMA_EXT_NDMA_REQ2 6
165#define OMAP_DMA_UWIRE_TX 7
166#define OMAP_DMA_MCBSP1_TX 8
167#define OMAP_DMA_MCBSP1_RX 9
168#define OMAP_DMA_MCBSP3_TX 10
169#define OMAP_DMA_MCBSP3_RX 11
170#define OMAP_DMA_UART1_TX 12
171#define OMAP_DMA_UART1_RX 13
172#define OMAP_DMA_UART2_TX 14
173#define OMAP_DMA_UART2_RX 15
174#define OMAP_DMA_MCBSP2_TX 16
175#define OMAP_DMA_MCBSP2_RX 17
176#define OMAP_DMA_UART3_TX 18
177#define OMAP_DMA_UART3_RX 19
178#define OMAP_DMA_CAMERA_IF_RX 20
179#define OMAP_DMA_MMC_TX 21
180#define OMAP_DMA_MMC_RX 22
181#define OMAP_DMA_NAND 23
182#define OMAP_DMA_IRQ_LCD_LINE 24
183#define OMAP_DMA_MEMORY_STICK 25
184#define OMAP_DMA_USB_W2FC_RX0 26
185#define OMAP_DMA_USB_W2FC_RX1 27
186#define OMAP_DMA_USB_W2FC_RX2 28
187#define OMAP_DMA_USB_W2FC_TX0 29
188#define OMAP_DMA_USB_W2FC_TX1 30
189#define OMAP_DMA_USB_W2FC_TX2 31
190
191/* These are only for 1610 */
192#define OMAP_DMA_CRYPTO_DES_IN 32
193#define OMAP_DMA_SPI_TX 33
194#define OMAP_DMA_SPI_RX 34
195#define OMAP_DMA_CRYPTO_HASH 35
196#define OMAP_DMA_CCP_ATTN 36
197#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
198#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
199#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
200#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
201#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
202#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
203#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
204#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
205#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
206#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
207#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
208#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
209#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
210#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
211#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
212#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
213#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
214#define OMAP_DMA_MMC2_TX 54
215#define OMAP_DMA_MMC2_RX 55
216#define OMAP_DMA_CRYPTO_DES_OUT 56
217
218/* DMA channels for 24xx */
219#define OMAP24XX_DMA_NO_DEVICE 0
220#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
221#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */
222#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */
223#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
224#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
225#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
226#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */
227#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */
228#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
229#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
230#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
231#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
232#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
233#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
234#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */
235#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
236#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
237#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
238#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */
239#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */
240#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
241#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
242#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
243#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
244#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
245#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
246#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
247#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
248#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */
249#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
250#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
251#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */
252#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */
253#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */
254#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */
255#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */
256#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */
257#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
258#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
259#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */
260#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */
261#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */
262#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */
263#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
264#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
265#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
266#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
267#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */
268#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */
269#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */
270#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */
271#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
272#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
273#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
274#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
275#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
276#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
277#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
278#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
279#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
280#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
281#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
282#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
283#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */
284#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */
285#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */
286#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */
287#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */
288#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */
289#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */
290#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */
291#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */
292#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */
293#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */
294#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */
295#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */
296#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */
297#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */
298#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */
299#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */
300#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
301#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */
302#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */
303#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */
304#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */
305#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */
306#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */
307#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */
308#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
309#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
310#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */
311#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */
312#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */
313#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */
314#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */
315#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */
316#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
317#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
318
319/* DMA request lines for 44xx */
320#define OMAP44XX_DMA_DSS_DISPC_REQ 6 /* S_DMA_5 */
321#define OMAP44XX_DMA_SYS_REQ2 7 /* S_DMA_6 */
322#define OMAP44XX_DMA_ISS_REQ1 9 /* S_DMA_8 */
323#define OMAP44XX_DMA_ISS_REQ2 10 /* S_DMA_9 */
324#define OMAP44XX_DMA_ISS_REQ3 12 /* S_DMA_11 */
325#define OMAP44XX_DMA_ISS_REQ4 13 /* S_DMA_12 */
326#define OMAP44XX_DMA_DSS_RFBI_REQ 14 /* S_DMA_13 */
327#define OMAP44XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
328#define OMAP44XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
329#define OMAP44XX_DMA_MCBSP2_TX 17 /* S_DMA_16 */
330#define OMAP44XX_DMA_MCBSP2_RX 18 /* S_DMA_17 */
331#define OMAP44XX_DMA_MCBSP3_TX 19 /* S_DMA_18 */
332#define OMAP44XX_DMA_MCBSP3_RX 20 /* S_DMA_19 */
333#define OMAP44XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
334#define OMAP44XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
335#define OMAP44XX_DMA_I2C3_TX 25 /* S_DMA_24 */
336#define OMAP44XX_DMA_I2C3_RX 26 /* S_DMA_25 */
337#define OMAP44XX_DMA_I2C1_TX 27 /* S_DMA_26 */
338#define OMAP44XX_DMA_I2C1_RX 28 /* S_DMA_27 */
339#define OMAP44XX_DMA_I2C2_TX 29 /* S_DMA_28 */
340#define OMAP44XX_DMA_I2C2_RX 30 /* S_DMA_29 */
341#define OMAP44XX_DMA_MCBSP4_TX 31 /* S_DMA_30 */
342#define OMAP44XX_DMA_MCBSP4_RX 32 /* S_DMA_31 */
343#define OMAP44XX_DMA_MCBSP1_TX 33 /* S_DMA_32 */
344#define OMAP44XX_DMA_MCBSP1_RX 34 /* S_DMA_33 */
345#define OMAP44XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
346#define OMAP44XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
347#define OMAP44XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
348#define OMAP44XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
349#define OMAP44XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
350#define OMAP44XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
351#define OMAP44XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
352#define OMAP44XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
353#define OMAP44XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
354#define OMAP44XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
355#define OMAP44XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
356#define OMAP44XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
357#define OMAP44XX_DMA_MMC2_TX 47 /* S_DMA_46 */
358#define OMAP44XX_DMA_MMC2_RX 48 /* S_DMA_47 */
359#define OMAP44XX_DMA_UART1_TX 49 /* S_DMA_48 */
360#define OMAP44XX_DMA_UART1_RX 50 /* S_DMA_49 */
361#define OMAP44XX_DMA_UART2_TX 51 /* S_DMA_50 */
362#define OMAP44XX_DMA_UART2_RX 52 /* S_DMA_51 */
363#define OMAP44XX_DMA_UART3_TX 53 /* S_DMA_52 */
364#define OMAP44XX_DMA_UART3_RX 54 /* S_DMA_53 */
365#define OMAP44XX_DMA_UART4_TX 55 /* S_DMA_54 */
366#define OMAP44XX_DMA_UART4_RX 56 /* S_DMA_55 */
367#define OMAP44XX_DMA_MMC4_TX 57 /* S_DMA_56 */
368#define OMAP44XX_DMA_MMC4_RX 58 /* S_DMA_57 */
369#define OMAP44XX_DMA_MMC5_TX 59 /* S_DMA_58 */
370#define OMAP44XX_DMA_MMC5_RX 60 /* S_DMA_59 */
371#define OMAP44XX_DMA_MMC1_TX 61 /* S_DMA_60 */
372#define OMAP44XX_DMA_MMC1_RX 62 /* S_DMA_61 */
373#define OMAP44XX_DMA_SYS_REQ3 64 /* S_DMA_63 */
374#define OMAP44XX_DMA_MCPDM_UP 65 /* S_DMA_64 */
375#define OMAP44XX_DMA_MCPDM_DL 66 /* S_DMA_65 */
376#define OMAP44XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
377#define OMAP44XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
378#define OMAP44XX_DMA_DSS_DSI1_REQ0 72 /* S_DMA_71 */
379#define OMAP44XX_DMA_DSS_DSI1_REQ1 73 /* S_DMA_72 */
380#define OMAP44XX_DMA_DSS_DSI1_REQ2 74 /* S_DMA_73 */
381#define OMAP44XX_DMA_DSS_DSI1_REQ3 75 /* S_DMA_74 */
382#define OMAP44XX_DMA_DSS_HDMI_REQ 76 /* S_DMA_75 */
383#define OMAP44XX_DMA_MMC3_TX 77 /* S_DMA_76 */
384#define OMAP44XX_DMA_MMC3_RX 78 /* S_DMA_77 */
385#define OMAP44XX_DMA_USIM_TX 79 /* S_DMA_78 */
386#define OMAP44XX_DMA_USIM_RX 80 /* S_DMA_79 */
387#define OMAP44XX_DMA_DSS_DSI2_REQ0 81 /* S_DMA_80 */
388#define OMAP44XX_DMA_DSS_DSI2_REQ1 82 /* S_DMA_81 */
389#define OMAP44XX_DMA_DSS_DSI2_REQ2 83 /* S_DMA_82 */
390#define OMAP44XX_DMA_DSS_DSI2_REQ3 84 /* S_DMA_83 */
391#define OMAP44XX_DMA_ABE_REQ0 101 /* S_DMA_100 */
392#define OMAP44XX_DMA_ABE_REQ1 102 /* S_DMA_101 */
393#define OMAP44XX_DMA_ABE_REQ2 103 /* S_DMA_102 */
394#define OMAP44XX_DMA_ABE_REQ3 104 /* S_DMA_103 */
395#define OMAP44XX_DMA_ABE_REQ4 105 /* S_DMA_104 */
396#define OMAP44XX_DMA_ABE_REQ5 106 /* S_DMA_105 */
397#define OMAP44XX_DMA_ABE_REQ6 107 /* S_DMA_106 */
398#define OMAP44XX_DMA_ABE_REQ7 108 /* S_DMA_107 */
399#define OMAP44XX_DMA_I2C4_TX 124 /* S_DMA_123 */
400#define OMAP44XX_DMA_I2C4_RX 125 /* S_DMA_124 */
401
402/*----------------------------------------------------------------------------*/
403
404/* Hardware registers for LCD DMA */
405#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
406#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
407#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
408#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04)
409#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06)
410#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
411
412#define OMAP1610_DMA_LCD_BASE (0xfffee300)
413#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
414#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
415#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
416#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
417#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca)
418#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc)
419#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce)
420#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0)
421#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2)
422#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4)
423#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6)
424#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8)
425#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda)
426#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0)
427#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4)
428#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
429#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
430
431#define OMAP1_DMA_TOUT_IRQ (1 << 0)
432#define OMAP_DMA_DROP_IRQ (1 << 1)
433#define OMAP_DMA_HALF_IRQ (1 << 2)
434#define OMAP_DMA_FRAME_IRQ (1 << 3)
435#define OMAP_DMA_LAST_IRQ (1 << 4)
436#define OMAP_DMA_BLOCK_IRQ (1 << 5)
437#define OMAP1_DMA_SYNC_IRQ (1 << 6)
438#define OMAP2_DMA_PKT_IRQ (1 << 7)
439#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
440#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
441#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
442#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
443
444#define OMAP_DMA_DATA_TYPE_S8 0x00
445#define OMAP_DMA_DATA_TYPE_S16 0x01
446#define OMAP_DMA_DATA_TYPE_S32 0x02
447
448#define OMAP_DMA_SYNC_ELEMENT 0x00
449#define OMAP_DMA_SYNC_FRAME 0x01
450#define OMAP_DMA_SYNC_BLOCK 0x02
451#define OMAP_DMA_SYNC_PACKET 0x03
452
453#define OMAP_DMA_SRC_SYNC 0x01
454#define OMAP_DMA_DST_SYNC 0x00
455
456#define OMAP_DMA_PORT_EMIFF 0x00
457#define OMAP_DMA_PORT_EMIFS 0x01
458#define OMAP_DMA_PORT_OCP_T1 0x02
459#define OMAP_DMA_PORT_TIPB 0x03
460#define OMAP_DMA_PORT_OCP_T2 0x04
461#define OMAP_DMA_PORT_MPUI 0x05
462
463#define OMAP_DMA_AMODE_CONSTANT 0x00
464#define OMAP_DMA_AMODE_POST_INC 0x01
465#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
466#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
467
468#define DMA_DEFAULT_FIFO_DEPTH 0x10
469#define DMA_DEFAULT_ARB_RATE 0x01
470/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
471#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
472#define DMA_THREAD_RESERVE_ONET (0x01 << 12)
473#define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
474#define DMA_THREAD_RESERVE_THREET (0x03 << 12)
475#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
476#define DMA_THREAD_FIFO_75 (0x01 << 14)
477#define DMA_THREAD_FIFO_25 (0x02 << 14)
478#define DMA_THREAD_FIFO_50 (0x03 << 14)
479
480/* DMA4_OCP_SYSCONFIG bits */
481#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12)
482#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
483#define DMA_SYSCONFIG_EMUFREE (1 << 5)
484#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3)
485#define DMA_SYSCONFIG_SOFTRESET (1 << 2)
486#define DMA_SYSCONFIG_AUTOIDLE (1 << 0)
487
488#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12)
489#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3)
490
491#define DMA_IDLEMODE_SMARTIDLE 0x2
492#define DMA_IDLEMODE_NO_IDLE 0x1
493#define DMA_IDLEMODE_FORCE_IDLE 0x0
494
495/* Chaining modes*/
496#ifndef CONFIG_ARCH_OMAP1
497#define OMAP_DMA_STATIC_CHAIN 0x1
498#define OMAP_DMA_DYNAMIC_CHAIN 0x2
499#define OMAP_DMA_CHAIN_ACTIVE 0x1
500#define OMAP_DMA_CHAIN_INACTIVE 0x0
501#endif
502
503#define DMA_CH_PRIO_HIGH 0x1
504#define DMA_CH_PRIO_LOW 0x0 /* Def */
505
506/* LCD DMA block numbers */
507enum {
508 OMAP_LCD_DMA_B1_TOP,
509 OMAP_LCD_DMA_B1_BOTTOM,
510 OMAP_LCD_DMA_B2_TOP,
511 OMAP_LCD_DMA_B2_BOTTOM
512};
513
514enum omap_dma_burst_mode {
515 OMAP_DMA_DATA_BURST_DIS = 0,
516 OMAP_DMA_DATA_BURST_4,
517 OMAP_DMA_DATA_BURST_8,
518 OMAP_DMA_DATA_BURST_16,
519};
520
521enum end_type {
522 OMAP_DMA_LITTLE_ENDIAN = 0,
523 OMAP_DMA_BIG_ENDIAN
524};
525
526enum omap_dma_color_mode {
527 OMAP_DMA_COLOR_DIS = 0,
528 OMAP_DMA_CONSTANT_FILL,
529 OMAP_DMA_TRANSPARENT_COPY
530};
531
532enum omap_dma_write_mode {
533 OMAP_DMA_WRITE_NON_POSTED = 0,
534 OMAP_DMA_WRITE_POSTED,
535 OMAP_DMA_WRITE_LAST_NON_POSTED
536};
537
538enum omap_dma_channel_mode {
539 OMAP_DMA_LCH_2D = 0,
540 OMAP_DMA_LCH_G,
541 OMAP_DMA_LCH_P,
542 OMAP_DMA_LCH_PD
543};
544
545struct omap_dma_channel_params {
546 int data_type; /* data type 8,16,32 */
547 int elem_count; /* number of elements in a frame */
548 int frame_count; /* number of frames in a element */
549
550 int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
551 int src_amode; /* constant, post increment, indexed,
552 double indexed */
553 unsigned long src_start; /* source address : physical */
554 int src_ei; /* source element index */
555 int src_fi; /* source frame index */
556
557 int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
558 int dst_amode; /* constant, post increment, indexed,
559 double indexed */
560 unsigned long dst_start; /* source address : physical */
561 int dst_ei; /* source element index */
562 int dst_fi; /* source frame index */
563
564 int trigger; /* trigger attached if the channel is
565 synchronized */
566 int sync_mode; /* sycn on element, frame , block or packet */
567 int src_or_dst_synch; /* source synch(1) or destination synch(0) */
568
569 int ie; /* interrupt enabled */
570
571 unsigned char read_prio;/* read priority */
572 unsigned char write_prio;/* write priority */
573
574#ifndef CONFIG_ARCH_OMAP1
575 enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
576#endif
577};
578
579
580extern void omap_set_dma_priority(int lch, int dst_port, int priority);
581extern int omap_request_dma(int dev_id, const char *dev_name,
582 void (*callback)(int lch, u16 ch_status, void *data),
583 void *data, int *dma_ch);
584extern void omap_enable_dma_irq(int ch, u16 irq_bits);
585extern void omap_disable_dma_irq(int ch, u16 irq_bits);
586extern void omap_free_dma(int ch);
587extern void omap_start_dma(int lch);
588extern void omap_stop_dma(int lch);
589extern void omap_set_dma_transfer_params(int lch, int data_type,
590 int elem_count, int frame_count,
591 int sync_mode,
592 int dma_trigger, int src_or_dst_synch);
593extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
594 u32 color);
595extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
596extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
597
598extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
599 unsigned long src_start,
600 int src_ei, int src_fi);
601extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
602extern void omap_set_dma_src_data_pack(int lch, int enable);
603extern void omap_set_dma_src_burst_mode(int lch,
604 enum omap_dma_burst_mode burst_mode);
605
606extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
607 unsigned long dest_start,
608 int dst_ei, int dst_fi);
609extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
610extern void omap_set_dma_dest_data_pack(int lch, int enable);
611extern void omap_set_dma_dest_burst_mode(int lch,
612 enum omap_dma_burst_mode burst_mode);
613
614extern void omap_set_dma_params(int lch,
615 struct omap_dma_channel_params *params);
616
617extern void omap_dma_link_lch(int lch_head, int lch_queue);
618extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
619
620extern int omap_set_dma_callback(int lch,
621 void (*callback)(int lch, u16 ch_status, void *data),
622 void *data);
623extern dma_addr_t omap_get_dma_src_pos(int lch);
624extern dma_addr_t omap_get_dma_dst_pos(int lch);
625extern void omap_clear_dma(int lch);
626extern int omap_get_dma_active_status(int lch);
627extern int omap_dma_running(void);
628extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
629 int tparams);
630extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
631 unsigned char write_prio);
632extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
633extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
634extern int omap_get_dma_index(int lch, int *ei, int *fi);
635
636void omap_dma_global_context_save(void);
637void omap_dma_global_context_restore(void);
638
639extern void omap_dma_disable_irq(int lch);
640
641/* Chaining APIs */
642#ifndef CONFIG_ARCH_OMAP1
643extern int omap_request_dma_chain(int dev_id, const char *dev_name,
644 void (*callback) (int lch, u16 ch_status,
645 void *data),
646 int *chain_id, int no_of_chans,
647 int chain_mode,
648 struct omap_dma_channel_params params);
649extern int omap_free_dma_chain(int chain_id);
650extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
651 int dest_start, int elem_count,
652 int frame_count, void *callbk_data);
653extern int omap_start_dma_chain_transfers(int chain_id);
654extern int omap_stop_dma_chain_transfers(int chain_id);
655extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
656extern int omap_get_dma_chain_dst_pos(int chain_id);
657extern int omap_get_dma_chain_src_pos(int chain_id);
658
659extern int omap_modify_dma_chain_params(int chain_id,
660 struct omap_dma_channel_params params);
661extern int omap_dma_chain_status(int chain_id);
662#endif
663
664/* LCD DMA functions */
665extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
666 void *data);
667extern void omap_free_lcd_dma(void);
668extern void omap_setup_lcd_dma(void);
669extern void omap_enable_lcd_dma(void);
670extern void omap_stop_lcd_dma(void);
671extern void omap_set_lcd_dma_ext_controller(int external);
672extern void omap_set_lcd_dma_single_transfer(int single);
673extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
674 int data_type);
675extern void omap_set_lcd_dma_b1_rotation(int rotate);
676extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
677extern void omap_set_lcd_dma_b1_mirror(int mirror);
678extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
679
680#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
new file mode 100644
index 000000000000..20f1054c0a80
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -0,0 +1,84 @@
1/*
2 * arch/arm/plat-omap/include/mach/dmtimer.h
3 *
4 * OMAP Dual-Mode Timers
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
8 * PWM and clock framwork support by Timo Teras.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __ASM_ARCH_DMTIMER_H
30#define __ASM_ARCH_DMTIMER_H
31
32/* clock sources */
33#define OMAP_TIMER_SRC_SYS_CLK 0x00
34#define OMAP_TIMER_SRC_32_KHZ 0x01
35#define OMAP_TIMER_SRC_EXT_CLK 0x02
36
37/* timer interrupt enable bits */
38#define OMAP_TIMER_INT_CAPTURE (1 << 2)
39#define OMAP_TIMER_INT_OVERFLOW (1 << 1)
40#define OMAP_TIMER_INT_MATCH (1 << 0)
41
42/* trigger types */
43#define OMAP_TIMER_TRIGGER_NONE 0x00
44#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
45#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
46
47struct omap_dm_timer;
48struct clk;
49
50int omap_dm_timer_init(void);
51
52struct omap_dm_timer *omap_dm_timer_request(void);
53struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
54void omap_dm_timer_free(struct omap_dm_timer *timer);
55void omap_dm_timer_enable(struct omap_dm_timer *timer);
56void omap_dm_timer_disable(struct omap_dm_timer *timer);
57
58int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
59
60u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
61struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
62
63void omap_dm_timer_trigger(struct omap_dm_timer *timer);
64void omap_dm_timer_start(struct omap_dm_timer *timer);
65void omap_dm_timer_stop(struct omap_dm_timer *timer);
66
67int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
68void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
69void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
70void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
71void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
72void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
73
74void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
75
76unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
77void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
78unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
79void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
80
81int omap_dm_timers_active(void);
82
83
84#endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/arch/arm/plat-omap/include/plat/dsp_common.h b/arch/arm/plat-omap/include/plat/dsp_common.h
new file mode 100644
index 000000000000..da97736f3efa
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/dsp_common.h
@@ -0,0 +1,40 @@
1/*
2 * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
3 *
4 * Copyright (C) 2004-2006 Nokia Corporation. All rights reserved.
5 *
6 * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#ifndef ASM_ARCH_DSP_COMMON_H
25#define ASM_ARCH_DSP_COMMON_H
26
27#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_OMAP_MMU_FWK)
28extern void omap_dsp_request_mpui(void);
29extern void omap_dsp_release_mpui(void);
30extern int omap_dsp_request_mem(void);
31extern int omap_dsp_release_mem(void);
32#else
33static inline int omap_dsp_request_mem(void)
34{
35 return 0;
36}
37#define omap_dsp_release_mem() do {} while (0)
38#endif
39
40#endif /* ASM_ARCH_DSP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/plat/fpga.h b/arch/arm/plat-omap/include/plat/fpga.h
new file mode 100644
index 000000000000..f1864a652f7a
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/fpga.h
@@ -0,0 +1,197 @@
1/*
2 * arch/arm/plat-omap/include/mach/fpga.h
3 *
4 * Interrupt handler for OMAP-1510 FPGA
5 *
6 * Copyright (C) 2001 RidgeRun, Inc.
7 * Author: Greg Lonnon <glonnon@ridgerun.com>
8 *
9 * Copyright (C) 2002 MontaVista Software, Inc.
10 *
11 * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
12 * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#ifndef __ASM_ARCH_OMAP_FPGA_H
20#define __ASM_ARCH_OMAP_FPGA_H
21
22#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
23extern void omap1510_fpga_init_irq(void);
24#else
25#define omap1510_fpga_init_irq() (0)
26#endif
27
28#define fpga_read(reg) __raw_readb(reg)
29#define fpga_write(val, reg) __raw_writeb(val, reg)
30
31/*
32 * ---------------------------------------------------------------------------
33 * H2/P2 Debug board FPGA
34 * ---------------------------------------------------------------------------
35 */
36/* maps in the FPGA registers and the ETHR registers */
37#define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */
38#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
39#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
40
41#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
42#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
43#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
44#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
45#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
46#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
47#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
48#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
49
50/* NOTE: most boards don't have a static mapping for the FPGA ... */
51struct h2p2_dbg_fpga {
52 /* offset 0x00 */
53 u16 smc91x[8];
54 /* offset 0x10 */
55 u16 fpga_rev;
56 u16 board_rev;
57 u16 gpio_outputs;
58 u16 leds;
59 /* offset 0x18 */
60 u16 misc_inputs;
61 u16 lan_status;
62 u16 lan_reset;
63 u16 reserved0;
64 /* offset 0x20 */
65 u16 ps2_data;
66 u16 ps2_ctrl;
67 /* plus also 4 rs232 ports ... */
68};
69
70/* LEDs definition on debug board (16 LEDs, all physically green) */
71#define H2P2_DBG_FPGA_LED_GREEN (1 << 15)
72#define H2P2_DBG_FPGA_LED_AMBER (1 << 14)
73#define H2P2_DBG_FPGA_LED_RED (1 << 13)
74#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
75/* cpu0 load-meter LEDs */
76#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ...
77#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
78#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
79
80#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
81#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
82
83/*
84 * ---------------------------------------------------------------------------
85 * OMAP-1510 FPGA
86 * ---------------------------------------------------------------------------
87 */
88#define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */
89#define OMAP1510_FPGA_SIZE SZ_4K
90#define OMAP1510_FPGA_START 0x08000000 /* PA */
91
92/* Revision */
93#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
94#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1)
95
96#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2)
97#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3)
98#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4)
99#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5)
100
101/* Interrupt status */
102#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6)
103#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7)
104
105/* Interrupt mask */
106#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8)
107#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9)
108
109/* Reset registers */
110#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa)
111#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb)
112
113#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc)
114#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe)
115#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf)
116#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14)
117#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15)
118#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16)
119#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18)
120#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100)
121#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101)
122#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102)
123
124#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204)
125
126#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205)
127#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206)
128#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207)
129#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208)
130#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209)
131#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a)
132#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b)
133#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c)
134#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d)
135#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e)
136#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210)
137
138#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
139
140/*
141 * Power up Giga UART driver, turn on HID clock.
142 * Turn off BT power, since we're not using it and it
143 * draws power.
144 */
145#define OMAP1510_FPGA_RESET_VALUE 0x42
146
147#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7)
148#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6)
149#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5)
150#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4)
151#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3)
152#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2)
153#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
154#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
155
156/*
157 * Innovator/OMAP1510 FPGA HID register bit definitions
158 */
159#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */
160#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */
161#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */
162#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */
163#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */
164#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */
165#define OMAP1510_FPGA_HID_rsrvd (1<<6)
166#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
167
168/* The FPGA IRQ is cascaded through GPIO_13 */
169#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
170
171/* IRQ Numbers for interrupts muxed through the FPGA */
172#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0)
173#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1)
174#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2)
175#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3)
176#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4)
177#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5)
178#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6)
179#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7)
180#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8)
181#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9)
182#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10)
183#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11)
184#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12)
185#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13)
186#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14)
187#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15)
188#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16)
189#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17)
190#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18)
191#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19)
192#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20)
193#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21)
194#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22)
195#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23)
196
197#endif
diff --git a/arch/arm/plat-omap/include/plat/gpio-switch.h b/arch/arm/plat-omap/include/plat/gpio-switch.h
new file mode 100644
index 000000000000..10da0e07c0cf
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/gpio-switch.h
@@ -0,0 +1,54 @@
1/*
2 * GPIO switch definitions
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
12#define __ASM_ARCH_OMAP_GPIO_SWITCH_H
13
14#include <linux/types.h>
15
16/* Cover:
17 * high -> closed
18 * low -> open
19 * Connection:
20 * high -> connected
21 * low -> disconnected
22 * Activity:
23 * high -> active
24 * low -> inactive
25 *
26 */
27#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000
28#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001
29#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY 0x0002
30#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
31#define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002
32
33struct omap_gpio_switch {
34 const char *name;
35 s16 gpio;
36 unsigned flags:4;
37 unsigned type:4;
38
39 /* Time in ms to debounce when transitioning from
40 * inactive state to active state. */
41 u16 debounce_rising;
42 /* Same for transition from active to inactive state. */
43 u16 debounce_falling;
44
45 /* notify board-specific code about state changes */
46 void (* notify)(void *data, int state);
47 void *notify_data;
48};
49
50/* Call at init time only */
51extern void omap_register_gpio_switches(const struct omap_gpio_switch *tbl,
52 int count);
53
54#endif
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
new file mode 100644
index 000000000000..de7c54731cbe
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -0,0 +1,129 @@
1/*
2 * arch/arm/plat-omap/include/mach/gpio.h
3 *
4 * OMAP GPIO handling defines and functions
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 *
8 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#ifndef __ASM_ARCH_OMAP_GPIO_H
27#define __ASM_ARCH_OMAP_GPIO_H
28
29#include <linux/io.h>
30#include <mach/irqs.h>
31
32#define OMAP1_MPUIO_BASE 0xfffb5000
33
34#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850))
35
36#define OMAP_MPUIO_INPUT_LATCH 0x00
37#define OMAP_MPUIO_OUTPUT 0x02
38#define OMAP_MPUIO_IO_CNTL 0x04
39#define OMAP_MPUIO_KBR_LATCH 0x08
40#define OMAP_MPUIO_KBC 0x0a
41#define OMAP_MPUIO_GPIO_EVENT_MODE 0x0c
42#define OMAP_MPUIO_GPIO_INT_EDGE 0x0e
43#define OMAP_MPUIO_KBD_INT 0x10
44#define OMAP_MPUIO_GPIO_INT 0x12
45#define OMAP_MPUIO_KBD_MASKIT 0x14
46#define OMAP_MPUIO_GPIO_MASKIT 0x16
47#define OMAP_MPUIO_GPIO_DEBOUNCING 0x18
48#define OMAP_MPUIO_LATCH 0x1a
49#else
50#define OMAP_MPUIO_INPUT_LATCH 0x00
51#define OMAP_MPUIO_OUTPUT 0x04
52#define OMAP_MPUIO_IO_CNTL 0x08
53#define OMAP_MPUIO_KBR_LATCH 0x10
54#define OMAP_MPUIO_KBC 0x14
55#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
56#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
57#define OMAP_MPUIO_KBD_INT 0x20
58#define OMAP_MPUIO_GPIO_INT 0x24
59#define OMAP_MPUIO_KBD_MASKIT 0x28
60#define OMAP_MPUIO_GPIO_MASKIT 0x2c
61#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
62#define OMAP_MPUIO_LATCH 0x34
63#endif
64
65#define OMAP34XX_NR_GPIOS 6
66
67#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
68#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
69
70#define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \
71 IH_MPUIO_BASE + ((nr) & 0x0f) : \
72 IH_GPIO_BASE + (nr))
73
74extern int omap_gpio_init(void); /* Call from board init only */
75extern void omap2_gpio_prepare_for_retention(void);
76extern void omap2_gpio_resume_after_retention(void);
77extern void omap_set_gpio_debounce(int gpio, int enable);
78extern void omap_set_gpio_debounce_time(int gpio, int enable);
79extern void omap_gpio_save_context(void);
80extern void omap_gpio_restore_context(void);
81/*-------------------------------------------------------------------------*/
82
83/* Wrappers for "new style" GPIO calls, using the new infrastructure
84 * which lets us plug in FPGA, I2C, and other implementations.
85 * *
86 * The original OMAP-specfic calls should eventually be removed.
87 */
88
89#include <linux/errno.h>
90#include <asm-generic/gpio.h>
91
92static inline int gpio_get_value(unsigned gpio)
93{
94 return __gpio_get_value(gpio);
95}
96
97static inline void gpio_set_value(unsigned gpio, int value)
98{
99 __gpio_set_value(gpio, value);
100}
101
102static inline int gpio_cansleep(unsigned gpio)
103{
104 return __gpio_cansleep(gpio);
105}
106
107static inline int gpio_to_irq(unsigned gpio)
108{
109 return __gpio_to_irq(gpio);
110}
111
112static inline int irq_to_gpio(unsigned irq)
113{
114 int tmp;
115
116 /* omap1 SOC mpuio */
117 if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))
118 return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;
119
120 /* SOC gpio */
121 tmp = irq - IH_GPIO_BASE;
122 if (tmp < OMAP_MAX_GPIO_LINES)
123 return tmp;
124
125 /* we don't supply reverse mappings for non-SOC gpios */
126 return -EIO;
127}
128
129#endif
diff --git a/arch/arm/plat-omap/include/plat/gpmc-smc91x.h b/arch/arm/plat-omap/include/plat/gpmc-smc91x.h
new file mode 100644
index 000000000000..b64fbee4d567
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/gpmc-smc91x.h
@@ -0,0 +1,42 @@
1/*
2 * arch/arm/plat-omap/include/mach/gpmc-smc91x.h
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__
12
13#define GPMC_TIMINGS_SMC91C96 (1 << 4)
14#define GPMC_MUX_ADD_DATA (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */
15#define GPMC_READ_MON (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */
16#define GPMC_WRITE_MON (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */
17
18struct omap_smc91x_platform_data {
19 int cs;
20 int gpio_irq;
21 int gpio_pwrdwn;
22 int gpio_reset;
23 int wait_pin; /* Optional GPMC_CONFIG1_WAITPINSELECT */
24 u32 flags;
25 int (*retime)(void);
26};
27
28#if defined(CONFIG_SMC91X) || \
29 defined(CONFIG_SMC91X_MODULE)
30
31extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d);
32
33#else
34
35#define board_smc91x_data NULL
36
37static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d)
38{
39}
40
41#endif
42#endif
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
new file mode 100644
index 000000000000..696e0ca051b7
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -0,0 +1,115 @@
1/*
2 * General-Purpose Memory Controller for OMAP2
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H
13
14/* Maximum Number of Chip Selects */
15#define GPMC_CS_NUM 8
16
17#define GPMC_CS_CONFIG1 0x00
18#define GPMC_CS_CONFIG2 0x04
19#define GPMC_CS_CONFIG3 0x08
20#define GPMC_CS_CONFIG4 0x0c
21#define GPMC_CS_CONFIG5 0x10
22#define GPMC_CS_CONFIG6 0x14
23#define GPMC_CS_CONFIG7 0x18
24#define GPMC_CS_NAND_COMMAND 0x1c
25#define GPMC_CS_NAND_ADDRESS 0x20
26#define GPMC_CS_NAND_DATA 0x24
27
28#define GPMC_CONFIG 0x50
29#define GPMC_STATUS 0x54
30
31#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
32#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
33#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
34#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
35#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
36#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
37#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
38#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
39#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
40#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
41#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
42#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
43#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
44#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
45#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
46#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
47#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
48#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(1)
49#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
50#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
51#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
52#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
53#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
54#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
55#define GPMC_CONFIG7_CSVALID (1 << 6)
56
57/*
58 * Note that all values in this struct are in nanoseconds, while
59 * the register values are in gpmc_fck cycles.
60 */
61struct gpmc_timings {
62 /* Minimum clock period for synchronous mode */
63 u16 sync_clk;
64
65 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
66 u16 cs_on; /* Assertion time */
67 u16 cs_rd_off; /* Read deassertion time */
68 u16 cs_wr_off; /* Write deassertion time */
69
70 /* ADV signal timings corresponding to GPMC_CONFIG3 */
71 u16 adv_on; /* Assertion time */
72 u16 adv_rd_off; /* Read deassertion time */
73 u16 adv_wr_off; /* Write deassertion time */
74
75 /* WE signals timings corresponding to GPMC_CONFIG4 */
76 u16 we_on; /* WE assertion time */
77 u16 we_off; /* WE deassertion time */
78
79 /* OE signals timings corresponding to GPMC_CONFIG4 */
80 u16 oe_on; /* OE assertion time */
81 u16 oe_off; /* OE deassertion time */
82
83 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
84 u16 page_burst_access; /* Multiple access word delay */
85 u16 access; /* Start-cycle to first data valid delay */
86 u16 rd_cycle; /* Total read cycle time */
87 u16 wr_cycle; /* Total write cycle time */
88
89 /* The following are only on OMAP3430 */
90 u16 wr_access; /* WRACCESSTIME */
91 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
92};
93
94extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
95extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
96extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
97extern unsigned long gpmc_get_fclk_period(void);
98
99extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
100extern u32 gpmc_cs_read_reg(int cs, int idx);
101extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
102extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
103extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
104extern void gpmc_cs_free(int cs);
105extern int gpmc_cs_set_reserved(int cs, int reserved);
106extern int gpmc_cs_reserved(int cs);
107extern int gpmc_prefetch_enable(int cs, int dma_mode,
108 unsigned int u32_count, int is_write);
109extern void gpmc_prefetch_reset(void);
110extern int gpmc_prefetch_status(void);
111extern void omap3_gpmc_save_context(void);
112extern void omap3_gpmc_restore_context(void);
113extern void __init gpmc_init(void);
114
115#endif
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
new file mode 100644
index 000000000000..d5b26adfb890
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -0,0 +1,290 @@
1/*
2 * arch/arm/plat-omap/include/mach/hardware.h
3 *
4 * Hardware definitions for TI OMAP processors and boards
5 *
6 * NOTE: Please put device driver specific defines into a separate header
7 * file for each driver.
8 *
9 * Copyright (C) 2001 RidgeRun, Inc.
10 * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
11 *
12 * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
13 * and Dirk Behme <dirk.behme@de.bosch.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35
36#ifndef __ASM_ARCH_OMAP_HARDWARE_H
37#define __ASM_ARCH_OMAP_HARDWARE_H
38
39#include <asm/sizes.h>
40#ifndef __ASSEMBLER__
41#include <asm/types.h>
42#include <plat/cpu.h>
43#endif
44#include <plat/serial.h>
45
46/*
47 * ---------------------------------------------------------------------------
48 * Common definitions for all OMAP processors
49 * NOTE: Put all processor or board specific parts to the special header
50 * files.
51 * ---------------------------------------------------------------------------
52 */
53
54/*
55 * ----------------------------------------------------------------------------
56 * Timers
57 * ----------------------------------------------------------------------------
58 */
59#define OMAP_MPU_TIMER1_BASE (0xfffec500)
60#define OMAP_MPU_TIMER2_BASE (0xfffec600)
61#define OMAP_MPU_TIMER3_BASE (0xfffec700)
62#define MPU_TIMER_FREE (1 << 6)
63#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
64#define MPU_TIMER_AR (1 << 1)
65#define MPU_TIMER_ST (1 << 0)
66
67/*
68 * ----------------------------------------------------------------------------
69 * Clocks
70 * ----------------------------------------------------------------------------
71 */
72#define CLKGEN_REG_BASE (0xfffece00)
73#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
74#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
75#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
76#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
77#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
78#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
79#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
80#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
81
82#define CK_RATEF 1
83#define CK_IDLEF 2
84#define CK_ENABLEF 4
85#define CK_SELECTF 8
86#define SETARM_IDLE_SHIFT
87
88/* DPLL control registers */
89#define DPLL_CTL (0xfffecf00)
90
91/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
92#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
93#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
94#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
95#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
96#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
97
98/*
99 * ---------------------------------------------------------------------------
100 * UPLD
101 * ---------------------------------------------------------------------------
102 */
103#define ULPD_REG_BASE (0xfffe0800)
104#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
105#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
106#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
107# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
108# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
109#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
110# define SOFT_UDC_REQ (1 << 4)
111# define SOFT_USB_CLK_REQ (1 << 3)
112# define SOFT_DPLL_REQ (1 << 0)
113#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
114#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
115#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
116#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
117#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
118# define DIS_MMC2_DPLL_REQ (1 << 11)
119# define DIS_MMC1_DPLL_REQ (1 << 10)
120# define DIS_UART3_DPLL_REQ (1 << 9)
121# define DIS_UART2_DPLL_REQ (1 << 8)
122# define DIS_UART1_DPLL_REQ (1 << 7)
123# define DIS_USB_HOST_DPLL_REQ (1 << 6)
124#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
125#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
126
127/*
128 * ---------------------------------------------------------------------------
129 * Watchdog timer
130 * ---------------------------------------------------------------------------
131 */
132
133/* Watchdog timer within the OMAP3.2 gigacell */
134#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
135#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
136#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
137#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
138#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
139
140/*
141 * ---------------------------------------------------------------------------
142 * Interrupts
143 * ---------------------------------------------------------------------------
144 */
145#ifdef CONFIG_ARCH_OMAP1
146
147/*
148 * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
149 * or something similar.. -- PFM.
150 */
151
152#define OMAP_IH1_BASE 0xfffecb00
153#define OMAP_IH2_BASE 0xfffe0000
154
155#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
156#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
157#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
158#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
159#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
160#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
161#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
162
163#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
164#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
165#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
166#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
167#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
168#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
169#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
170
171#define IRQ_ITR_REG_OFFSET 0x00
172#define IRQ_MIR_REG_OFFSET 0x04
173#define IRQ_SIR_IRQ_REG_OFFSET 0x10
174#define IRQ_SIR_FIQ_REG_OFFSET 0x14
175#define IRQ_CONTROL_REG_OFFSET 0x18
176#define IRQ_ISR_REG_OFFSET 0x9c
177#define IRQ_ILR0_REG_OFFSET 0x1c
178#define IRQ_GMR_REG_OFFSET 0xa0
179
180#endif
181
182/*
183 * ----------------------------------------------------------------------------
184 * System control registers
185 * ----------------------------------------------------------------------------
186 */
187#define MOD_CONF_CTRL_0 0xfffe1080
188#define MOD_CONF_CTRL_1 0xfffe1110
189
190/*
191 * ----------------------------------------------------------------------------
192 * Pin multiplexing registers
193 * ----------------------------------------------------------------------------
194 */
195#define FUNC_MUX_CTRL_0 0xfffe1000
196#define FUNC_MUX_CTRL_1 0xfffe1004
197#define FUNC_MUX_CTRL_2 0xfffe1008
198#define COMP_MODE_CTRL_0 0xfffe100c
199#define FUNC_MUX_CTRL_3 0xfffe1010
200#define FUNC_MUX_CTRL_4 0xfffe1014
201#define FUNC_MUX_CTRL_5 0xfffe1018
202#define FUNC_MUX_CTRL_6 0xfffe101C
203#define FUNC_MUX_CTRL_7 0xfffe1020
204#define FUNC_MUX_CTRL_8 0xfffe1024
205#define FUNC_MUX_CTRL_9 0xfffe1028
206#define FUNC_MUX_CTRL_A 0xfffe102C
207#define FUNC_MUX_CTRL_B 0xfffe1030
208#define FUNC_MUX_CTRL_C 0xfffe1034
209#define FUNC_MUX_CTRL_D 0xfffe1038
210#define PULL_DWN_CTRL_0 0xfffe1040
211#define PULL_DWN_CTRL_1 0xfffe1044
212#define PULL_DWN_CTRL_2 0xfffe1048
213#define PULL_DWN_CTRL_3 0xfffe104c
214#define PULL_DWN_CTRL_4 0xfffe10ac
215
216/* OMAP-1610 specific multiplexing registers */
217#define FUNC_MUX_CTRL_E 0xfffe1090
218#define FUNC_MUX_CTRL_F 0xfffe1094
219#define FUNC_MUX_CTRL_10 0xfffe1098
220#define FUNC_MUX_CTRL_11 0xfffe109c
221#define FUNC_MUX_CTRL_12 0xfffe10a0
222#define PU_PD_SEL_0 0xfffe10b4
223#define PU_PD_SEL_1 0xfffe10b8
224#define PU_PD_SEL_2 0xfffe10bc
225#define PU_PD_SEL_3 0xfffe10c0
226#define PU_PD_SEL_4 0xfffe10c4
227
228/* Timer32K for 1610 and 1710*/
229#define OMAP_TIMER32K_BASE 0xFFFBC400
230
231/*
232 * ---------------------------------------------------------------------------
233 * TIPB bus interface
234 * ---------------------------------------------------------------------------
235 */
236#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
237#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
238#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
239#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
240
241/*
242 * ----------------------------------------------------------------------------
243 * MPUI interface
244 * ----------------------------------------------------------------------------
245 */
246#define MPUI_BASE (0xfffec900)
247#define MPUI_CTRL (MPUI_BASE + 0x0)
248#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
249#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
250#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
251#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
252#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
253#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
254#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
255
256/*
257 * ----------------------------------------------------------------------------
258 * LED Pulse Generator
259 * ----------------------------------------------------------------------------
260 */
261#define OMAP_LPG1_BASE 0xfffbd000
262#define OMAP_LPG2_BASE 0xfffbd800
263#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
264#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
265#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
266#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
267
268/*
269 * ----------------------------------------------------------------------------
270 * Pulse-Width Light
271 * ----------------------------------------------------------------------------
272 */
273#define OMAP_PWL_BASE 0xfffb5800
274#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
275#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
276
277/*
278 * ---------------------------------------------------------------------------
279 * Processor specific defines
280 * ---------------------------------------------------------------------------
281 */
282
283#include <plat/omap7xx.h>
284#include <plat/omap1510.h>
285#include <plat/omap16xx.h>
286#include <plat/omap24xx.h>
287#include <plat/omap34xx.h>
288#include <plat/omap44xx.h>
289
290#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/hwa742.h b/arch/arm/plat-omap/include/plat/hwa742.h
new file mode 100644
index 000000000000..886248d32b49
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/hwa742.h
@@ -0,0 +1,8 @@
1#ifndef _HWA742_H
2#define _HWA742_H
3
4struct hwa742_platform_data {
5 unsigned te_connected:1;
6};
7
8#endif
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
new file mode 100644
index 000000000000..7e5319f907d1
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -0,0 +1,287 @@
1/*
2 * arch/arm/plat-omap/include/mach/io.h
3 *
4 * IO definitions for TI OMAP processors and boards
5 *
6 * Copied from arch/arm/mach-sa1100/include/mach/io.h
7 * Copyright (C) 1997-1999 Russell King
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 *
32 * Modifications:
33 * 06-12-1997 RMK Created.
34 * 07-04-1999 RMK Major cleanup
35 */
36
37#ifndef __ASM_ARM_ARCH_IO_H
38#define __ASM_ARM_ARCH_IO_H
39
40#include <mach/hardware.h>
41
42#define IO_SPACE_LIMIT 0xffffffff
43
44/*
45 * We don't actually have real ISA nor PCI buses, but there is so many
46 * drivers out there that might just work if we fake them...
47 */
48#define __io(a) __typesafe_io(a)
49#define __mem_pci(a) (a)
50
51/*
52 * ----------------------------------------------------------------------------
53 * I/O mapping
54 * ----------------------------------------------------------------------------
55 */
56
57#ifdef __ASSEMBLER__
58#define IOMEM(x) (x)
59#else
60#define IOMEM(x) ((void __force __iomem *)(x))
61#endif
62
63#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
64#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
65
66#define OMAP2_L3_IO_OFFSET 0x90000000
67#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
68
69
70#define OMAP2_L4_IO_OFFSET 0xb2000000
71#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
72
73#define OMAP4_L3_IO_OFFSET 0xb4000000
74#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
75
76#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
77#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
78
79#define OMAP4_GPMC_IO_OFFSET 0xa9000000
80#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
81
82#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
83#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
84
85/*
86 * ----------------------------------------------------------------------------
87 * Omap1 specific IO mapping
88 * ----------------------------------------------------------------------------
89 */
90
91#define OMAP1_IO_PHYS 0xFFFB0000
92#define OMAP1_IO_SIZE 0x40000
93#define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
94
95/*
96 * ----------------------------------------------------------------------------
97 * Omap2 specific IO mapping
98 * ----------------------------------------------------------------------------
99 */
100
101/* We map both L3 and L4 on OMAP2 */
102#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
103#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
104#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
105#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
106#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
107#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
108
109#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
110#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
111#define L4_WK_243X_SIZE SZ_1M
112#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE
113#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
114 /* 0x6e000000 --> 0xfe000000 */
115#define OMAP243X_GPMC_SIZE SZ_1M
116#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
117 /* 0x6D000000 --> 0xfd000000 */
118#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
119#define OMAP243X_SDRC_SIZE SZ_1M
120#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
121 /* 0x6c000000 --> 0xfc000000 */
122#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
123#define OMAP243X_SMS_SIZE SZ_1M
124
125/* DSP */
126#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
127#define DSP_MEM_24XX_VIRT 0xe0000000
128#define DSP_MEM_24XX_SIZE 0x28000
129#define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */
130#define DSP_IPI_24XX_VIRT 0xe1000000
131#define DSP_IPI_24XX_SIZE SZ_4K
132#define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */
133#define DSP_MMU_24XX_VIRT 0xe2000000
134#define DSP_MMU_24XX_SIZE SZ_4K
135
136/*
137 * ----------------------------------------------------------------------------
138 * Omap3 specific IO mapping
139 * ----------------------------------------------------------------------------
140 */
141
142/* We map both L3 and L4 on OMAP3 */
143#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */
144#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
145#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
146
147#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */
148#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
149#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
150
151/*
152 * Need to look at the Size 4M for L4.
153 * VPOM3430 was not working for Int controller
154 */
155
156#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */
157#define L4_WK_34XX_VIRT (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET)
158#define L4_WK_34XX_SIZE SZ_1M
159
160#define L4_PER_34XX_PHYS L4_PER_34XX_BASE
161 /* 0x49000000 --> 0xfb000000 */
162#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
163#define L4_PER_34XX_SIZE SZ_1M
164
165#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE
166 /* 0x54000000 --> 0xfe800000 */
167#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
168#define L4_EMU_34XX_SIZE SZ_8M
169
170#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE
171 /* 0x6e000000 --> 0xfe000000 */
172#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
173#define OMAP34XX_GPMC_SIZE SZ_1M
174
175#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE
176 /* 0x6c000000 --> 0xfc000000 */
177#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
178#define OMAP343X_SMS_SIZE SZ_1M
179
180#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE
181 /* 0x6D000000 --> 0xfd000000 */
182#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
183#define OMAP343X_SDRC_SIZE SZ_1M
184
185/* DSP */
186#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */
187#define DSP_MEM_34XX_VIRT 0xe0000000
188#define DSP_MEM_34XX_SIZE 0x28000
189#define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */
190#define DSP_IPI_34XX_VIRT 0xe1000000
191#define DSP_IPI_34XX_SIZE SZ_4K
192#define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */
193#define DSP_MMU_34XX_VIRT 0xe2000000
194#define DSP_MMU_34XX_SIZE SZ_4K
195
196/*
197 * ----------------------------------------------------------------------------
198 * Omap4 specific IO mapping
199 * ----------------------------------------------------------------------------
200 */
201
202/* We map both L3 and L4 on OMAP4 */
203#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */
204#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
205#define L3_44XX_SIZE SZ_1M
206
207#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */
208#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
209#define L4_44XX_SIZE SZ_4M
210
211
212#define L4_WK_44XX_PHYS L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */
213#define L4_WK_44XX_VIRT (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET)
214#define L4_WK_44XX_SIZE SZ_1M
215
216#define L4_PER_44XX_PHYS L4_PER_44XX_BASE
217 /* 0x48000000 --> 0xfa000000 */
218#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
219#define L4_PER_44XX_SIZE SZ_4M
220
221#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE
222 /* 0x49000000 --> 0xfb000000 */
223#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
224#define L4_ABE_44XX_SIZE SZ_1M
225
226#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
227 /* 0x54000000 --> 0xfe800000 */
228#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
229#define L4_EMU_44XX_SIZE SZ_8M
230
231#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
232 /* 0x50000000 --> 0xf9000000 */
233#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
234#define OMAP44XX_GPMC_SIZE SZ_1M
235
236
237#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE
238 /* 0x4c000000 --> 0xfd100000 */
239#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
240#define OMAP44XX_EMIF1_SIZE SZ_1M
241
242#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
243 /* 0x4d000000 --> 0xfd200000 */
244#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
245#define OMAP44XX_EMIF2_SIZE SZ_1M
246
247#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
248 /* 0x4e000000 --> 0xfd300000 */
249#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
250#define OMAP44XX_DMM_SIZE SZ_1M
251/*
252 * ----------------------------------------------------------------------------
253 * Omap specific register access
254 * ----------------------------------------------------------------------------
255 */
256
257#ifndef __ASSEMBLER__
258
259/*
260 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
261 */
262
263extern u8 omap_readb(u32 pa);
264extern u16 omap_readw(u32 pa);
265extern u32 omap_readl(u32 pa);
266extern void omap_writeb(u8 v, u32 pa);
267extern void omap_writew(u16 v, u32 pa);
268extern void omap_writel(u32 v, u32 pa);
269
270struct omap_sdrc_params;
271
272extern void omap1_map_common_io(void);
273extern void omap1_init_common_hw(void);
274
275extern void omap2_map_common_io(void);
276extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
277 struct omap_sdrc_params *sdrc_cs1);
278
279#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
280#define __arch_iounmap(v) omap_iounmap(v)
281
282void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
283void omap_iounmap(volatile void __iomem *addr);
284
285#endif
286
287#endif
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
new file mode 100644
index 000000000000..0752af9d099e
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -0,0 +1,168 @@
1/*
2 * omap iommu: main structures
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __MACH_IOMMU_H
14#define __MACH_IOMMU_H
15
16struct iotlb_entry {
17 u32 da;
18 u32 pa;
19 u32 pgsz, prsvd, valid;
20 union {
21 u16 ap;
22 struct {
23 u32 endian, elsz, mixed;
24 };
25 };
26};
27
28struct iommu {
29 const char *name;
30 struct module *owner;
31 struct clk *clk;
32 void __iomem *regbase;
33 struct device *dev;
34
35 unsigned int refcount;
36 struct mutex iommu_lock; /* global for this whole object */
37
38 /*
39 * We don't change iopgd for a situation like pgd for a task,
40 * but share it globally for each iommu.
41 */
42 u32 *iopgd;
43 spinlock_t page_table_lock; /* protect iopgd */
44
45 int nr_tlb_entries;
46
47 struct list_head mmap;
48 struct mutex mmap_lock; /* protect mmap */
49
50 int (*isr)(struct iommu *obj);
51
52 void *ctx; /* iommu context: registres saved area */
53};
54
55struct cr_regs {
56 union {
57 struct {
58 u16 cam_l;
59 u16 cam_h;
60 };
61 u32 cam;
62 };
63 union {
64 struct {
65 u16 ram_l;
66 u16 ram_h;
67 };
68 u32 ram;
69 };
70};
71
72struct iotlb_lock {
73 short base;
74 short vict;
75};
76
77/* architecture specific functions */
78struct iommu_functions {
79 unsigned long version;
80
81 int (*enable)(struct iommu *obj);
82 void (*disable)(struct iommu *obj);
83 u32 (*fault_isr)(struct iommu *obj, u32 *ra);
84
85 void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
86 void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr);
87
88 struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e);
89 int (*cr_valid)(struct cr_regs *cr);
90 u32 (*cr_to_virt)(struct cr_regs *cr);
91 void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
92 ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf);
93
94 u32 (*get_pte_attr)(struct iotlb_entry *e);
95
96 void (*save_ctx)(struct iommu *obj);
97 void (*restore_ctx)(struct iommu *obj);
98 ssize_t (*dump_ctx)(struct iommu *obj, char *buf, ssize_t len);
99};
100
101struct iommu_platform_data {
102 const char *name;
103 const char *clk_name;
104 const int nr_tlb_entries;
105};
106
107#if defined(CONFIG_ARCH_OMAP1)
108#error "iommu for this processor not implemented yet"
109#else
110#include <plat/iommu2.h>
111#endif
112
113/*
114 * utilities for super page(16MB, 1MB, 64KB and 4KB)
115 */
116
117#define iopgsz_max(bytes) \
118 (((bytes) >= SZ_16M) ? SZ_16M : \
119 ((bytes) >= SZ_1M) ? SZ_1M : \
120 ((bytes) >= SZ_64K) ? SZ_64K : \
121 ((bytes) >= SZ_4K) ? SZ_4K : 0)
122
123#define bytes_to_iopgsz(bytes) \
124 (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
125 ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
126 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
127 ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
128
129#define iopgsz_to_bytes(iopgsz) \
130 (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
131 ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
132 ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
133 ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
134
135#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
136
137/*
138 * global functions
139 */
140extern u32 iommu_arch_version(void);
141
142extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
143extern u32 iotlb_cr_to_virt(struct cr_regs *cr);
144
145extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
146extern void flush_iotlb_page(struct iommu *obj, u32 da);
147extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
148extern void flush_iotlb_all(struct iommu *obj);
149
150extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
151extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
152
153extern struct iommu *iommu_get(const char *name);
154extern void iommu_put(struct iommu *obj);
155
156extern void iommu_save_ctx(struct iommu *obj);
157extern void iommu_restore_ctx(struct iommu *obj);
158
159extern int install_iommu_arch(const struct iommu_functions *ops);
160extern void uninstall_iommu_arch(const struct iommu_functions *ops);
161
162extern int foreach_iommu_device(void *data,
163 int (*fn)(struct device *, void *));
164
165extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len);
166extern size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t len);
167
168#endif /* __MACH_IOMMU_H */
diff --git a/arch/arm/plat-omap/include/plat/iommu2.h b/arch/arm/plat-omap/include/plat/iommu2.h
new file mode 100644
index 000000000000..10ad05f410e9
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/iommu2.h
@@ -0,0 +1,96 @@
1/*
2 * omap iommu: omap2 architecture specific definitions
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __MACH_IOMMU2_H
14#define __MACH_IOMMU2_H
15
16#include <linux/io.h>
17
18/*
19 * MMU Register offsets
20 */
21#define MMU_REVISION 0x00
22#define MMU_SYSCONFIG 0x10
23#define MMU_SYSSTATUS 0x14
24#define MMU_IRQSTATUS 0x18
25#define MMU_IRQENABLE 0x1c
26#define MMU_WALKING_ST 0x40
27#define MMU_CNTL 0x44
28#define MMU_FAULT_AD 0x48
29#define MMU_TTB 0x4c
30#define MMU_LOCK 0x50
31#define MMU_LD_TLB 0x54
32#define MMU_CAM 0x58
33#define MMU_RAM 0x5c
34#define MMU_GFLUSH 0x60
35#define MMU_FLUSH_ENTRY 0x64
36#define MMU_READ_CAM 0x68
37#define MMU_READ_RAM 0x6c
38#define MMU_EMU_FAULT_AD 0x70
39
40#define MMU_REG_SIZE 256
41
42/*
43 * MMU Register bit definitions
44 */
45#define MMU_LOCK_BASE_SHIFT 10
46#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
47#define MMU_LOCK_BASE(x) \
48 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
49
50#define MMU_LOCK_VICT_SHIFT 4
51#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
52#define MMU_LOCK_VICT(x) \
53 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
54
55#define MMU_CAM_VATAG_SHIFT 12
56#define MMU_CAM_VATAG_MASK \
57 ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
58#define MMU_CAM_P (1 << 3)
59#define MMU_CAM_V (1 << 2)
60#define MMU_CAM_PGSZ_MASK 3
61#define MMU_CAM_PGSZ_1M (0 << 0)
62#define MMU_CAM_PGSZ_64K (1 << 0)
63#define MMU_CAM_PGSZ_4K (2 << 0)
64#define MMU_CAM_PGSZ_16M (3 << 0)
65
66#define MMU_RAM_PADDR_SHIFT 12
67#define MMU_RAM_PADDR_MASK \
68 ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
69#define MMU_RAM_ENDIAN_SHIFT 9
70#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
71#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT)
72#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
73#define MMU_RAM_ELSZ_SHIFT 7
74#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
75#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
76#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
77#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
78#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
79#define MMU_RAM_MIXED_SHIFT 6
80#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
81#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
82
83/*
84 * register accessors
85 */
86static inline u32 iommu_read_reg(struct iommu *obj, size_t offs)
87{
88 return __raw_readl(obj->regbase + offs);
89}
90
91static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs)
92{
93 __raw_writel(val, obj->regbase + offs);
94}
95
96#endif /* __MACH_IOMMU2_H */
diff --git a/arch/arm/plat-omap/include/plat/iovmm.h b/arch/arm/plat-omap/include/plat/iovmm.h
new file mode 100644
index 000000000000..bdc7ce5d7a4a
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/iovmm.h
@@ -0,0 +1,94 @@
1/*
2 * omap iommu: simple virtual address space management
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __IOMMU_MMAP_H
14#define __IOMMU_MMAP_H
15
16struct iovm_struct {
17 struct iommu *iommu; /* iommu object which this belongs to */
18 u32 da_start; /* area definition */
19 u32 da_end;
20 u32 flags; /* IOVMF_: see below */
21 struct list_head list; /* linked in ascending order */
22 const struct sg_table *sgt; /* keep 'page' <-> 'da' mapping */
23 void *va; /* mpu side mapped address */
24};
25
26/*
27 * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma)
28 *
29 * lower 16 bit is used for h/w and upper 16 bit is for s/w.
30 */
31#define IOVMF_SW_SHIFT 16
32#define IOVMF_HW_SIZE (1 << IOVMF_SW_SHIFT)
33#define IOVMF_HW_MASK (IOVMF_HW_SIZE - 1)
34#define IOVMF_SW_MASK (~IOVMF_HW_MASK)UL
35
36/*
37 * iovma: h/w flags derived from cam and ram attribute
38 */
39#define IOVMF_CAM_MASK (~((1 << 10) - 1))
40#define IOVMF_RAM_MASK (~IOVMF_CAM_MASK)
41
42#define IOVMF_PGSZ_MASK (3 << 0)
43#define IOVMF_PGSZ_1M MMU_CAM_PGSZ_1M
44#define IOVMF_PGSZ_64K MMU_CAM_PGSZ_64K
45#define IOVMF_PGSZ_4K MMU_CAM_PGSZ_4K
46#define IOVMF_PGSZ_16M MMU_CAM_PGSZ_16M
47
48#define IOVMF_ENDIAN_MASK (1 << 9)
49#define IOVMF_ENDIAN_BIG MMU_RAM_ENDIAN_BIG
50#define IOVMF_ENDIAN_LITTLE MMU_RAM_ENDIAN_LITTLE
51
52#define IOVMF_ELSZ_MASK (3 << 7)
53#define IOVMF_ELSZ_8 MMU_RAM_ELSZ_8
54#define IOVMF_ELSZ_16 MMU_RAM_ELSZ_16
55#define IOVMF_ELSZ_32 MMU_RAM_ELSZ_32
56#define IOVMF_ELSZ_NONE MMU_RAM_ELSZ_NONE
57
58#define IOVMF_MIXED_MASK (1 << 6)
59#define IOVMF_MIXED MMU_RAM_MIXED
60
61/*
62 * iovma: s/w flags, used for mapping and umapping internally.
63 */
64#define IOVMF_MMIO (1 << IOVMF_SW_SHIFT)
65#define IOVMF_ALLOC (2 << IOVMF_SW_SHIFT)
66#define IOVMF_ALLOC_MASK (3 << IOVMF_SW_SHIFT)
67
68/* "superpages" is supported just with physically linear pages */
69#define IOVMF_DISCONT (1 << (2 + IOVMF_SW_SHIFT))
70#define IOVMF_LINEAR (2 << (2 + IOVMF_SW_SHIFT))
71#define IOVMF_LINEAR_MASK (3 << (2 + IOVMF_SW_SHIFT))
72
73#define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT))
74#define IOVMF_DA_ANON (2 << (4 + IOVMF_SW_SHIFT))
75#define IOVMF_DA_MASK (3 << (4 + IOVMF_SW_SHIFT))
76
77
78extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da);
79extern u32 iommu_vmap(struct iommu *obj, u32 da,
80 const struct sg_table *sgt, u32 flags);
81extern struct sg_table *iommu_vunmap(struct iommu *obj, u32 da);
82extern u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes,
83 u32 flags);
84extern void iommu_vfree(struct iommu *obj, const u32 da);
85extern u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
86 u32 flags);
87extern void iommu_kunmap(struct iommu *obj, u32 da);
88extern u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes,
89 u32 flags);
90extern void iommu_kfree(struct iommu *obj, u32 da);
91
92extern void *da_to_va(struct iommu *obj, u32 da);
93
94#endif /* __IOMMU_MMAP_H */
diff --git a/arch/arm/plat-omap/include/plat/irda.h b/arch/arm/plat-omap/include/plat/irda.h
new file mode 100644
index 000000000000..40f60339d1c6
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/irda.h
@@ -0,0 +1,33 @@
1/*
2 * arch/arm/plat-omap/include/mach/irda.h
3 *
4 * Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef ASMARM_ARCH_IRDA_H
11#define ASMARM_ARCH_IRDA_H
12
13/* board specific transceiver capabilities */
14
15#define IR_SEL 1 /* Selects IrDA */
16#define IR_SIRMODE 2
17#define IR_FIRMODE 4
18#define IR_MIRMODE 8
19
20struct omap_irda_config {
21 int transceiver_cap;
22 int (*transceiver_mode)(struct device *dev, int mode);
23 int (*select_irda)(struct device *dev, int state);
24 int rx_channel;
25 int tx_channel;
26 unsigned long dest_start;
27 unsigned long src_start;
28 int tx_trigger;
29 int rx_trigger;
30 int mode;
31};
32
33#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
new file mode 100644
index 000000000000..ce5dd2d1dc21
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -0,0 +1,492 @@
1/*
2 * arch/arm/plat-omap/include/mach/irqs.h
3 *
4 * Copyright (C) Greg Lonnon 2001
5 * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
25 * are different.
26 */
27
28#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
29#define __ASM_ARCH_OMAP15XX_IRQS_H
30
31/*
32 * IRQ numbers for interrupt handler 1
33 *
34 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
35 *
36 */
37#define INT_CAMERA 1
38#define INT_FIQ 3
39#define INT_RTDX 6
40#define INT_DSP_MMU_ABORT 7
41#define INT_HOST 8
42#define INT_ABORT 9
43#define INT_BRIDGE_PRIV 13
44#define INT_GPIO_BANK1 14
45#define INT_UART3 15
46#define INT_TIMER3 16
47#define INT_DMA_CH0_6 19
48#define INT_DMA_CH1_7 20
49#define INT_DMA_CH2_8 21
50#define INT_DMA_CH3 22
51#define INT_DMA_CH4 23
52#define INT_DMA_CH5 24
53#define INT_DMA_LCD 25
54#define INT_TIMER1 26
55#define INT_WD_TIMER 27
56#define INT_BRIDGE_PUB 28
57#define INT_TIMER2 30
58#define INT_LCD_CTRL 31
59
60/*
61 * OMAP-1510 specific IRQ numbers for interrupt handler 1
62 */
63#define INT_1510_IH2_IRQ 0
64#define INT_1510_RES2 2
65#define INT_1510_SPI_TX 4
66#define INT_1510_SPI_RX 5
67#define INT_1510_DSP_MAILBOX1 10
68#define INT_1510_DSP_MAILBOX2 11
69#define INT_1510_RES12 12
70#define INT_1510_LB_MMU 17
71#define INT_1510_RES18 18
72#define INT_1510_LOCAL_BUS 29
73
74/*
75 * OMAP-1610 specific IRQ numbers for interrupt handler 1
76 */
77#define INT_1610_IH2_IRQ 0
78#define INT_1610_IH2_FIQ 2
79#define INT_1610_McBSP2_TX 4
80#define INT_1610_McBSP2_RX 5
81#define INT_1610_DSP_MAILBOX1 10
82#define INT_1610_DSP_MAILBOX2 11
83#define INT_1610_LCD_LINE 12
84#define INT_1610_GPTIMER1 17
85#define INT_1610_GPTIMER2 18
86#define INT_1610_SSR_FIFO_0 29
87
88/*
89 * OMAP-7xx specific IRQ numbers for interrupt handler 1
90 */
91#define INT_7XX_IH2_FIQ 0
92#define INT_7XX_IH2_IRQ 1
93#define INT_7XX_USB_NON_ISO 2
94#define INT_7XX_USB_ISO 3
95#define INT_7XX_ICR 4
96#define INT_7XX_EAC 5
97#define INT_7XX_GPIO_BANK1 6
98#define INT_7XX_GPIO_BANK2 7
99#define INT_7XX_GPIO_BANK3 8
100#define INT_7XX_McBSP2TX 10
101#define INT_7XX_McBSP2RX 11
102#define INT_7XX_McBSP2RX_OVF 12
103#define INT_7XX_LCD_LINE 14
104#define INT_7XX_GSM_PROTECT 15
105#define INT_7XX_TIMER3 16
106#define INT_7XX_GPIO_BANK5 17
107#define INT_7XX_GPIO_BANK6 18
108#define INT_7XX_SPGIO_WR 29
109
110/*
111 * IRQ numbers for interrupt handler 2
112 *
113 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
114 */
115#define IH2_BASE 32
116
117#define INT_KEYBOARD (1 + IH2_BASE)
118#define INT_uWireTX (2 + IH2_BASE)
119#define INT_uWireRX (3 + IH2_BASE)
120#define INT_I2C (4 + IH2_BASE)
121#define INT_MPUIO (5 + IH2_BASE)
122#define INT_USB_HHC_1 (6 + IH2_BASE)
123#define INT_McBSP3TX (10 + IH2_BASE)
124#define INT_McBSP3RX (11 + IH2_BASE)
125#define INT_McBSP1TX (12 + IH2_BASE)
126#define INT_McBSP1RX (13 + IH2_BASE)
127#define INT_UART1 (14 + IH2_BASE)
128#define INT_UART2 (15 + IH2_BASE)
129#define INT_BT_MCSI1TX (16 + IH2_BASE)
130#define INT_BT_MCSI1RX (17 + IH2_BASE)
131#define INT_SOSSI_MATCH (19 + IH2_BASE)
132#define INT_USB_W2FC (20 + IH2_BASE)
133#define INT_1WIRE (21 + IH2_BASE)
134#define INT_OS_TIMER (22 + IH2_BASE)
135#define INT_MMC (23 + IH2_BASE)
136#define INT_GAUGE_32K (24 + IH2_BASE)
137#define INT_RTC_TIMER (25 + IH2_BASE)
138#define INT_RTC_ALARM (26 + IH2_BASE)
139#define INT_MEM_STICK (27 + IH2_BASE)
140
141/*
142 * OMAP-1510 specific IRQ numbers for interrupt handler 2
143 */
144#define INT_1510_DSP_MMU (28 + IH2_BASE)
145#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
146
147/*
148 * OMAP-1610 specific IRQ numbers for interrupt handler 2
149 */
150#define INT_1610_FAC (0 + IH2_BASE)
151#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
152#define INT_1610_USB_OTG (8 + IH2_BASE)
153#define INT_1610_SoSSI (9 + IH2_BASE)
154#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
155#define INT_1610_DSP_MMU (28 + IH2_BASE)
156#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
157#define INT_1610_STI (32 + IH2_BASE)
158#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
159#define INT_1610_GPTIMER3 (34 + IH2_BASE)
160#define INT_1610_GPTIMER4 (35 + IH2_BASE)
161#define INT_1610_GPTIMER5 (36 + IH2_BASE)
162#define INT_1610_GPTIMER6 (37 + IH2_BASE)
163#define INT_1610_GPTIMER7 (38 + IH2_BASE)
164#define INT_1610_GPTIMER8 (39 + IH2_BASE)
165#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
166#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
167#define INT_1610_MMC2 (42 + IH2_BASE)
168#define INT_1610_CF (43 + IH2_BASE)
169#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
170#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
171#define INT_1610_SPI (49 + IH2_BASE)
172#define INT_1610_DMA_CH6 (53 + IH2_BASE)
173#define INT_1610_DMA_CH7 (54 + IH2_BASE)
174#define INT_1610_DMA_CH8 (55 + IH2_BASE)
175#define INT_1610_DMA_CH9 (56 + IH2_BASE)
176#define INT_1610_DMA_CH10 (57 + IH2_BASE)
177#define INT_1610_DMA_CH11 (58 + IH2_BASE)
178#define INT_1610_DMA_CH12 (59 + IH2_BASE)
179#define INT_1610_DMA_CH13 (60 + IH2_BASE)
180#define INT_1610_DMA_CH14 (61 + IH2_BASE)
181#define INT_1610_DMA_CH15 (62 + IH2_BASE)
182#define INT_1610_NAND (63 + IH2_BASE)
183#define INT_1610_SHA1MD5 (91 + IH2_BASE)
184
185/*
186 * OMAP-7xx specific IRQ numbers for interrupt handler 2
187 */
188#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
189#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
190#define INT_7XX_CFCD (2 + IH2_BASE)
191#define INT_7XX_CFIREQ (3 + IH2_BASE)
192#define INT_7XX_I2C (4 + IH2_BASE)
193#define INT_7XX_PCC (5 + IH2_BASE)
194#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
195#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
196#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
197#define INT_7XX_VLYNQ (9 + IH2_BASE)
198#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
199#define INT_7XX_McBSP1TX (11 + IH2_BASE)
200#define INT_7XX_McBSP1RX (12 + IH2_BASE)
201#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
202#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
203#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
204#define INT_7XX_MCSI (16 + IH2_BASE)
205#define INT_7XX_uWireTX (17 + IH2_BASE)
206#define INT_7XX_uWireRX (18 + IH2_BASE)
207#define INT_7XX_SMC_CD (19 + IH2_BASE)
208#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
209#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
210#define INT_7XX_TIMER32K (22 + IH2_BASE)
211#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
212#define INT_7XX_UPLD (24 + IH2_BASE)
213#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
214#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
215#define INT_7XX_USB_GENI (29 + IH2_BASE)
216#define INT_7XX_USB_OTG (30 + IH2_BASE)
217#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
218#define INT_7XX_RNG (32 + IH2_BASE)
219#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
220#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
221#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
222#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
223#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
224#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
225#define INT_7XX_MPUIO (39 + IH2_BASE)
226#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
227#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
228#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
229#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
230#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
231#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
232#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
233#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
234#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
235#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
236#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
237#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
238#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
239#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
240#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
241#define INT_7XX_NAND (63 + IH2_BASE)
242
243#define INT_24XX_SYS_NIRQ 7
244#define INT_24XX_SDMA_IRQ0 12
245#define INT_24XX_SDMA_IRQ1 13
246#define INT_24XX_SDMA_IRQ2 14
247#define INT_24XX_SDMA_IRQ3 15
248#define INT_24XX_CAM_IRQ 24
249#define INT_24XX_DSS_IRQ 25
250#define INT_24XX_MAIL_U0_MPU 26
251#define INT_24XX_DSP_UMA 27
252#define INT_24XX_DSP_MMU 28
253#define INT_24XX_GPIO_BANK1 29
254#define INT_24XX_GPIO_BANK2 30
255#define INT_24XX_GPIO_BANK3 31
256#define INT_24XX_GPIO_BANK4 32
257#define INT_24XX_GPIO_BANK5 33
258#define INT_24XX_MAIL_U3_MPU 34
259#define INT_24XX_GPTIMER1 37
260#define INT_24XX_GPTIMER2 38
261#define INT_24XX_GPTIMER3 39
262#define INT_24XX_GPTIMER4 40
263#define INT_24XX_GPTIMER5 41
264#define INT_24XX_GPTIMER6 42
265#define INT_24XX_GPTIMER7 43
266#define INT_24XX_GPTIMER8 44
267#define INT_24XX_GPTIMER9 45
268#define INT_24XX_GPTIMER10 46
269#define INT_24XX_GPTIMER11 47
270#define INT_24XX_GPTIMER12 48
271#define INT_24XX_SHA1MD5 51
272#define INT_24XX_MCBSP4_IRQ_TX 54
273#define INT_24XX_MCBSP4_IRQ_RX 55
274#define INT_24XX_I2C1_IRQ 56
275#define INT_24XX_I2C2_IRQ 57
276#define INT_24XX_HDQ_IRQ 58
277#define INT_24XX_MCBSP1_IRQ_TX 59
278#define INT_24XX_MCBSP1_IRQ_RX 60
279#define INT_24XX_MCBSP2_IRQ_TX 62
280#define INT_24XX_MCBSP2_IRQ_RX 63
281#define INT_24XX_SPI1_IRQ 65
282#define INT_24XX_SPI2_IRQ 66
283#define INT_24XX_UART1_IRQ 72
284#define INT_24XX_UART2_IRQ 73
285#define INT_24XX_UART3_IRQ 74
286#define INT_24XX_USB_IRQ_GEN 75
287#define INT_24XX_USB_IRQ_NISO 76
288#define INT_24XX_USB_IRQ_ISO 77
289#define INT_24XX_USB_IRQ_HGEN 78
290#define INT_24XX_USB_IRQ_HSOF 79
291#define INT_24XX_USB_IRQ_OTG 80
292#define INT_24XX_MCBSP5_IRQ_TX 81
293#define INT_24XX_MCBSP5_IRQ_RX 82
294#define INT_24XX_MMC_IRQ 83
295#define INT_24XX_MMC2_IRQ 86
296#define INT_24XX_MCBSP3_IRQ_TX 89
297#define INT_24XX_MCBSP3_IRQ_RX 90
298#define INT_24XX_SPI3_IRQ 91
299
300#define INT_243X_MCBSP2_IRQ 16
301#define INT_243X_MCBSP3_IRQ 17
302#define INT_243X_MCBSP4_IRQ 18
303#define INT_243X_MCBSP5_IRQ 19
304#define INT_243X_MCBSP1_IRQ 64
305#define INT_243X_HS_USB_MC 92
306#define INT_243X_HS_USB_DMA 93
307#define INT_243X_CARKIT_IRQ 94
308
309#define INT_34XX_BENCH_MPU_EMUL 3
310#define INT_34XX_ST_MCBSP2_IRQ 4
311#define INT_34XX_ST_MCBSP3_IRQ 5
312#define INT_34XX_SSM_ABORT_IRQ 6
313#define INT_34XX_SYS_NIRQ 7
314#define INT_34XX_D2D_FW_IRQ 8
315#define INT_34XX_PRCM_MPU_IRQ 11
316#define INT_34XX_MCBSP1_IRQ 16
317#define INT_34XX_MCBSP2_IRQ 17
318#define INT_34XX_MCBSP3_IRQ 22
319#define INT_34XX_MCBSP4_IRQ 23
320#define INT_34XX_CAM_IRQ 24
321#define INT_34XX_MCBSP5_IRQ 27
322#define INT_34XX_GPIO_BANK1 29
323#define INT_34XX_GPIO_BANK2 30
324#define INT_34XX_GPIO_BANK3 31
325#define INT_34XX_GPIO_BANK4 32
326#define INT_34XX_GPIO_BANK5 33
327#define INT_34XX_GPIO_BANK6 34
328#define INT_34XX_USIM_IRQ 35
329#define INT_34XX_WDT3_IRQ 36
330#define INT_34XX_SPI4_IRQ 48
331#define INT_34XX_SHA1MD52_IRQ 49
332#define INT_34XX_FPKA_READY_IRQ 50
333#define INT_34XX_SHA1MD51_IRQ 51
334#define INT_34XX_RNG_IRQ 52
335#define INT_34XX_I2C3_IRQ 61
336#define INT_34XX_FPKA_ERROR_IRQ 64
337#define INT_34XX_PBIAS_IRQ 75
338#define INT_34XX_OHCI_IRQ 76
339#define INT_34XX_EHCI_IRQ 77
340#define INT_34XX_TLL_IRQ 78
341#define INT_34XX_PARTHASH_IRQ 79
342#define INT_34XX_MMC3_IRQ 94
343#define INT_34XX_GPT12_IRQ 95
344
345#define INT_34XX_BENCH_MPU_EMUL 3
346
347
348#define IRQ_GIC_START 32
349#define INT_44XX_LOCALTIMER_IRQ 29
350#define INT_44XX_LOCALWDT_IRQ 30
351
352#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
353#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START)
354#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START)
355#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START)
356#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START)
357#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START)
358#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START)
359#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START)
360#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START)
361#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START)
362#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START)
363#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START)
364#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START)
365#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START)
366#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START)
367#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START)
368#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START)
369#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START)
370#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START)
371#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START)
372#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START)
373#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START)
374#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START)
375#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START)
376#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START)
377#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START)
378#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START)
379#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START)
380#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START)
381#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START)
382#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START)
383#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START)
384#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START)
385#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START)
386#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START)
387#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START)
388#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START)
389#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START)
390#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START)
391#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START)
392#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START)
393#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START)
394#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START)
395#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START)
396#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START)
397#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START)
398#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START)
399#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START)
400#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START)
401#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START)
402#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START)
403
404#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START)
405#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START)
406#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START)
407#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START)
408#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START)
409#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START)
410#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START)
411
412#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START)
413#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START)
414#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START)
415#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START)
416#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START)
417#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START)
418#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START)
419#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START)
420#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START)
421#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START)
422#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
423#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START)
424#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START)
425#define INT_44XX_MMC5_IRQ (59 + IRQ_GIC_START)
426#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START)
427#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
428#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START)
429#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START)
430#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START)
431#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START)
432#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START)
433#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START)
434#define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START)
435
436
437/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
438 * 16 MPUIO lines */
439#define OMAP_MAX_GPIO_LINES 192
440#define IH_GPIO_BASE (128 + IH2_BASE)
441#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
442#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
443
444/* External FPGA handles interrupts on Innovator boards */
445#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
446#ifdef CONFIG_MACH_OMAP_INNOVATOR
447#define OMAP_FPGA_NR_IRQS 24
448#else
449#define OMAP_FPGA_NR_IRQS 0
450#endif
451#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
452
453/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
454#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
455#ifdef CONFIG_TWL4030_CORE
456#define TWL4030_BASE_NR_IRQS 8
457#define TWL4030_PWR_NR_IRQS 8
458#else
459#define TWL4030_BASE_NR_IRQS 0
460#define TWL4030_PWR_NR_IRQS 0
461#endif
462#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
463#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
464#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
465
466/* External TWL4030 gpio interrupts are optional */
467#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
468#ifdef CONFIG_GPIO_TWL4030
469#define TWL4030_GPIO_NR_IRQS 18
470#else
471#define TWL4030_GPIO_NR_IRQS 0
472#endif
473#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
474
475/* Total number of interrupts depends on the enabled blocks above */
476#define NR_IRQS TWL4030_GPIO_IRQ_END
477
478#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
479
480#define INTCPS_NR_MIR_REGS 3
481#define INTCPS_NR_IRQS 96
482
483#ifndef __ASSEMBLY__
484extern void omap_init_irq(void);
485extern int omap_irq_pending(void);
486void omap_intc_save_context(void);
487void omap_intc_restore_context(void);
488#endif
489
490#include <mach/hardware.h>
491
492#endif
diff --git a/arch/arm/plat-omap/include/plat/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h
new file mode 100644
index 000000000000..3ae52ccc793c
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/keypad.h
@@ -0,0 +1,45 @@
1/*
2 * arch/arm/plat-omap/include/mach/keypad.h
3 *
4 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef ASMARM_ARCH_KEYPAD_H
11#define ASMARM_ARCH_KEYPAD_H
12
13#warning: Please update the board to use matrix_keypad.h instead
14
15struct omap_kp_platform_data {
16 int rows;
17 int cols;
18 int *keymap;
19 unsigned int keymapsize;
20 unsigned int rep:1;
21 unsigned long delay;
22 unsigned int dbounce:1;
23 /* specific to OMAP242x*/
24 unsigned int *row_gpios;
25 unsigned int *col_gpios;
26};
27
28/* Group (0..3) -- when multiple keys are pressed, only the
29 * keys pressed in the same group are considered as pressed. This is
30 * in order to workaround certain crappy HW designs that produce ghost
31 * keypresses. */
32#define GROUP_0 (0 << 16)
33#define GROUP_1 (1 << 16)
34#define GROUP_2 (2 << 16)
35#define GROUP_3 (3 << 16)
36#define GROUP_MASK GROUP_3
37
38#define KEY_PERSISTENT 0x00800000
39#define KEYNUM_MASK 0x00EFFFFF
40#define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val))
41#define PERSISTENT_KEY(col, row) (((col) << 28) | ((row) << 24) | \
42 KEY_PERSISTENT)
43
44#endif
45
diff --git a/arch/arm/plat-omap/include/plat/lcd_mipid.h b/arch/arm/plat-omap/include/plat/lcd_mipid.h
new file mode 100644
index 000000000000..8e52c6572281
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/lcd_mipid.h
@@ -0,0 +1,29 @@
1#ifndef __LCD_MIPID_H
2#define __LCD_MIPID_H
3
4enum mipid_test_num {
5 MIPID_TEST_RGB_LINES,
6};
7
8enum mipid_test_result {
9 MIPID_TEST_SUCCESS,
10 MIPID_TEST_INVALID,
11 MIPID_TEST_FAILED,
12};
13
14#ifdef __KERNEL__
15
16struct mipid_platform_data {
17 int nreset_gpio;
18 int data_lines;
19
20 void (*shutdown)(struct mipid_platform_data *pdata);
21 void (*set_bklight_level)(struct mipid_platform_data *pdata,
22 int level);
23 int (*get_bklight_level)(struct mipid_platform_data *pdata);
24 int (*get_bklight_max)(struct mipid_platform_data *pdata);
25};
26
27#endif
28
29#endif
diff --git a/arch/arm/plat-omap/include/plat/led.h b/arch/arm/plat-omap/include/plat/led.h
new file mode 100644
index 000000000000..25e451e7e2fd
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/led.h
@@ -0,0 +1,24 @@
1/*
2 * arch/arm/plat-omap/include/mach/led.h
3 *
4 * Copyright (C) 2006 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef ASMARM_ARCH_LED_H
12#define ASMARM_ARCH_LED_H
13
14struct omap_led_config {
15 struct led_classdev cdev;
16 s16 gpio;
17};
18
19struct omap_led_platform_data {
20 s16 nr_leds;
21 struct omap_led_config *leds;
22};
23
24#endif
diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
new file mode 100644
index 000000000000..b7a6991814ec
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/mailbox.h
@@ -0,0 +1,96 @@
1/* mailbox.h */
2
3#ifndef MAILBOX_H
4#define MAILBOX_H
5
6#include <linux/wait.h>
7#include <linux/workqueue.h>
8#include <linux/blkdev.h>
9
10typedef u32 mbox_msg_t;
11typedef void (mbox_receiver_t)(mbox_msg_t msg);
12struct omap_mbox;
13
14typedef int __bitwise omap_mbox_irq_t;
15#define IRQ_TX ((__force omap_mbox_irq_t) 1)
16#define IRQ_RX ((__force omap_mbox_irq_t) 2)
17
18typedef int __bitwise omap_mbox_type_t;
19#define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1)
20#define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2)
21
22struct omap_mbox_ops {
23 omap_mbox_type_t type;
24 int (*startup)(struct omap_mbox *mbox);
25 void (*shutdown)(struct omap_mbox *mbox);
26 /* fifo */
27 mbox_msg_t (*fifo_read)(struct omap_mbox *mbox);
28 void (*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg);
29 int (*fifo_empty)(struct omap_mbox *mbox);
30 int (*fifo_full)(struct omap_mbox *mbox);
31 /* irq */
32 void (*enable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
33 void (*disable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
34 void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
35 int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
36 /* ctx */
37 void (*save_ctx)(struct omap_mbox *mbox);
38 void (*restore_ctx)(struct omap_mbox *mbox);
39};
40
41struct omap_mbox_queue {
42 spinlock_t lock;
43 struct request_queue *queue;
44 struct work_struct work;
45 int (*callback)(void *);
46 struct omap_mbox *mbox;
47};
48
49struct omap_mbox {
50 char *name;
51 unsigned int irq;
52
53 struct omap_mbox_queue *txq, *rxq;
54
55 struct omap_mbox_ops *ops;
56
57 mbox_msg_t seq_snd, seq_rcv;
58
59 struct device *dev;
60
61 struct omap_mbox *next;
62 void *priv;
63
64 void (*err_notify)(void);
65};
66
67int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg, void *);
68void omap_mbox_init_seq(struct omap_mbox *);
69
70struct omap_mbox *omap_mbox_get(const char *);
71void omap_mbox_put(struct omap_mbox *);
72
73int omap_mbox_register(struct device *parent, struct omap_mbox *);
74int omap_mbox_unregister(struct omap_mbox *);
75
76static inline void omap_mbox_save_ctx(struct omap_mbox *mbox)
77{
78 if (!mbox->ops->save_ctx) {
79 dev_err(mbox->dev, "%s:\tno save\n", __func__);
80 return;
81 }
82
83 mbox->ops->save_ctx(mbox);
84}
85
86static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
87{
88 if (!mbox->ops->restore_ctx) {
89 dev_err(mbox->dev, "%s:\tno restore\n", __func__);
90 return;
91 }
92
93 mbox->ops->restore_ctx(mbox);
94}
95
96#endif /* MAILBOX_H */
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
new file mode 100644
index 000000000000..4f22e5bb7ff7
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -0,0 +1,462 @@
1/*
2 * arch/arm/plat-omap/include/mach/mcbsp.h
3 *
4 * Defines for Multi-Channel Buffered Serial Port
5 *
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Author: Steve Johnson
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24#ifndef __ASM_ARCH_OMAP_MCBSP_H
25#define __ASM_ARCH_OMAP_MCBSP_H
26
27#include <linux/completion.h>
28#include <linux/spinlock.h>
29
30#include <mach/hardware.h>
31#include <plat/clock.h>
32
33#define OMAP7XX_MCBSP1_BASE 0xfffb1000
34#define OMAP7XX_MCBSP2_BASE 0xfffb1800
35
36#define OMAP1510_MCBSP1_BASE 0xe1011800
37#define OMAP1510_MCBSP2_BASE 0xfffb1000
38#define OMAP1510_MCBSP3_BASE 0xe1017000
39
40#define OMAP1610_MCBSP1_BASE 0xe1011800
41#define OMAP1610_MCBSP2_BASE 0xfffb1000
42#define OMAP1610_MCBSP3_BASE 0xe1017000
43
44#define OMAP24XX_MCBSP1_BASE 0x48074000
45#define OMAP24XX_MCBSP2_BASE 0x48076000
46#define OMAP2430_MCBSP3_BASE 0x4808c000
47#define OMAP2430_MCBSP4_BASE 0x4808e000
48#define OMAP2430_MCBSP5_BASE 0x48096000
49
50#define OMAP34XX_MCBSP1_BASE 0x48074000
51#define OMAP34XX_MCBSP2_BASE 0x49022000
52#define OMAP34XX_MCBSP3_BASE 0x49024000
53#define OMAP34XX_MCBSP4_BASE 0x49026000
54#define OMAP34XX_MCBSP5_BASE 0x48096000
55
56#define OMAP44XX_MCBSP1_BASE 0x49022000
57#define OMAP44XX_MCBSP2_BASE 0x49024000
58#define OMAP44XX_MCBSP3_BASE 0x49026000
59#define OMAP44XX_MCBSP4_BASE 0x48074000
60
61#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
62
63#define OMAP_MCBSP_REG_DRR2 0x00
64#define OMAP_MCBSP_REG_DRR1 0x02
65#define OMAP_MCBSP_REG_DXR2 0x04
66#define OMAP_MCBSP_REG_DXR1 0x06
67#define OMAP_MCBSP_REG_SPCR2 0x08
68#define OMAP_MCBSP_REG_SPCR1 0x0a
69#define OMAP_MCBSP_REG_RCR2 0x0c
70#define OMAP_MCBSP_REG_RCR1 0x0e
71#define OMAP_MCBSP_REG_XCR2 0x10
72#define OMAP_MCBSP_REG_XCR1 0x12
73#define OMAP_MCBSP_REG_SRGR2 0x14
74#define OMAP_MCBSP_REG_SRGR1 0x16
75#define OMAP_MCBSP_REG_MCR2 0x18
76#define OMAP_MCBSP_REG_MCR1 0x1a
77#define OMAP_MCBSP_REG_RCERA 0x1c
78#define OMAP_MCBSP_REG_RCERB 0x1e
79#define OMAP_MCBSP_REG_XCERA 0x20
80#define OMAP_MCBSP_REG_XCERB 0x22
81#define OMAP_MCBSP_REG_PCR0 0x24
82#define OMAP_MCBSP_REG_RCERC 0x26
83#define OMAP_MCBSP_REG_RCERD 0x28
84#define OMAP_MCBSP_REG_XCERC 0x2A
85#define OMAP_MCBSP_REG_XCERD 0x2C
86#define OMAP_MCBSP_REG_RCERE 0x2E
87#define OMAP_MCBSP_REG_RCERF 0x30
88#define OMAP_MCBSP_REG_XCERE 0x32
89#define OMAP_MCBSP_REG_XCERF 0x34
90#define OMAP_MCBSP_REG_RCERG 0x36
91#define OMAP_MCBSP_REG_RCERH 0x38
92#define OMAP_MCBSP_REG_XCERG 0x3A
93#define OMAP_MCBSP_REG_XCERH 0x3C
94
95/* Dummy defines, these are not available on omap1 */
96#define OMAP_MCBSP_REG_XCCR 0x00
97#define OMAP_MCBSP_REG_RCCR 0x00
98
99#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
100#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
101
102#define AUDIO_MCBSP OMAP_MCBSP1
103#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
104#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
105
106#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
107 defined(CONFIG_ARCH_OMAP4)
108
109#define OMAP_MCBSP_REG_DRR2 0x00
110#define OMAP_MCBSP_REG_DRR1 0x04
111#define OMAP_MCBSP_REG_DXR2 0x08
112#define OMAP_MCBSP_REG_DXR1 0x0C
113#define OMAP_MCBSP_REG_DRR 0x00
114#define OMAP_MCBSP_REG_DXR 0x08
115#define OMAP_MCBSP_REG_SPCR2 0x10
116#define OMAP_MCBSP_REG_SPCR1 0x14
117#define OMAP_MCBSP_REG_RCR2 0x18
118#define OMAP_MCBSP_REG_RCR1 0x1C
119#define OMAP_MCBSP_REG_XCR2 0x20
120#define OMAP_MCBSP_REG_XCR1 0x24
121#define OMAP_MCBSP_REG_SRGR2 0x28
122#define OMAP_MCBSP_REG_SRGR1 0x2C
123#define OMAP_MCBSP_REG_MCR2 0x30
124#define OMAP_MCBSP_REG_MCR1 0x34
125#define OMAP_MCBSP_REG_RCERA 0x38
126#define OMAP_MCBSP_REG_RCERB 0x3C
127#define OMAP_MCBSP_REG_XCERA 0x40
128#define OMAP_MCBSP_REG_XCERB 0x44
129#define OMAP_MCBSP_REG_PCR0 0x48
130#define OMAP_MCBSP_REG_RCERC 0x4C
131#define OMAP_MCBSP_REG_RCERD 0x50
132#define OMAP_MCBSP_REG_XCERC 0x54
133#define OMAP_MCBSP_REG_XCERD 0x58
134#define OMAP_MCBSP_REG_RCERE 0x5C
135#define OMAP_MCBSP_REG_RCERF 0x60
136#define OMAP_MCBSP_REG_XCERE 0x64
137#define OMAP_MCBSP_REG_XCERF 0x68
138#define OMAP_MCBSP_REG_RCERG 0x6C
139#define OMAP_MCBSP_REG_RCERH 0x70
140#define OMAP_MCBSP_REG_XCERG 0x74
141#define OMAP_MCBSP_REG_XCERH 0x78
142#define OMAP_MCBSP_REG_SYSCON 0x8C
143#define OMAP_MCBSP_REG_THRSH2 0x90
144#define OMAP_MCBSP_REG_THRSH1 0x94
145#define OMAP_MCBSP_REG_IRQST 0xA0
146#define OMAP_MCBSP_REG_IRQEN 0xA4
147#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
148#define OMAP_MCBSP_REG_XCCR 0xAC
149#define OMAP_MCBSP_REG_RCCR 0xB0
150
151#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
152#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
153
154#define AUDIO_MCBSP OMAP_MCBSP2
155#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX
156#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX
157
158#endif
159
160/************************** McBSP SPCR1 bit definitions ***********************/
161#define RRST 0x0001
162#define RRDY 0x0002
163#define RFULL 0x0004
164#define RSYNC_ERR 0x0008
165#define RINTM(value) ((value)<<4) /* bits 4:5 */
166#define ABIS 0x0040
167#define DXENA 0x0080
168#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
169#define RJUST(value) ((value)<<13) /* bits 13:14 */
170#define ALB 0x8000
171#define DLB 0x8000
172
173/************************** McBSP SPCR2 bit definitions ***********************/
174#define XRST 0x0001
175#define XRDY 0x0002
176#define XEMPTY 0x0004
177#define XSYNC_ERR 0x0008
178#define XINTM(value) ((value)<<4) /* bits 4:5 */
179#define GRST 0x0040
180#define FRST 0x0080
181#define SOFT 0x0100
182#define FREE 0x0200
183
184/************************** McBSP PCR bit definitions *************************/
185#define CLKRP 0x0001
186#define CLKXP 0x0002
187#define FSRP 0x0004
188#define FSXP 0x0008
189#define DR_STAT 0x0010
190#define DX_STAT 0x0020
191#define CLKS_STAT 0x0040
192#define SCLKME 0x0080
193#define CLKRM 0x0100
194#define CLKXM 0x0200
195#define FSRM 0x0400
196#define FSXM 0x0800
197#define RIOEN 0x1000
198#define XIOEN 0x2000
199#define IDLE_EN 0x4000
200
201/************************** McBSP RCR1 bit definitions ************************/
202#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
203#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
204
205/************************** McBSP XCR1 bit definitions ************************/
206#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
207#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
208
209/*************************** McBSP RCR2 bit definitions ***********************/
210#define RDATDLY(value) (value) /* Bits 0:1 */
211#define RFIG 0x0004
212#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
213#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
214#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
215#define RPHASE 0x8000
216
217/*************************** McBSP XCR2 bit definitions ***********************/
218#define XDATDLY(value) (value) /* Bits 0:1 */
219#define XFIG 0x0004
220#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
221#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
222#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
223#define XPHASE 0x8000
224
225/************************* McBSP SRGR1 bit definitions ************************/
226#define CLKGDV(value) (value) /* Bits 0:7 */
227#define FWID(value) ((value)<<8) /* Bits 8:15 */
228
229/************************* McBSP SRGR2 bit definitions ************************/
230#define FPER(value) (value) /* Bits 0:11 */
231#define FSGM 0x1000
232#define CLKSM 0x2000
233#define CLKSP 0x4000
234#define GSYNC 0x8000
235
236/************************* McBSP MCR1 bit definitions *************************/
237#define RMCM 0x0001
238#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
239#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
240#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
241
242/************************* McBSP MCR2 bit definitions *************************/
243#define XMCM(value) (value) /* Bits 0:1 */
244#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
245#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
246#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
247
248/*********************** McBSP XCCR bit definitions *************************/
249#define EXTCLKGATE 0x8000
250#define PPCONNECT 0x4000
251#define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
252#define XFULL_CYCLE 0x0800
253#define DILB 0x0020
254#define XDMAEN 0x0008
255#define XDISABLE 0x0001
256
257/********************** McBSP RCCR bit definitions *************************/
258#define RFULL_CYCLE 0x0800
259#define RDMAEN 0x0008
260#define RDISABLE 0x0001
261
262/********************** McBSP SYSCONFIG bit definitions ********************/
263#define CLOCKACTIVITY(value) ((value)<<8)
264#define SIDLEMODE(value) ((value)<<3)
265#define ENAWAKEUP 0x0004
266#define SOFTRST 0x0002
267
268/********************** McBSP DMA operating modes **************************/
269#define MCBSP_DMA_MODE_ELEMENT 0
270#define MCBSP_DMA_MODE_THRESHOLD 1
271#define MCBSP_DMA_MODE_FRAME 2
272
273/********************** McBSP WAKEUPEN bit definitions *********************/
274#define XEMPTYEOFEN 0x4000
275#define XRDYEN 0x0400
276#define XEOFEN 0x0200
277#define XFSXEN 0x0100
278#define XSYNCERREN 0x0080
279#define RRDYEN 0x0008
280#define REOFEN 0x0004
281#define RFSREN 0x0002
282#define RSYNCERREN 0x0001
283
284/* we don't do multichannel for now */
285struct omap_mcbsp_reg_cfg {
286 u16 spcr2;
287 u16 spcr1;
288 u16 rcr2;
289 u16 rcr1;
290 u16 xcr2;
291 u16 xcr1;
292 u16 srgr2;
293 u16 srgr1;
294 u16 mcr2;
295 u16 mcr1;
296 u16 pcr0;
297 u16 rcerc;
298 u16 rcerd;
299 u16 xcerc;
300 u16 xcerd;
301 u16 rcere;
302 u16 rcerf;
303 u16 xcere;
304 u16 xcerf;
305 u16 rcerg;
306 u16 rcerh;
307 u16 xcerg;
308 u16 xcerh;
309 u16 xccr;
310 u16 rccr;
311};
312
313typedef enum {
314 OMAP_MCBSP1 = 0,
315 OMAP_MCBSP2,
316 OMAP_MCBSP3,
317 OMAP_MCBSP4,
318 OMAP_MCBSP5
319} omap_mcbsp_id;
320
321typedef int __bitwise omap_mcbsp_io_type_t;
322#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
323#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
324
325typedef enum {
326 OMAP_MCBSP_WORD_8 = 0,
327 OMAP_MCBSP_WORD_12,
328 OMAP_MCBSP_WORD_16,
329 OMAP_MCBSP_WORD_20,
330 OMAP_MCBSP_WORD_24,
331 OMAP_MCBSP_WORD_32,
332} omap_mcbsp_word_length;
333
334typedef enum {
335 OMAP_MCBSP_CLK_RISING = 0,
336 OMAP_MCBSP_CLK_FALLING,
337} omap_mcbsp_clk_polarity;
338
339typedef enum {
340 OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
341 OMAP_MCBSP_FS_ACTIVE_LOW,
342} omap_mcbsp_fs_polarity;
343
344typedef enum {
345 OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
346 OMAP_MCBSP_CLK_STP_MODE_DELAY,
347} omap_mcbsp_clk_stp_mode;
348
349
350/******* SPI specific mode **********/
351typedef enum {
352 OMAP_MCBSP_SPI_MASTER = 0,
353 OMAP_MCBSP_SPI_SLAVE,
354} omap_mcbsp_spi_mode;
355
356struct omap_mcbsp_spi_cfg {
357 omap_mcbsp_spi_mode spi_mode;
358 omap_mcbsp_clk_polarity rx_clock_polarity;
359 omap_mcbsp_clk_polarity tx_clock_polarity;
360 omap_mcbsp_fs_polarity fsx_polarity;
361 u8 clk_div;
362 omap_mcbsp_clk_stp_mode clk_stp_mode;
363 omap_mcbsp_word_length word_length;
364};
365
366/* Platform specific configuration */
367struct omap_mcbsp_ops {
368 void (*request)(unsigned int);
369 void (*free)(unsigned int);
370};
371
372struct omap_mcbsp_platform_data {
373 unsigned long phys_base;
374 u8 dma_rx_sync, dma_tx_sync;
375 u16 rx_irq, tx_irq;
376 struct omap_mcbsp_ops *ops;
377#ifdef CONFIG_ARCH_OMAP34XX
378 u16 buffer_size;
379#endif
380};
381
382struct omap_mcbsp {
383 struct device *dev;
384 unsigned long phys_base;
385 void __iomem *io_base;
386 u8 id;
387 u8 free;
388 omap_mcbsp_word_length rx_word_length;
389 omap_mcbsp_word_length tx_word_length;
390
391 omap_mcbsp_io_type_t io_type; /* IRQ or poll */
392 /* IRQ based TX/RX */
393 int rx_irq;
394 int tx_irq;
395
396 /* DMA stuff */
397 u8 dma_rx_sync;
398 short dma_rx_lch;
399 u8 dma_tx_sync;
400 short dma_tx_lch;
401
402 /* Completion queues */
403 struct completion tx_irq_completion;
404 struct completion rx_irq_completion;
405 struct completion tx_dma_completion;
406 struct completion rx_dma_completion;
407
408 /* Protect the field .free, while checking if the mcbsp is in use */
409 spinlock_t lock;
410 struct omap_mcbsp_platform_data *pdata;
411 struct clk *iclk;
412 struct clk *fclk;
413#ifdef CONFIG_ARCH_OMAP34XX
414 int dma_op_mode;
415 u16 max_tx_thres;
416 u16 max_rx_thres;
417#endif
418};
419extern struct omap_mcbsp **mcbsp_ptr;
420extern int omap_mcbsp_count;
421
422int omap_mcbsp_init(void);
423void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
424 int size);
425void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
426#ifdef CONFIG_ARCH_OMAP34XX
427void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
428void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
429u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
430u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
431int omap_mcbsp_get_dma_op_mode(unsigned int id);
432#else
433static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
434{ }
435static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
436{ }
437static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
438static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
439static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
440#endif
441int omap_mcbsp_request(unsigned int id);
442void omap_mcbsp_free(unsigned int id);
443void omap_mcbsp_start(unsigned int id, int tx, int rx);
444void omap_mcbsp_stop(unsigned int id, int tx, int rx);
445void omap_mcbsp_xmit_word(unsigned int id, u32 word);
446u32 omap_mcbsp_recv_word(unsigned int id);
447
448int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
449int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
450int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
451int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
452
453
454/* SPI specific API */
455void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
456
457/* Polled read/write functions */
458int omap_mcbsp_pollread(unsigned int id, u16 * buf);
459int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
460int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
461
462#endif
diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
new file mode 100644
index 000000000000..1254e4945b6f
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/mcspi.h
@@ -0,0 +1,15 @@
1#ifndef _OMAP2_MCSPI_H
2#define _OMAP2_MCSPI_H
3
4struct omap2_mcspi_platform_config {
5 unsigned short num_cs;
6};
7
8struct omap2_mcspi_device_config {
9 unsigned turbo_mode:1;
10
11 /* Do we want one channel enabled at the same time? */
12 unsigned single_channel:1;
13};
14
15#endif
diff --git a/arch/arm/plat-omap/include/plat/memory.h b/arch/arm/plat-omap/include/plat/memory.h
new file mode 100644
index 000000000000..9ad41dc484c1
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/memory.h
@@ -0,0 +1,96 @@
1/*
2 * arch/arm/plat-omap/include/mach/memory.h
3 *
4 * Memory map for OMAP-1510 and 1610
5 *
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Author: Greg Lonnon <glonnon@ridgerun.com>
8 *
9 * This file was derived from arch/arm/mach-intergrator/include/mach/memory.h
10 * Copyright (C) 1999 ARM Limited
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32
33#ifndef __ASM_ARCH_MEMORY_H
34#define __ASM_ARCH_MEMORY_H
35
36/*
37 * Physical DRAM offset.
38 */
39#if defined(CONFIG_ARCH_OMAP1)
40#define PHYS_OFFSET UL(0x10000000)
41#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
42 defined(CONFIG_ARCH_OMAP4)
43#define PHYS_OFFSET UL(0x80000000)
44#endif
45
46/*
47 * Bus address is physical address, except for OMAP-1510 Local Bus.
48 * OMAP-1510 bus address is translated into a Local Bus address if the
49 * OMAP bus type is lbus. We do the address translation based on the
50 * device overriding the defaults used in the dma-mapping API.
51 * Note that the is_lbus_device() test is not very efficient on 1510
52 * because of the strncmp().
53 */
54#ifdef CONFIG_ARCH_OMAP15XX
55
56/*
57 * OMAP-1510 Local Bus address offset
58 */
59#define OMAP1510_LB_OFFSET UL(0x30000000)
60
61#define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
62#define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
63#define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0))
64
65#define __arch_page_to_dma(dev, page) \
66 ({ dma_addr_t __dma = page_to_phys(page); \
67 if (is_lbus_device(dev)) \
68 __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \
69 __dma; })
70
71#define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \
72 lbus_to_virt(addr) : \
73 __phys_to_virt(addr)); })
74
75#define __arch_virt_to_dma(dev, addr) ({ unsigned long __addr = (unsigned long)(addr); \
76 (dma_addr_t) (is_lbus_device(dev) ? \
77 virt_to_lbus(__addr) : \
78 __virt_to_phys(__addr)); })
79
80#endif /* CONFIG_ARCH_OMAP15XX */
81
82/* Override the ARM default */
83#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
84
85#if (CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE == 0)
86#undef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
87#define CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE 2
88#endif
89
90#define CONSISTENT_DMA_SIZE \
91 (((CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024)
92
93#endif
94
95#endif
96
diff --git a/arch/arm/plat-omap/include/plat/menelaus.h b/arch/arm/plat-omap/include/plat/menelaus.h
new file mode 100644
index 000000000000..3122bf68c7ce
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/menelaus.h
@@ -0,0 +1,49 @@
1/*
2 * arch/arm/plat-omap/include/mach/menelaus.h
3 *
4 * Functions to access Menelaus power management chip
5 */
6
7#ifndef __ASM_ARCH_MENELAUS_H
8#define __ASM_ARCH_MENELAUS_H
9
10struct device;
11
12struct menelaus_platform_data {
13 int (* late_init)(struct device *dev);
14};
15
16extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
17 void *data);
18extern void menelaus_unregister_mmc_callback(void);
19extern int menelaus_set_mmc_opendrain(int slot, int enable);
20extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
21
22extern int menelaus_set_vmem(unsigned int mV);
23extern int menelaus_set_vio(unsigned int mV);
24extern int menelaus_set_vmmc(unsigned int mV);
25extern int menelaus_set_vaux(unsigned int mV);
26extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
27extern int menelaus_set_slot_sel(int enable);
28extern int menelaus_get_slot_pin_states(void);
29extern int menelaus_set_vcore_sw(unsigned int mV);
30extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
31
32#define EN_VPLL_SLEEP (1 << 7)
33#define EN_VMMC_SLEEP (1 << 6)
34#define EN_VAUX_SLEEP (1 << 5)
35#define EN_VIO_SLEEP (1 << 4)
36#define EN_VMEM_SLEEP (1 << 3)
37#define EN_DC3_SLEEP (1 << 2)
38#define EN_DC2_SLEEP (1 << 1)
39#define EN_VC_SLEEP (1 << 0)
40
41extern int menelaus_set_regulator_sleep(int enable, u32 val);
42
43#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS)
44#define omap_has_menelaus() 1
45#else
46#define omap_has_menelaus() 0
47#endif
48
49#endif
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
new file mode 100644
index 000000000000..29937137bf3e
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -0,0 +1,157 @@
1/*
2 * MMC definitions for OMAP2
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __OMAP2_MMC_H
12#define __OMAP2_MMC_H
13
14#include <linux/types.h>
15#include <linux/device.h>
16#include <linux/mmc/host.h>
17
18#include <plat/board.h>
19
20#define OMAP15XX_NR_MMC 1
21#define OMAP16XX_NR_MMC 2
22#define OMAP1_MMC_SIZE 0x080
23#define OMAP1_MMC1_BASE 0xfffb7800
24#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */
25
26#define OMAP24XX_NR_MMC 2
27#define OMAP34XX_NR_MMC 3
28#define OMAP44XX_NR_MMC 5
29#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE
30#define OMAP3_HSMMC_SIZE 0x200
31#define OMAP4_HSMMC_SIZE 0x1000
32#define OMAP2_MMC1_BASE 0x4809c000
33#define OMAP2_MMC2_BASE 0x480b4000
34#define OMAP3_MMC3_BASE 0x480ad000
35#define OMAP4_MMC4_BASE 0x480d1000
36#define OMAP4_MMC5_BASE 0x480d5000
37#define OMAP4_MMC_REG_OFFSET 0x100
38#define HSMMC5 (1 << 4)
39#define HSMMC4 (1 << 3)
40#define HSMMC3 (1 << 2)
41#define HSMMC2 (1 << 1)
42#define HSMMC1 (1 << 0)
43
44#define OMAP_MMC_MAX_SLOTS 2
45
46struct omap_mmc_platform_data {
47 /* back-link to device */
48 struct device *dev;
49
50 /* number of slots per controller */
51 unsigned nr_slots:2;
52
53 /* set if your board has components or wiring that limits the
54 * maximum frequency on the MMC bus */
55 unsigned int max_freq;
56
57 /* switch the bus to a new slot */
58 int (* switch_slot)(struct device *dev, int slot);
59 /* initialize board-specific MMC functionality, can be NULL if
60 * not supported */
61 int (* init)(struct device *dev);
62 void (* cleanup)(struct device *dev);
63 void (* shutdown)(struct device *dev);
64
65 /* To handle board related suspend/resume functionality for MMC */
66 int (*suspend)(struct device *dev, int slot);
67 int (*resume)(struct device *dev, int slot);
68
69 /* Return context loss count due to PM states changing */
70 int (*get_context_loss_count)(struct device *dev);
71
72 u64 dma_mask;
73
74 struct omap_mmc_slot_data {
75
76 /* 4 wire signaling is optional, and is used for SD/SDIO/HSMMC;
77 * 8 wire signaling is also optional, and is used with HSMMC
78 */
79 u8 wires;
80
81 /*
82 * nomux means "standard" muxing is wrong on this board, and
83 * that board-specific code handled it before common init logic.
84 */
85 unsigned nomux:1;
86
87 /* switch pin can be for card detect (default) or card cover */
88 unsigned cover:1;
89
90 /* use the internal clock */
91 unsigned internal_clock:1;
92
93 /* nonremovable e.g. eMMC */
94 unsigned nonremovable:1;
95
96 /* Try to sleep or power off when possible */
97 unsigned power_saving:1;
98
99 int switch_pin; /* gpio (card detect) */
100 int gpio_wp; /* gpio (write protect) */
101
102 int (* set_bus_mode)(struct device *dev, int slot, int bus_mode);
103 int (* set_power)(struct device *dev, int slot, int power_on, int vdd);
104 int (* get_ro)(struct device *dev, int slot);
105 int (*set_sleep)(struct device *dev, int slot, int sleep,
106 int vdd, int cardsleep);
107
108 /* return MMC cover switch state, can be NULL if not supported.
109 *
110 * possible return values:
111 * 0 - closed
112 * 1 - open
113 */
114 int (* get_cover_state)(struct device *dev, int slot);
115
116 const char *name;
117 u32 ocr_mask;
118
119 /* Card detection IRQs */
120 int card_detect_irq;
121 int (* card_detect)(int irq);
122
123 unsigned int ban_openended:1;
124
125 } slots[OMAP_MMC_MAX_SLOTS];
126};
127
128/* called from board-specific card detection service routine */
129extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed);
130
131#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
132 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
133void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
134 int nr_controllers);
135void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
136 int nr_controllers);
137int omap_mmc_add(const char *name, int id, unsigned long base,
138 unsigned long size, unsigned int irq,
139 struct omap_mmc_platform_data *data);
140#else
141static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
142 int nr_controllers)
143{
144}
145static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
146 int nr_controllers)
147{
148}
149static inline int omap_mmc_add(const char *name, int id, unsigned long base,
150 unsigned long size, unsigned int irq,
151 struct omap_mmc_platform_data *data)
152{
153 return 0;
154}
155
156#endif
157#endif
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h
new file mode 100644
index 000000000000..f3c1d8a90456
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/mux.h
@@ -0,0 +1,864 @@
1/*
2 * arch/arm/plat-omap/include/mach/mux.h
3 *
4 * Table of the Omap register configurations for the FUNC_MUX and
5 * PULL_DWN combinations.
6 *
7 * Copyright (C) 2004 - 2008 Texas Instruments Inc.
8 * Copyright (C) 2003 - 2008 Nokia Corporation
9 *
10 * Written by Tony Lindgren
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * NOTE: Please use the following naming style for new pin entries.
27 * For example, W8_1610_MMC2_DAT0, where:
28 * - W8 = ball
29 * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
30 * - MMC2_DAT0 = function
31 */
32
33#ifndef __ASM_ARCH_MUX_H
34#define __ASM_ARCH_MUX_H
35
36#define PU_PD_SEL_NA 0 /* No pu_pd reg available */
37#define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
38
39#ifdef CONFIG_OMAP_MUX_DEBUG
40#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
41 .mux_reg = FUNC_MUX_CTRL_##reg, \
42 .mask_offset = mode_offset, \
43 .mask = mode,
44
45#define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
46 .pull_reg = PULL_DWN_CTRL_##reg, \
47 .pull_bit = bit, \
48 .pull_val = status,
49
50#define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
51 .pu_pd_reg = PU_PD_SEL_##reg, \
52 .pu_pd_val = status,
53
54#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
55 .mux_reg = OMAP7XX_IO_CONF_##reg, \
56 .mask_offset = mode_offset, \
57 .mask = mode,
58
59#define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \
60 .pull_reg = OMAP7XX_IO_CONF_##reg, \
61 .pull_bit = bit, \
62 .pull_val = status,
63
64#else
65
66#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
67 .mask_offset = mode_offset, \
68 .mask = mode,
69
70#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
71 .pull_bit = bit, \
72 .pull_val = status,
73
74#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
75 .pu_pd_val = status,
76
77#define MUX_REG_7XX(reg, mode_offset, mode) \
78 .mux_reg = OMAP7XX_IO_CONF_##reg, \
79 .mask_offset = mode_offset, \
80 .mask = mode,
81
82#define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \
83 .pull_bit = bit, \
84 .pull_val = status,
85
86#endif /* CONFIG_OMAP_MUX_DEBUG */
87
88#define MUX_CFG(desc, mux_reg, mode_offset, mode, \
89 pull_reg, pull_bit, pull_status, \
90 pu_pd_reg, pu_pd_status, debug_status) \
91{ \
92 .name = desc, \
93 .debug = debug_status, \
94 MUX_REG(mux_reg, mode_offset, mode) \
95 PULL_REG(pull_reg, pull_bit, pull_status) \
96 PU_PD_REG(pu_pd_reg, pu_pd_status) \
97},
98
99
100/*
101 * OMAP730/850 has a slightly different config for the pin mux.
102 * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
103 * not the FUNC_MUX_CTRL_x regs from hardware.h
104 * - for pull-up/down, only has one enable bit which is is in the same register
105 * as mux config
106 */
107#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
108 pull_bit, pull_status, debug_status)\
109{ \
110 .name = desc, \
111 .debug = debug_status, \
112 MUX_REG_7XX(mux_reg, mode_offset, mode) \
113 PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
114 PU_PD_REG(NA, 0) \
115},
116
117#define MUX_CFG_24XX(desc, reg_offset, mode, \
118 pull_en, pull_mode, dbg) \
119{ \
120 .name = desc, \
121 .debug = dbg, \
122 .mux_reg = reg_offset, \
123 .mask = mode, \
124 .pull_val = pull_en, \
125 .pu_pd_val = pull_mode, \
126},
127
128/* 24xx/34xx mux bit defines */
129#define OMAP2_PULL_ENA (1 << 3)
130#define OMAP2_PULL_UP (1 << 4)
131#define OMAP2_ALTELECTRICALSEL (1 << 5)
132
133/* 34xx specific mux bit defines */
134#define OMAP3_INPUT_EN (1 << 8)
135#define OMAP3_OFF_EN (1 << 9)
136#define OMAP3_OFFOUT_EN (1 << 10)
137#define OMAP3_OFFOUT_VAL (1 << 11)
138#define OMAP3_OFF_PULL_EN (1 << 12)
139#define OMAP3_OFF_PULL_UP (1 << 13)
140#define OMAP3_WAKEUP_EN (1 << 14)
141
142/* 34xx mux mode options for each pin. See TRM for options */
143#define OMAP34XX_MUX_MODE0 0
144#define OMAP34XX_MUX_MODE1 1
145#define OMAP34XX_MUX_MODE2 2
146#define OMAP34XX_MUX_MODE3 3
147#define OMAP34XX_MUX_MODE4 4
148#define OMAP34XX_MUX_MODE5 5
149#define OMAP34XX_MUX_MODE6 6
150#define OMAP34XX_MUX_MODE7 7
151
152/* 34xx active pin states */
153#define OMAP34XX_PIN_OUTPUT 0
154#define OMAP34XX_PIN_INPUT OMAP3_INPUT_EN
155#define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
156 | OMAP2_PULL_UP)
157#define OMAP34XX_PIN_INPUT_PULLDOWN (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
158
159/* 34xx off mode states */
160#define OMAP34XX_PIN_OFF_NONE 0
161#define OMAP34XX_PIN_OFF_OUTPUT_HIGH (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
162 | OMAP3_OFFOUT_VAL)
163#define OMAP34XX_PIN_OFF_OUTPUT_LOW (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
164#define OMAP34XX_PIN_OFF_INPUT_PULLUP (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
165 | OMAP3_OFF_PULL_UP)
166#define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
167#define OMAP34XX_PIN_OFF_WAKEUPENABLE OMAP3_WAKEUP_EN
168
169#define MUX_CFG_34XX(desc, reg_offset, mux_value) { \
170 .name = desc, \
171 .debug = 0, \
172 .mux_reg = reg_offset, \
173 .mux_val = mux_value \
174},
175
176struct pin_config {
177 char *name;
178 const unsigned int mux_reg;
179 unsigned char debug;
180
181#if defined(CONFIG_ARCH_OMAP34XX)
182 u16 mux_val; /* Wake-up, off mode, pull, mux mode */
183#endif
184
185#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
186 const unsigned char mask_offset;
187 const unsigned char mask;
188
189 const char *pull_name;
190 const unsigned int pull_reg;
191 const unsigned char pull_val;
192 const unsigned char pull_bit;
193
194 const char *pu_pd_name;
195 const unsigned int pu_pd_reg;
196 const unsigned char pu_pd_val;
197#endif
198
199#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
200 const char *mux_reg_name;
201#endif
202
203};
204
205enum omap7xx_index {
206 /* OMAP 730 keyboard */
207 E2_7XX_KBR0,
208 J7_7XX_KBR1,
209 E1_7XX_KBR2,
210 F3_7XX_KBR3,
211 D2_7XX_KBR4,
212 C2_7XX_KBC0,
213 D3_7XX_KBC1,
214 E4_7XX_KBC2,
215 F4_7XX_KBC3,
216 E3_7XX_KBC4,
217
218 /* USB */
219 AA17_7XX_USB_DM,
220 W16_7XX_USB_PU_EN,
221 W17_7XX_USB_VBUSI,
222};
223
224enum omap1xxx_index {
225 /* UART1 (BT_UART_GATING)*/
226 UART1_TX = 0,
227 UART1_RTS,
228
229 /* UART2 (COM_UART_GATING)*/
230 UART2_TX,
231 UART2_RX,
232 UART2_CTS,
233 UART2_RTS,
234
235 /* UART3 (GIGA_UART_GATING) */
236 UART3_TX,
237 UART3_RX,
238 UART3_CTS,
239 UART3_RTS,
240 UART3_CLKREQ,
241 UART3_BCLK, /* 12MHz clock out */
242 Y15_1610_UART3_RTS,
243
244 /* PWT & PWL */
245 PWT,
246 PWL,
247
248 /* USB master generic */
249 R18_USB_VBUS,
250 R18_1510_USB_GPIO0,
251 W4_USB_PUEN,
252 W4_USB_CLKO,
253 W4_USB_HIGHZ,
254 W4_GPIO58,
255
256 /* USB1 master */
257 USB1_SUSP,
258 USB1_SEO,
259 W13_1610_USB1_SE0,
260 USB1_TXEN,
261 USB1_TXD,
262 USB1_VP,
263 USB1_VM,
264 USB1_RCV,
265 USB1_SPEED,
266 R13_1610_USB1_SPEED,
267 R13_1710_USB1_SE0,
268
269 /* USB2 master */
270 USB2_SUSP,
271 USB2_VP,
272 USB2_TXEN,
273 USB2_VM,
274 USB2_RCV,
275 USB2_SEO,
276 USB2_TXD,
277
278 /* OMAP-1510 GPIO */
279 R18_1510_GPIO0,
280 R19_1510_GPIO1,
281 M14_1510_GPIO2,
282
283 /* OMAP1610 GPIO */
284 P18_1610_GPIO3,
285 Y15_1610_GPIO17,
286
287 /* OMAP-1710 GPIO */
288 R18_1710_GPIO0,
289 V2_1710_GPIO10,
290 N21_1710_GPIO14,
291 W15_1710_GPIO40,
292
293 /* MPUIO */
294 MPUIO2,
295 N15_1610_MPUIO2,
296 MPUIO4,
297 MPUIO5,
298 T20_1610_MPUIO5,
299 W11_1610_MPUIO6,
300 V10_1610_MPUIO7,
301 W11_1610_MPUIO9,
302 V10_1610_MPUIO10,
303 W10_1610_MPUIO11,
304 E20_1610_MPUIO13,
305 U20_1610_MPUIO14,
306 E19_1610_MPUIO15,
307
308 /* MCBSP2 */
309 MCBSP2_CLKR,
310 MCBSP2_CLKX,
311 MCBSP2_DR,
312 MCBSP2_DX,
313 MCBSP2_FSR,
314 MCBSP2_FSX,
315
316 /* MCBSP3 */
317 MCBSP3_CLKX,
318
319 /* Misc ballouts */
320 BALLOUT_V8_ARMIO3,
321 N20_HDQ,
322
323 /* OMAP-1610 MMC2 */
324 W8_1610_MMC2_DAT0,
325 V8_1610_MMC2_DAT1,
326 W15_1610_MMC2_DAT2,
327 R10_1610_MMC2_DAT3,
328 Y10_1610_MMC2_CLK,
329 Y8_1610_MMC2_CMD,
330 V9_1610_MMC2_CMDDIR,
331 V5_1610_MMC2_DATDIR0,
332 W19_1610_MMC2_DATDIR1,
333 R18_1610_MMC2_CLKIN,
334
335 /* OMAP-1610 External Trace Interface */
336 M19_1610_ETM_PSTAT0,
337 L15_1610_ETM_PSTAT1,
338 L18_1610_ETM_PSTAT2,
339 L19_1610_ETM_D0,
340 J19_1610_ETM_D6,
341 J18_1610_ETM_D7,
342
343 /* OMAP16XX GPIO */
344 P20_1610_GPIO4,
345 V9_1610_GPIO7,
346 W8_1610_GPIO9,
347 N20_1610_GPIO11,
348 N19_1610_GPIO13,
349 P10_1610_GPIO22,
350 V5_1610_GPIO24,
351 AA20_1610_GPIO_41,
352 W19_1610_GPIO48,
353 M7_1610_GPIO62,
354 V14_16XX_GPIO37,
355 R9_16XX_GPIO18,
356 L14_16XX_GPIO49,
357
358 /* OMAP-1610 uWire */
359 V19_1610_UWIRE_SCLK,
360 U18_1610_UWIRE_SDI,
361 W21_1610_UWIRE_SDO,
362 N14_1610_UWIRE_CS0,
363 P15_1610_UWIRE_CS3,
364 N15_1610_UWIRE_CS1,
365
366 /* OMAP-1610 SPI */
367 U19_1610_SPIF_SCK,
368 U18_1610_SPIF_DIN,
369 P20_1610_SPIF_DIN,
370 W21_1610_SPIF_DOUT,
371 R18_1610_SPIF_DOUT,
372 N14_1610_SPIF_CS0,
373 N15_1610_SPIF_CS1,
374 T19_1610_SPIF_CS2,
375 P15_1610_SPIF_CS3,
376
377 /* OMAP-1610 Flash */
378 L3_1610_FLASH_CS2B_OE,
379 M8_1610_FLASH_CS2B_WE,
380
381 /* First MMC */
382 MMC_CMD,
383 MMC_DAT1,
384 MMC_DAT2,
385 MMC_DAT0,
386 MMC_CLK,
387 MMC_DAT3,
388
389 /* OMAP-1710 MMC CMDDIR and DATDIR0 */
390 M15_1710_MMC_CLKI,
391 P19_1710_MMC_CMDDIR,
392 P20_1710_MMC_DATDIR0,
393
394 /* OMAP-1610 USB0 alternate pin configuration */
395 W9_USB0_TXEN,
396 AA9_USB0_VP,
397 Y5_USB0_RCV,
398 R9_USB0_VM,
399 V6_USB0_TXD,
400 W5_USB0_SE0,
401 V9_USB0_SPEED,
402 V9_USB0_SUSP,
403
404 /* USB2 */
405 W9_USB2_TXEN,
406 AA9_USB2_VP,
407 Y5_USB2_RCV,
408 R9_USB2_VM,
409 V6_USB2_TXD,
410 W5_USB2_SE0,
411
412 /* 16XX UART */
413 R13_1610_UART1_TX,
414 V14_16XX_UART1_RX,
415 R14_1610_UART1_CTS,
416 AA15_1610_UART1_RTS,
417 R9_16XX_UART2_RX,
418 L14_16XX_UART3_RX,
419
420 /* I2C OMAP-1610 */
421 I2C_SCL,
422 I2C_SDA,
423
424 /* Keypad */
425 F18_1610_KBC0,
426 D20_1610_KBC1,
427 D19_1610_KBC2,
428 E18_1610_KBC3,
429 C21_1610_KBC4,
430 G18_1610_KBR0,
431 F19_1610_KBR1,
432 H14_1610_KBR2,
433 E20_1610_KBR3,
434 E19_1610_KBR4,
435 N19_1610_KBR5,
436
437 /* Power management */
438 T20_1610_LOW_PWR,
439
440 /* MCLK Settings */
441 V5_1710_MCLK_ON,
442 V5_1710_MCLK_OFF,
443 R10_1610_MCLK_ON,
444 R10_1610_MCLK_OFF,
445
446 /* CompactFlash controller */
447 P11_1610_CF_CD2,
448 R11_1610_CF_IOIS16,
449 V10_1610_CF_IREQ,
450 W10_1610_CF_RESET,
451 W11_1610_CF_CD1,
452
453 /* parallel camera */
454 J15_1610_CAM_LCLK,
455 J18_1610_CAM_D7,
456 J19_1610_CAM_D6,
457 J14_1610_CAM_D5,
458 K18_1610_CAM_D4,
459 K19_1610_CAM_D3,
460 K15_1610_CAM_D2,
461 K14_1610_CAM_D1,
462 L19_1610_CAM_D0,
463 L18_1610_CAM_VS,
464 L15_1610_CAM_HS,
465 M19_1610_CAM_RSTZ,
466 Y15_1610_CAM_OUTCLK,
467
468 /* serial camera */
469 H19_1610_CAM_EXCLK,
470 Y12_1610_CCP_CLKP,
471 W13_1610_CCP_CLKM,
472 W14_1610_CCP_DATAP,
473 Y14_1610_CCP_DATAM,
474
475};
476
477enum omap24xx_index {
478 /* 24xx I2C */
479 M19_24XX_I2C1_SCL,
480 L15_24XX_I2C1_SDA,
481 J15_24XX_I2C2_SCL,
482 H19_24XX_I2C2_SDA,
483
484 /* 24xx Menelaus interrupt */
485 W19_24XX_SYS_NIRQ,
486
487 /* 24xx clock */
488 W14_24XX_SYS_CLKOUT,
489
490 /* 24xx GPMC chipselects, wait pin monitoring */
491 E2_GPMC_NCS2,
492 L2_GPMC_NCS7,
493 L3_GPMC_WAIT0,
494 N7_GPMC_WAIT1,
495 M1_GPMC_WAIT2,
496 P1_GPMC_WAIT3,
497
498 /* 242X McBSP */
499 Y15_24XX_MCBSP2_CLKX,
500 R14_24XX_MCBSP2_FSX,
501 W15_24XX_MCBSP2_DR,
502 V15_24XX_MCBSP2_DX,
503
504 /* 24xx GPIO */
505 M21_242X_GPIO11,
506 P21_242X_GPIO12,
507 AA10_242X_GPIO13,
508 AA6_242X_GPIO14,
509 AA4_242X_GPIO15,
510 Y11_242X_GPIO16,
511 AA12_242X_GPIO17,
512 AA8_242X_GPIO58,
513 Y20_24XX_GPIO60,
514 W4__24XX_GPIO74,
515 N15_24XX_GPIO85,
516 M15_24XX_GPIO92,
517 P20_24XX_GPIO93,
518 P18_24XX_GPIO95,
519 M18_24XX_GPIO96,
520 L14_24XX_GPIO97,
521 J15_24XX_GPIO99,
522 V14_24XX_GPIO117,
523 P14_24XX_GPIO125,
524
525 /* 242x DBG GPIO */
526 V4_242X_GPIO49,
527 W2_242X_GPIO50,
528 U4_242X_GPIO51,
529 V3_242X_GPIO52,
530 V2_242X_GPIO53,
531 V6_242X_GPIO53,
532 T4_242X_GPIO54,
533 Y4_242X_GPIO54,
534 T3_242X_GPIO55,
535 U2_242X_GPIO56,
536
537 /* 24xx external DMA requests */
538 AA10_242X_DMAREQ0,
539 AA6_242X_DMAREQ1,
540 E4_242X_DMAREQ2,
541 G4_242X_DMAREQ3,
542 D3_242X_DMAREQ4,
543 E3_242X_DMAREQ5,
544
545 /* UART3 */
546 K15_24XX_UART3_TX,
547 K14_24XX_UART3_RX,
548
549 /* MMC/SDIO */
550 G19_24XX_MMC_CLKO,
551 H18_24XX_MMC_CMD,
552 F20_24XX_MMC_DAT0,
553 H14_24XX_MMC_DAT1,
554 E19_24XX_MMC_DAT2,
555 D19_24XX_MMC_DAT3,
556 F19_24XX_MMC_DAT_DIR0,
557 E20_24XX_MMC_DAT_DIR1,
558 F18_24XX_MMC_DAT_DIR2,
559 E18_24XX_MMC_DAT_DIR3,
560 G18_24XX_MMC_CMD_DIR,
561 H15_24XX_MMC_CLKI,
562
563 /* Full speed USB */
564 J20_24XX_USB0_PUEN,
565 J19_24XX_USB0_VP,
566 K20_24XX_USB0_VM,
567 J18_24XX_USB0_RCV,
568 K19_24XX_USB0_TXEN,
569 J14_24XX_USB0_SE0,
570 K18_24XX_USB0_DAT,
571
572 N14_24XX_USB1_SE0,
573 W12_24XX_USB1_SE0,
574 P15_24XX_USB1_DAT,
575 R13_24XX_USB1_DAT,
576 W20_24XX_USB1_TXEN,
577 P13_24XX_USB1_TXEN,
578 V19_24XX_USB1_RCV,
579 V12_24XX_USB1_RCV,
580
581 AA10_24XX_USB2_SE0,
582 Y11_24XX_USB2_DAT,
583 AA12_24XX_USB2_TXEN,
584 AA6_24XX_USB2_RCV,
585 AA4_24XX_USB2_TLLSE0,
586
587 /* Keypad GPIO*/
588 T19_24XX_KBR0,
589 R19_24XX_KBR1,
590 V18_24XX_KBR2,
591 M21_24XX_KBR3,
592 E5__24XX_KBR4,
593 M18_24XX_KBR5,
594 R20_24XX_KBC0,
595 M14_24XX_KBC1,
596 H19_24XX_KBC2,
597 V17_24XX_KBC3,
598 P21_24XX_KBC4,
599 L14_24XX_KBC5,
600 N19_24XX_KBC6,
601
602 /* 24xx Menelaus Keypad GPIO */
603 B3__24XX_KBR5,
604 AA4_24XX_KBC2,
605 B13_24XX_KBC6,
606
607 /* 2430 USB */
608 AD9_2430_USB0_PUEN,
609 Y11_2430_USB0_VP,
610 AD7_2430_USB0_VM,
611 AE7_2430_USB0_RCV,
612 AD4_2430_USB0_TXEN,
613 AF9_2430_USB0_SE0,
614 AE6_2430_USB0_DAT,
615 AD24_2430_USB1_SE0,
616 AB24_2430_USB1_RCV,
617 Y25_2430_USB1_TXEN,
618 AA26_2430_USB1_DAT,
619
620 /* 2430 HS-USB */
621 AD9_2430_USB0HS_DATA3,
622 Y11_2430_USB0HS_DATA4,
623 AD7_2430_USB0HS_DATA5,
624 AE7_2430_USB0HS_DATA6,
625 AD4_2430_USB0HS_DATA2,
626 AF9_2430_USB0HS_DATA0,
627 AE6_2430_USB0HS_DATA1,
628 AE8_2430_USB0HS_CLK,
629 AD8_2430_USB0HS_DIR,
630 AE5_2430_USB0HS_STP,
631 AE9_2430_USB0HS_NXT,
632 AC7_2430_USB0HS_DATA7,
633
634 /* 2430 McBSP */
635 AD6_2430_MCBSP_CLKS,
636
637 AB2_2430_MCBSP1_CLKR,
638 AD5_2430_MCBSP1_FSR,
639 AA1_2430_MCBSP1_DX,
640 AF3_2430_MCBSP1_DR,
641 AB3_2430_MCBSP1_FSX,
642 Y9_2430_MCBSP1_CLKX,
643
644 AC10_2430_MCBSP2_FSX,
645 AD16_2430_MCBSP2_CLX,
646 AE13_2430_MCBSP2_DX,
647 AD13_2430_MCBSP2_DR,
648 AC10_2430_MCBSP2_FSX_OFF,
649 AD16_2430_MCBSP2_CLX_OFF,
650 AE13_2430_MCBSP2_DX_OFF,
651 AD13_2430_MCBSP2_DR_OFF,
652
653 AC9_2430_MCBSP3_CLKX,
654 AE4_2430_MCBSP3_FSX,
655 AE2_2430_MCBSP3_DR,
656 AF4_2430_MCBSP3_DX,
657
658 N3_2430_MCBSP4_CLKX,
659 AD23_2430_MCBSP4_DR,
660 AB25_2430_MCBSP4_DX,
661 AC25_2430_MCBSP4_FSX,
662
663 AE16_2430_MCBSP5_CLKX,
664 AF12_2430_MCBSP5_FSX,
665 K7_2430_MCBSP5_DX,
666 M1_2430_MCBSP5_DR,
667
668 /* 2430 McSPI*/
669 Y18_2430_MCSPI1_CLK,
670 AD15_2430_MCSPI1_SIMO,
671 AE17_2430_MCSPI1_SOMI,
672 U1_2430_MCSPI1_CS0,
673
674 /* Touchscreen GPIO */
675 AF19_2430_GPIO_85,
676
677};
678
679enum omap34xx_index {
680 /* 34xx I2C */
681 K21_34XX_I2C1_SCL,
682 J21_34XX_I2C1_SDA,
683 AF15_34XX_I2C2_SCL,
684 AE15_34XX_I2C2_SDA,
685 AF14_34XX_I2C3_SCL,
686 AG14_34XX_I2C3_SDA,
687 AD26_34XX_I2C4_SCL,
688 AE26_34XX_I2C4_SDA,
689
690 /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
691 Y8_3430_USB1HS_PHY_CLK,
692 Y9_3430_USB1HS_PHY_STP,
693 AA14_3430_USB1HS_PHY_DIR,
694 AA11_3430_USB1HS_PHY_NXT,
695 W13_3430_USB1HS_PHY_DATA0,
696 W12_3430_USB1HS_PHY_DATA1,
697 W11_3430_USB1HS_PHY_DATA2,
698 Y11_3430_USB1HS_PHY_DATA3,
699 W9_3430_USB1HS_PHY_DATA4,
700 Y12_3430_USB1HS_PHY_DATA5,
701 W8_3430_USB1HS_PHY_DATA6,
702 Y13_3430_USB1HS_PHY_DATA7,
703
704 /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
705 AA8_3430_USB2HS_PHY_CLK,
706 AA10_3430_USB2HS_PHY_STP,
707 AA9_3430_USB2HS_PHY_DIR,
708 AB11_3430_USB2HS_PHY_NXT,
709 AB10_3430_USB2HS_PHY_DATA0,
710 AB9_3430_USB2HS_PHY_DATA1,
711 W3_3430_USB2HS_PHY_DATA2,
712 T4_3430_USB2HS_PHY_DATA3,
713 T3_3430_USB2HS_PHY_DATA4,
714 R3_3430_USB2HS_PHY_DATA5,
715 R4_3430_USB2HS_PHY_DATA6,
716 T2_3430_USB2HS_PHY_DATA7,
717
718
719 /* TLL - HSUSB: 12-pin TLL Port 1*/
720 Y8_3430_USB1HS_TLL_CLK,
721 Y9_3430_USB1HS_TLL_STP,
722 AA14_3430_USB1HS_TLL_DIR,
723 AA11_3430_USB1HS_TLL_NXT,
724 W13_3430_USB1HS_TLL_DATA0,
725 W12_3430_USB1HS_TLL_DATA1,
726 W11_3430_USB1HS_TLL_DATA2,
727 Y11_3430_USB1HS_TLL_DATA3,
728 W9_3430_USB1HS_TLL_DATA4,
729 Y12_3430_USB1HS_TLL_DATA5,
730 W8_3430_USB1HS_TLL_DATA6,
731 Y13_3430_USB1HS_TLL_DATA7,
732
733 /* TLL - HSUSB: 12-pin TLL Port 2*/
734 AA8_3430_USB2HS_TLL_CLK,
735 AA10_3430_USB2HS_TLL_STP,
736 AA9_3430_USB2HS_TLL_DIR,
737 AB11_3430_USB2HS_TLL_NXT,
738 AB10_3430_USB2HS_TLL_DATA0,
739 AB9_3430_USB2HS_TLL_DATA1,
740 W3_3430_USB2HS_TLL_DATA2,
741 T4_3430_USB2HS_TLL_DATA3,
742 T3_3430_USB2HS_TLL_DATA4,
743 R3_3430_USB2HS_TLL_DATA5,
744 R4_3430_USB2HS_TLL_DATA6,
745 T2_3430_USB2HS_TLL_DATA7,
746
747 /* TLL - HSUSB: 12-pin TLL Port 3*/
748 AA6_3430_USB3HS_TLL_CLK,
749 AB3_3430_USB3HS_TLL_STP,
750 AA3_3430_USB3HS_TLL_DIR,
751 Y3_3430_USB3HS_TLL_NXT,
752 AA5_3430_USB3HS_TLL_DATA0,
753 Y4_3430_USB3HS_TLL_DATA1,
754 Y5_3430_USB3HS_TLL_DATA2,
755 W5_3430_USB3HS_TLL_DATA3,
756 AB12_3430_USB3HS_TLL_DATA4,
757 AB13_3430_USB3HS_TLL_DATA5,
758 AA13_3430_USB3HS_TLL_DATA6,
759 AA12_3430_USB3HS_TLL_DATA7,
760
761 /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
762 AF10_3430_USB1FS_PHY_MM1_RXDP,
763 AG9_3430_USB1FS_PHY_MM1_RXDM,
764 W13_3430_USB1FS_PHY_MM1_RXRCV,
765 W12_3430_USB1FS_PHY_MM1_TXSE0,
766 W11_3430_USB1FS_PHY_MM1_TXDAT,
767 Y11_3430_USB1FS_PHY_MM1_TXEN_N,
768
769 /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
770 AF7_3430_USB2FS_PHY_MM2_RXDP,
771 AH7_3430_USB2FS_PHY_MM2_RXDM,
772 AB10_3430_USB2FS_PHY_MM2_RXRCV,
773 AB9_3430_USB2FS_PHY_MM2_TXSE0,
774 W3_3430_USB2FS_PHY_MM2_TXDAT,
775 T4_3430_USB2FS_PHY_MM2_TXEN_N,
776
777 /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
778 AH3_3430_USB3FS_PHY_MM3_RXDP,
779 AE3_3430_USB3FS_PHY_MM3_RXDM,
780 AD1_3430_USB3FS_PHY_MM3_RXRCV,
781 AE1_3430_USB3FS_PHY_MM3_TXSE0,
782 AD2_3430_USB3FS_PHY_MM3_TXDAT,
783 AC1_3430_USB3FS_PHY_MM3_TXEN_N,
784
785 /* 34xx GPIO
786 * - normally these are bidirectional, no internal pullup/pulldown
787 * - "_UP" suffix (GPIO3_UP) if internal pullup is configured
788 * - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown
789 * - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx)
790 */
791 AF26_34XX_GPIO0,
792 AF22_34XX_GPIO9,
793 AG9_34XX_GPIO23,
794 AH8_34XX_GPIO29,
795 U8_34XX_GPIO54_OUT,
796 U8_34XX_GPIO54_DOWN,
797 L8_34XX_GPIO63,
798 G25_34XX_GPIO86_OUT,
799 AG4_34XX_GPIO134_OUT,
800 AF4_34XX_GPIO135_OUT,
801 AE4_34XX_GPIO136_OUT,
802 AF6_34XX_GPIO140_UP,
803 AE6_34XX_GPIO141,
804 AF5_34XX_GPIO142,
805 AE5_34XX_GPIO143,
806 H19_34XX_GPIO164_OUT,
807 J25_34XX_GPIO170,
808
809 /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
810 H16_34XX_SDRC_CKE0,
811 H17_34XX_SDRC_CKE1,
812
813 /* MMC1 */
814 N28_3430_MMC1_CLK,
815 M27_3430_MMC1_CMD,
816 N27_3430_MMC1_DAT0,
817 N26_3430_MMC1_DAT1,
818 N25_3430_MMC1_DAT2,
819 P28_3430_MMC1_DAT3,
820 P27_3430_MMC1_DAT4,
821 P26_3430_MMC1_DAT5,
822 R27_3430_MMC1_DAT6,
823 R25_3430_MMC1_DAT7,
824
825 /* MMC2 */
826 AE2_3430_MMC2_CLK,
827 AG5_3430_MMC2_CMD,
828 AH5_3430_MMC2_DAT0,
829 AH4_3430_MMC2_DAT1,
830 AG4_3430_MMC2_DAT2,
831 AF4_3430_MMC2_DAT3,
832
833 /* MMC3 */
834 AF10_3430_MMC3_CLK,
835 AC3_3430_MMC3_CMD,
836 AE11_3430_MMC3_DAT0,
837 AH9_3430_MMC3_DAT1,
838 AF13_3430_MMC3_DAT2,
839 AF13_3430_MMC3_DAT3,
840
841 /* SYS_NIRQ T2 INT1 */
842 AF26_34XX_SYS_NIRQ,
843};
844
845struct omap_mux_cfg {
846 struct pin_config *pins;
847 unsigned long size;
848 int (*cfg_reg)(const struct pin_config *cfg);
849};
850
851#ifdef CONFIG_OMAP_MUX
852/* setup pin muxing in Linux */
853extern int omap1_mux_init(void);
854extern int omap2_mux_init(void);
855extern int omap_mux_register(struct omap_mux_cfg *);
856extern int omap_cfg_reg(unsigned long reg_cfg);
857#else
858/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
859static inline int omap1_mux_init(void) { return 0; }
860static inline int omap2_mux_init(void) { return 0; }
861static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
862#endif
863
864#endif
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
new file mode 100644
index 000000000000..631a7bed1eef
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -0,0 +1,24 @@
1/*
2 * arch/arm/plat-omap/include/mach/nand.h
3 *
4 * Copyright (C) 2006 Micron Technology Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/mtd/partitions.h>
12
13struct omap_nand_platform_data {
14 unsigned int options;
15 int cs;
16 int gpio_irq;
17 struct mtd_partition *parts;
18 int nr_parts;
19 int (*nand_setup)(void __iomem *);
20 int (*dev_ready)(struct omap_nand_platform_data *);
21 int dma_channel;
22 void __iomem *gpmc_cs_baseaddr;
23 void __iomem *gpmc_baseaddr;
24};
diff --git a/arch/arm/plat-omap/include/plat/omap-alsa.h b/arch/arm/plat-omap/include/plat/omap-alsa.h
new file mode 100644
index 000000000000..b53055b390d0
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap-alsa.h
@@ -0,0 +1,123 @@
1/*
2 * arch/arm/plat-omap/include/mach/omap-alsa.h
3 *
4 * Alsa Driver for AIC23 and TSC2101 codecs on OMAP platform boards.
5 *
6 * Copyright (C) 2006 Mika Laitio <lamikr@cc.jyu.fi>
7 *
8 * Copyright (C) 2005 Instituto Nokia de Tecnologia - INdT - Manaus Brazil
9 * Written by Daniel Petrini, David Cohen, Anderson Briglia
10 * {daniel.petrini, david.cohen, anderson.briglia}@indt.org.br
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 *
32 * History
33 * -------
34 *
35 * 2005/07/25 INdT-10LE Kernel Team - Alsa driver for omap osk,
36 * original version based in sa1100 driver
37 * and omap oss driver.
38 */
39
40#ifndef __OMAP_ALSA_H
41#define __OMAP_ALSA_H
42
43#include <plat/dma.h>
44#include <sound/core.h>
45#include <sound/pcm.h>
46#include <plat/mcbsp.h>
47#include <linux/platform_device.h>
48
49#define DMA_BUF_SIZE (1024 * 8)
50
51/*
52 * Buffer management for alsa and dma
53 */
54struct audio_stream {
55 char *id; /* identification string */
56 int stream_id; /* numeric identification */
57 int dma_dev; /* dma number of that device */
58 int *lch; /* Chain of channels this stream is linked to */
59 char started; /* to store if the chain was started or not */
60 int dma_q_head; /* DMA Channel Q Head */
61 int dma_q_tail; /* DMA Channel Q Tail */
62 char dma_q_count; /* DMA Channel Q Count */
63 int active:1; /* we are using this stream for transfer now */
64 int period; /* current transfer period */
65 int periods; /* current count of periods registerd in the DMA engine */
66 spinlock_t dma_lock; /* for locking in DMA operations */
67 struct snd_pcm_substream *stream; /* the pcm stream */
68 unsigned linked:1; /* dma channels linked */
69 int offset; /* store start position of the last period in the alsa buffer */
70 int (*hw_start)(void); /* interface to start HW interface, e.g. McBSP */
71 int (*hw_stop)(void); /* interface to stop HW interface, e.g. McBSP */
72};
73
74/*
75 * Alsa card structure for aic23
76 */
77struct snd_card_omap_codec {
78 struct snd_card *card;
79 struct snd_pcm *pcm;
80 long samplerate;
81 struct audio_stream s[2]; /* playback & capture */
82};
83
84/* Codec specific information and function pointers.
85 * Codec (omap-alsa-aic23.c and omap-alsa-tsc2101.c)
86 * are responsible for defining the function pointers.
87 */
88struct omap_alsa_codec_config {
89 char *name;
90 struct omap_mcbsp_reg_cfg *mcbsp_regs_alsa;
91 struct snd_pcm_hw_constraint_list *hw_constraints_rates;
92 struct snd_pcm_hardware *snd_omap_alsa_playback;
93 struct snd_pcm_hardware *snd_omap_alsa_capture;
94 void (*codec_configure_dev)(void);
95 void (*codec_set_samplerate)(long);
96 void (*codec_clock_setup)(void);
97 int (*codec_clock_on)(void);
98 int (*codec_clock_off)(void);
99 int (*get_default_samplerate)(void);
100};
101
102/*********** Mixer function prototypes *************************/
103int snd_omap_mixer(struct snd_card_omap_codec *);
104void snd_omap_init_mixer(void);
105
106#ifdef CONFIG_PM
107void snd_omap_suspend_mixer(void);
108void snd_omap_resume_mixer(void);
109#endif
110
111int snd_omap_alsa_post_probe(struct platform_device *pdev, struct omap_alsa_codec_config *config);
112int snd_omap_alsa_remove(struct platform_device *pdev);
113#ifdef CONFIG_PM
114int snd_omap_alsa_suspend(struct platform_device *pdev, pm_message_t state);
115int snd_omap_alsa_resume(struct platform_device *pdev);
116#else
117#define snd_omap_alsa_suspend NULL
118#define snd_omap_alsa_resume NULL
119#endif
120
121void callback_omap_alsa_sound_dma(void *);
122
123#endif
diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h
new file mode 100644
index 000000000000..3ee41d711492
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap-pm.h
@@ -0,0 +1,301 @@
1/*
2 * omap-pm.h - OMAP power management interface
3 *
4 * Copyright (C) 2008-2009 Texas Instruments, Inc.
5 * Copyright (C) 2008-2009 Nokia Corporation
6 * Paul Walmsley
7 *
8 * Interface developed by (in alphabetical order): Karthik Dasu, Jouni
9 * Högander, Tony Lindgren, Rajendra Nayak, Sakari Poussa,
10 * Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul Walmsley,
11 * Richard Woodruff
12 */
13
14#ifndef ASM_ARM_ARCH_OMAP_OMAP_PM_H
15#define ASM_ARM_ARCH_OMAP_OMAP_PM_H
16
17#include <linux/device.h>
18#include <linux/cpufreq.h>
19
20#include "powerdomain.h"
21
22/**
23 * struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU
24 * @rate: target clock rate
25 * @opp_id: OPP ID
26 * @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP
27 *
28 * Operating performance point data. Can vary by OMAP chip and board.
29 */
30struct omap_opp {
31 unsigned long rate;
32 u8 opp_id;
33 u16 min_vdd;
34};
35
36extern struct omap_opp *mpu_opps;
37extern struct omap_opp *dsp_opps;
38extern struct omap_opp *l3_opps;
39
40/*
41 * agent_id values for use with omap_pm_set_min_bus_tput():
42 *
43 * OCP_INITIATOR_AGENT is only valid for devices that can act as
44 * initiators -- it represents the device's L3 interconnect
45 * connection. OCP_TARGET_AGENT represents the device's L4
46 * interconnect connection.
47 */
48#define OCP_TARGET_AGENT 1
49#define OCP_INITIATOR_AGENT 2
50
51/**
52 * omap_pm_if_early_init - OMAP PM init code called before clock fw init
53 * @mpu_opp_table: array ptr to struct omap_opp for MPU
54 * @dsp_opp_table: array ptr to struct omap_opp for DSP
55 * @l3_opp_table : array ptr to struct omap_opp for CORE
56 *
57 * Initialize anything that must be configured before the clock
58 * framework starts. The "_if_" is to avoid name collisions with the
59 * PM idle-loop code.
60 */
61int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
62 struct omap_opp *dsp_opp_table,
63 struct omap_opp *l3_opp_table);
64
65/**
66 * omap_pm_if_init - OMAP PM init code called after clock fw init
67 *
68 * The main initialization code. OPP tables are passed in here. The
69 * "_if_" is to avoid name collisions with the PM idle-loop code.
70 */
71int __init omap_pm_if_init(void);
72
73/**
74 * omap_pm_if_exit - OMAP PM exit code
75 *
76 * Exit code; currently unused. The "_if_" is to avoid name
77 * collisions with the PM idle-loop code.
78 */
79void omap_pm_if_exit(void);
80
81/*
82 * Device-driver-originated constraints (via board-*.c files, platform_data)
83 */
84
85
86/**
87 * omap_pm_set_max_mpu_wakeup_lat - set the maximum MPU wakeup latency
88 * @dev: struct device * requesting the constraint
89 * @t: maximum MPU wakeup latency in microseconds
90 *
91 * Request that the maximum interrupt latency for the MPU to be no
92 * greater than 't' microseconds. "Interrupt latency" in this case is
93 * defined as the elapsed time from the occurrence of a hardware or
94 * timer interrupt to the time when the device driver's interrupt
95 * service routine has been entered by the MPU.
96 *
97 * It is intended that underlying PM code will use this information to
98 * determine what power state to put the MPU powerdomain into, and
99 * possibly the CORE powerdomain as well, since interrupt handling
100 * code currently runs from SDRAM. Advanced PM or board*.c code may
101 * also configure interrupt controller priorities, OCP bus priorities,
102 * CPU speed(s), etc.
103 *
104 * This function will not affect device wakeup latency, e.g., time
105 * elapsed from when a device driver enables a hardware device with
106 * clk_enable(), to when the device is ready for register access or
107 * other use. To control this device wakeup latency, use
108 * set_max_dev_wakeup_lat()
109 *
110 * Multiple calls to set_max_mpu_wakeup_lat() will replace the
111 * previous t value. To remove the latency target for the MPU, call
112 * with t = -1.
113 *
114 * No return value.
115 */
116void omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
117
118
119/**
120 * omap_pm_set_min_bus_tput - set minimum bus throughput needed by device
121 * @dev: struct device * requesting the constraint
122 * @tbus_id: interconnect to operate on (OCP_{INITIATOR,TARGET}_AGENT)
123 * @r: minimum throughput (in KiB/s)
124 *
125 * Request that the minimum data throughput on the OCP interconnect
126 * attached to device 'dev' interconnect agent 'tbus_id' be no less
127 * than 'r' KiB/s.
128 *
129 * It is expected that the OMAP PM or bus code will use this
130 * information to set the interconnect clock to run at the lowest
131 * possible speed that satisfies all current system users. The PM or
132 * bus code will adjust the estimate based on its model of the bus, so
133 * device driver authors should attempt to specify an accurate
134 * quantity for their device use case, and let the PM or bus code
135 * overestimate the numbers as necessary to handle request/response
136 * latency, other competing users on the system, etc. On OMAP2/3, if
137 * a driver requests a minimum L4 interconnect speed constraint, the
138 * code will also need to add an minimum L3 interconnect speed
139 * constraint,
140 *
141 * Multiple calls to set_min_bus_tput() will replace the previous rate
142 * value for this device. To remove the interconnect throughput
143 * restriction for this device, call with r = 0.
144 *
145 * No return value.
146 */
147void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
148
149
150/**
151 * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
152 * @dev: struct device *
153 * @t: maximum device wakeup latency in microseconds
154 *
155 * Request that the maximum amount of time necessary for a device to
156 * become accessible after its clocks are enabled should be no greater
157 * than 't' microseconds. Specifically, this represents the time from
158 * when a device driver enables device clocks with clk_enable(), to
159 * when the register reads and writes on the device will succeed.
160 * This function should be called before clk_disable() is called,
161 * since the power state transition decision may be made during
162 * clk_disable().
163 *
164 * It is intended that underlying PM code will use this information to
165 * determine what power state to put the powerdomain enclosing this
166 * device into.
167 *
168 * Multiple calls to set_max_dev_wakeup_lat() will replace the
169 * previous wakeup latency values for this device. To remove the wakeup
170 * latency restriction for this device, call with t = -1.
171 *
172 * No return value.
173 */
174void omap_pm_set_max_dev_wakeup_lat(struct device *dev, long t);
175
176
177/**
178 * omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency
179 * @dev: struct device *
180 * @t: maximum DMA transfer start latency in microseconds
181 *
182 * Request that the maximum system DMA transfer start latency for this
183 * device 'dev' should be no greater than 't' microseconds. "DMA
184 * transfer start latency" here is defined as the elapsed time from
185 * when a device (e.g., McBSP) requests that a system DMA transfer
186 * start or continue, to the time at which data starts to flow into
187 * that device from the system DMA controller.
188 *
189 * It is intended that underlying PM code will use this information to
190 * determine what power state to put the CORE powerdomain into.
191 *
192 * Since system DMA transfers may not involve the MPU, this function
193 * will not affect MPU wakeup latency. Use set_max_cpu_lat() to do
194 * so. Similarly, this function will not affect device wakeup latency
195 * -- use set_max_dev_wakeup_lat() to affect that.
196 *
197 * Multiple calls to set_max_sdma_lat() will replace the previous t
198 * value for this device. To remove the maximum DMA latency for this
199 * device, call with t = -1.
200 *
201 * No return value.
202 */
203void omap_pm_set_max_sdma_lat(struct device *dev, long t);
204
205
206/*
207 * DSP Bridge-specific constraints
208 */
209
210/**
211 * omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table
212 *
213 * Intended for use by DSPBridge. Returns an array of OPP->DSP clock
214 * frequency entries. The final item in the array should have .rate =
215 * .opp_id = 0.
216 */
217const struct omap_opp *omap_pm_dsp_get_opp_table(void);
218
219/**
220 * omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge
221 * @opp_id: target DSP OPP ID
222 *
223 * Set a minimum OPP ID for the DSP. This is intended to be called
224 * only from the DSP Bridge MPU-side driver. Unfortunately, the only
225 * information that code receives from the DSP/BIOS load estimator is the
226 * target OPP ID; hence, this interface. No return value.
227 */
228void omap_pm_dsp_set_min_opp(u8 opp_id);
229
230/**
231 * omap_pm_dsp_get_opp - report the current DSP OPP ID
232 *
233 * Report the current OPP for the DSP. Since on OMAP3, the DSP and
234 * MPU share a single voltage domain, the OPP ID returned back may
235 * represent a higher DSP speed than the OPP requested via
236 * omap_pm_dsp_set_min_opp().
237 *
238 * Returns the current VDD1 OPP ID, or 0 upon error.
239 */
240u8 omap_pm_dsp_get_opp(void);
241
242
243/*
244 * CPUFreq-originated constraint
245 *
246 * In the future, this should be handled by custom OPP clocktype
247 * functions.
248 */
249
250/**
251 * omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr
252 *
253 * Provide a frequency table usable by CPUFreq for the current chip/board.
254 * Returns a pointer to a struct cpufreq_frequency_table array or NULL
255 * upon error.
256 */
257struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void);
258
259/**
260 * omap_pm_cpu_set_freq - set the current minimum MPU frequency
261 * @f: MPU frequency in Hz
262 *
263 * Set the current minimum CPU frequency. The actual CPU frequency
264 * used could end up higher if the DSP requested a higher OPP.
265 * Intended to be called by plat-omap/cpu_omap.c:omap_target(). No
266 * return value.
267 */
268void omap_pm_cpu_set_freq(unsigned long f);
269
270/**
271 * omap_pm_cpu_get_freq - report the current CPU frequency
272 *
273 * Returns the current MPU frequency, or 0 upon error.
274 */
275unsigned long omap_pm_cpu_get_freq(void);
276
277
278/*
279 * Device context loss tracking
280 */
281
282/**
283 * omap_pm_get_dev_context_loss_count - return count of times dev has lost ctx
284 * @dev: struct device *
285 *
286 * This function returns the number of times that the device @dev has
287 * lost its internal context. This generally occurs on a powerdomain
288 * transition to OFF. Drivers use this as an optimization to avoid restoring
289 * context if the device hasn't lost it. To use, drivers should initially
290 * call this in their context save functions and store the result. Early in
291 * the driver's context restore function, the driver should call this function
292 * again, and compare the result to the stored counter. If they differ, the
293 * driver must restore device context. If the number of context losses
294 * exceeds the maximum positive integer, the function will wrap to 0 and
295 * continue counting. Returns the number of context losses for this device,
296 * or -EINVAL upon error.
297 */
298int omap_pm_get_dev_context_loss_count(struct device *dev);
299
300
301#endif
diff --git a/arch/arm/plat-omap/include/plat/omap1510.h b/arch/arm/plat-omap/include/plat/omap1510.h
new file mode 100644
index 000000000000..d24004668138
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap1510.h
@@ -0,0 +1,50 @@
1/* arch/arm/plat-omap/include/mach/omap1510.h
2 *
3 * Hardware definitions for TI OMAP1510 processor.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __ASM_ARCH_OMAP15XX_H
29#define __ASM_ARCH_OMAP15XX_H
30
31/*
32 * ----------------------------------------------------------------------------
33 * Base addresses
34 * ----------------------------------------------------------------------------
35 */
36
37/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
38
39#define OMAP1510_DSP_BASE 0xE0000000
40#define OMAP1510_DSP_SIZE 0x28000
41#define OMAP1510_DSP_START 0xE0000000
42
43#define OMAP1510_DSPREG_BASE 0xE1000000
44#define OMAP1510_DSPREG_SIZE SZ_128K
45#define OMAP1510_DSPREG_START 0xE1000000
46
47#define OMAP1510_DSP_MMU_BASE (0xfffed200)
48
49#endif /* __ASM_ARCH_OMAP15XX_H */
50
diff --git a/arch/arm/plat-omap/include/plat/omap16xx.h b/arch/arm/plat-omap/include/plat/omap16xx.h
new file mode 100644
index 000000000000..0e69b504c25f
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap16xx.h
@@ -0,0 +1,202 @@
1/* arch/arm/plat-omap/include/mach/omap16xx.h
2 *
3 * Hardware definitions for TI OMAP1610/5912/1710 processors.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __ASM_ARCH_OMAP16XX_H
29#define __ASM_ARCH_OMAP16XX_H
30
31/*
32 * ----------------------------------------------------------------------------
33 * Base addresses
34 * ----------------------------------------------------------------------------
35 */
36
37/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
38
39#define OMAP16XX_DSP_BASE 0xE0000000
40#define OMAP16XX_DSP_SIZE 0x28000
41#define OMAP16XX_DSP_START 0xE0000000
42
43#define OMAP16XX_DSPREG_BASE 0xE1000000
44#define OMAP16XX_DSPREG_SIZE SZ_128K
45#define OMAP16XX_DSPREG_START 0xE1000000
46
47#define OMAP16XX_SEC_BASE 0xFFFE4000
48#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
49#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
50#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
51
52/*
53 * ---------------------------------------------------------------------------
54 * Interrupts
55 * ---------------------------------------------------------------------------
56 */
57#define OMAP_IH2_0_BASE (0xfffe0000)
58#define OMAP_IH2_1_BASE (0xfffe0100)
59#define OMAP_IH2_2_BASE (0xfffe0200)
60#define OMAP_IH2_3_BASE (0xfffe0300)
61
62#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
63#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
64#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
65#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
66#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
67#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
68#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
69
70#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
71#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
72#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
73#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
74#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
75#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
76#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
77
78#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
79#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
80#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
81#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
82#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
83#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
84#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
85
86#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
87#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
88#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
89#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
90#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
91#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
92#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
93
94/*
95 * ----------------------------------------------------------------------------
96 * Clocks
97 * ----------------------------------------------------------------------------
98 */
99#define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
100
101/*
102 * ----------------------------------------------------------------------------
103 * Pin configuration registers
104 * ----------------------------------------------------------------------------
105 */
106#define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8)
107#define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9)
108#define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10)
109#define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11)
110#define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13)
111
112/*
113 * ----------------------------------------------------------------------------
114 * System control registers
115 * ----------------------------------------------------------------------------
116 */
117#define OMAP1610_RESET_CONTROL 0xfffe1140
118
119/*
120 * ---------------------------------------------------------------------------
121 * TIPB bus interface
122 * ---------------------------------------------------------------------------
123 */
124#define TIPB_SWITCH_BASE (0xfffbc800)
125#define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
126
127/* UART3 Registers Maping through MPU bus */
128#define UART3_RHR (OMAP_UART3_BASE + 0)
129#define UART3_THR (OMAP_UART3_BASE + 0)
130#define UART3_DLL (OMAP_UART3_BASE + 0)
131#define UART3_IER (OMAP_UART3_BASE + 4)
132#define UART3_DLH (OMAP_UART3_BASE + 4)
133#define UART3_IIR (OMAP_UART3_BASE + 8)
134#define UART3_FCR (OMAP_UART3_BASE + 8)
135#define UART3_EFR (OMAP_UART3_BASE + 8)
136#define UART3_LCR (OMAP_UART3_BASE + 0x0C)
137#define UART3_MCR (OMAP_UART3_BASE + 0x10)
138#define UART3_XON1_ADDR1 (OMAP_UART3_BASE + 0x10)
139#define UART3_XON2_ADDR2 (OMAP_UART3_BASE + 0x14)
140#define UART3_LSR (OMAP_UART3_BASE + 0x14)
141#define UART3_TCR (OMAP_UART3_BASE + 0x18)
142#define UART3_MSR (OMAP_UART3_BASE + 0x18)
143#define UART3_XOFF1 (OMAP_UART3_BASE + 0x18)
144#define UART3_XOFF2 (OMAP_UART3_BASE + 0x1C)
145#define UART3_SPR (OMAP_UART3_BASE + 0x1C)
146#define UART3_TLR (OMAP_UART3_BASE + 0x1C)
147#define UART3_MDR1 (OMAP_UART3_BASE + 0x20)
148#define UART3_MDR2 (OMAP_UART3_BASE + 0x24)
149#define UART3_SFLSR (OMAP_UART3_BASE + 0x28)
150#define UART3_TXFLL (OMAP_UART3_BASE + 0x28)
151#define UART3_RESUME (OMAP_UART3_BASE + 0x2C)
152#define UART3_TXFLH (OMAP_UART3_BASE + 0x2C)
153#define UART3_SFREGL (OMAP_UART3_BASE + 0x30)
154#define UART3_RXFLL (OMAP_UART3_BASE + 0x30)
155#define UART3_SFREGH (OMAP_UART3_BASE + 0x34)
156#define UART3_RXFLH (OMAP_UART3_BASE + 0x34)
157#define UART3_BLR (OMAP_UART3_BASE + 0x38)
158#define UART3_ACREG (OMAP_UART3_BASE + 0x3C)
159#define UART3_DIV16 (OMAP_UART3_BASE + 0x3C)
160#define UART3_SCR (OMAP_UART3_BASE + 0x40)
161#define UART3_SSR (OMAP_UART3_BASE + 0x44)
162#define UART3_EBLR (OMAP_UART3_BASE + 0x48)
163#define UART3_OSC_12M_SEL (OMAP_UART3_BASE + 0x4C)
164#define UART3_MVR (OMAP_UART3_BASE + 0x50)
165
166/*
167 * ---------------------------------------------------------------------------
168 * Watchdog timer
169 * ---------------------------------------------------------------------------
170 */
171
172/* 32-bit Watchdog timer in OMAP 16XX */
173#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000)
174#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00)
175#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
176#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
177#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24)
178#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28)
179#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c)
180#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30)
181#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34)
182#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48)
183
184#define WCLR_PRE_SHIFT 5
185#define WCLR_PTV_SHIFT 2
186
187#define WWPS_W_PEND_WSPR (1 << 4)
188#define WWPS_W_PEND_WTGR (1 << 3)
189#define WWPS_W_PEND_WLDR (1 << 2)
190#define WWPS_W_PEND_WCRR (1 << 1)
191#define WWPS_W_PEND_WCLR (1 << 0)
192
193#define WSPR_ENABLE_0 (0x0000bbbb)
194#define WSPR_ENABLE_1 (0x00004444)
195#define WSPR_DISABLE_0 (0x0000aaaa)
196#define WSPR_DISABLE_1 (0x00005555)
197
198#define OMAP16XX_DSP_MMU_BASE (0xfffed200)
199#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
200
201#endif /* __ASM_ARCH_OMAP16XX_H */
202
diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h
new file mode 100644
index 000000000000..696edfc145a6
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap24xx.h
@@ -0,0 +1,89 @@
1/*
2 * arch/arm/plat-omap/include/mach/omap24xx.h
3 *
4 * This file contains the processor specific definitions
5 * of the TI OMAP24XX.
6 *
7 * Copyright (C) 2007 Texas Instruments.
8 * Copyright (C) 2007 Nokia Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#ifndef __ASM_ARCH_OMAP24XX_H
27#define __ASM_ARCH_OMAP24XX_H
28
29/*
30 * Please place only base defines here and put the rest in device
31 * specific headers. Note also that some of these defines are needed
32 * for omap1 to compile without adding ifdefs.
33 */
34
35#define L4_24XX_BASE 0x48000000
36#define L4_WK_243X_BASE 0x49000000
37#define L3_24XX_BASE 0x68000000
38
39/* interrupt controller */
40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
41#define OMAP24XX_IVA_INTC_BASE 0x40000000
42
43#define OMAP2420_CTRL_BASE L4_24XX_BASE
44#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
45#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
46#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
47#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
48#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
49#define OMAP2420_SMS_BASE 0x68008000
50#define OMAP2420_GPMC_BASE 0x6800a000
51
52#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
53#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
54#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000)
55#define OMAP2430_PRM_BASE OMAP2430_CM_BASE
56
57#define OMAP243X_SMS_BASE 0x6C000000
58#define OMAP243X_SDRC_BASE 0x6D000000
59#define OMAP243X_GPMC_BASE 0x6E000000
60#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000)
61#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE
62#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000)
63
64/* DSP SS */
65#define OMAP2420_DSP_BASE 0x58000000
66#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0)
67#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000)
68#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000)
69
70#define OMAP243X_DSP_BASE 0x5C000000
71#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0)
72#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000)
73
74/* Mailbox */
75#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000)
76
77/* Camera */
78#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000)
79
80/* Security */
81#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000)
82#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000)
83#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000)
84#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
85#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000)
86#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000)
87
88#endif /* __ASM_ARCH_OMAP24XX_H */
89
diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h
new file mode 100644
index 000000000000..f8d186a73712
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap34xx.h
@@ -0,0 +1,87 @@
1/*
2 * arch/arm/plat-omap/include/mach/omap34xx.h
3 *
4 * This file contains the processor specific definitions of the TI OMAP34XX.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 * Copyright (C) 2007 Nokia Corporation.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#ifndef __ASM_ARCH_OMAP34XX_H
25#define __ASM_ARCH_OMAP34XX_H
26
27/*
28 * Please place only base defines here and put the rest in device
29 * specific headers.
30 */
31
32#define L4_34XX_BASE 0x48000000
33#define L4_WK_34XX_BASE 0x48300000
34#define L4_PER_34XX_BASE 0x49000000
35#define L4_EMU_34XX_BASE 0x54000000
36#define L3_34XX_BASE 0x68000000
37
38#define OMAP3430_32KSYNCT_BASE 0x48320000
39#define OMAP3430_CM_BASE 0x48004800
40#define OMAP3430_PRM_BASE 0x48306800
41#define OMAP343X_SMS_BASE 0x6C000000
42#define OMAP343X_SDRC_BASE 0x6D000000
43#define OMAP34XX_GPMC_BASE 0x6E000000
44#define OMAP343X_SCM_BASE 0x48002000
45#define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE
46
47#define OMAP34XX_IC_BASE 0x48200000
48
49#define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000)
50#define OMAP3430_ISP_CBUFF_BASE (OMAP3430_ISP_BASE + 0x0100)
51#define OMAP3430_ISP_CCP2_BASE (OMAP3430_ISP_BASE + 0x0400)
52#define OMAP3430_ISP_CCDC_BASE (OMAP3430_ISP_BASE + 0x0600)
53#define OMAP3430_ISP_HIST_BASE (OMAP3430_ISP_BASE + 0x0A00)
54#define OMAP3430_ISP_H3A_BASE (OMAP3430_ISP_BASE + 0x0C00)
55#define OMAP3430_ISP_PREV_BASE (OMAP3430_ISP_BASE + 0x0E00)
56#define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000)
57#define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200)
58#define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400)
59#define OMAP3430_ISP_CSI2A_BASE (OMAP3430_ISP_BASE + 0x1800)
60#define OMAP3430_ISP_CSI2PHY_BASE (OMAP3430_ISP_BASE + 0x1970)
61
62#define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F)
63#define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077)
64#define OMAP3430_ISP_CCP2_END (OMAP3430_ISP_CCP2_BASE + 0x1EF)
65#define OMAP3430_ISP_CCDC_END (OMAP3430_ISP_CCDC_BASE + 0x0A7)
66#define OMAP3430_ISP_HIST_END (OMAP3430_ISP_HIST_BASE + 0x047)
67#define OMAP3430_ISP_H3A_END (OMAP3430_ISP_H3A_BASE + 0x05F)
68#define OMAP3430_ISP_PREV_END (OMAP3430_ISP_PREV_BASE + 0x09F)
69#define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB)
70#define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB)
71#define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F)
72#define OMAP3430_ISP_CSI2A_END (OMAP3430_ISP_CSI2A_BASE + 0x16F)
73#define OMAP3430_ISP_CSI2PHY_END (OMAP3430_ISP_CSI2PHY_BASE + 0x007)
74
75#define OMAP34XX_IVA_INTC_BASE 0x40000000
76#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
77#define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000)
78#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
79
80#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000)
81
82#define OMAP34XX_DSP_BASE 0x58000000
83#define OMAP34XX_DSP_MEM_BASE (OMAP34XX_DSP_BASE + 0x0)
84#define OMAP34XX_DSP_IPI_BASE (OMAP34XX_DSP_BASE + 0x1000000)
85#define OMAP34XX_DSP_MMU_BASE (OMAP34XX_DSP_BASE + 0x2000000)
86#endif /* __ASM_ARCH_OMAP34XX_H */
87
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
new file mode 100644
index 000000000000..336189753671
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -0,0 +1,44 @@
1/*:
2 * Address mappings and base address for OMAP4 interconnects
3 * and peripherals.
4 *
5 * Copyright (C) 2009 Texas Instruments
6 *
7 * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef __ASM_ARCH_OMAP44XX_H
14#define __ASM_ARCH_OMAP44XX_H
15
16/*
17 * Please place only base defines here and put the rest in device
18 * specific headers.
19 */
20#define L4_44XX_BASE 0x4a000000
21#define L4_WK_44XX_BASE 0x4a300000
22#define L4_PER_44XX_BASE 0x48000000
23#define L4_EMU_44XX_BASE 0x54000000
24#define L3_44XX_BASE 0x44000000
25#define OMAP44XX_EMIF1_BASE 0x4c000000
26#define OMAP44XX_EMIF2_BASE 0x4d000000
27#define OMAP44XX_DMM_BASE 0x4e000000
28#define OMAP4430_32KSYNCT_BASE 0x4a304000
29#define OMAP4430_CM_BASE 0x4a004000
30#define OMAP4430_PRM_BASE 0x48306000
31#define OMAP44XX_GPMC_BASE 0x50000000
32#define OMAP443X_SCM_BASE 0x4a002000
33#define OMAP443X_CTRL_BASE OMAP443X_SCM_BASE
34#define OMAP44XX_IC_BASE 0x48200000
35#define OMAP44XX_IVA_INTC_BASE 0x40000000
36#define IRQ_SIR_IRQ 0x0040
37#define OMAP44XX_GIC_DIST_BASE 0x48241000
38#define OMAP44XX_GIC_CPU_BASE 0x48240100
39#define OMAP44XX_SCU_BASE 0x48240000
40#define OMAP44XX_LOCAL_TWD_BASE 0x48240600
41#define OMAP44XX_WKUPGEN_BASE 0x48281000
42
43#endif /* __ASM_ARCH_OMAP44XX_H */
44
diff --git a/arch/arm/plat-omap/include/plat/omap730.h b/arch/arm/plat-omap/include/plat/omap730.h
new file mode 100644
index 000000000000..14272bc1a6fd
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap730.h
@@ -0,0 +1,102 @@
1/* arch/arm/plat-omap/include/mach/omap730.h
2 *
3 * Hardware definitions for TI OMAP730 processor.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __ASM_ARCH_OMAP730_H
29#define __ASM_ARCH_OMAP730_H
30
31/*
32 * ----------------------------------------------------------------------------
33 * Base addresses
34 * ----------------------------------------------------------------------------
35 */
36
37/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
38
39#define OMAP730_DSP_BASE 0xE0000000
40#define OMAP730_DSP_SIZE 0x50000
41#define OMAP730_DSP_START 0xE0000000
42
43#define OMAP730_DSPREG_BASE 0xE1000000
44#define OMAP730_DSPREG_SIZE SZ_128K
45#define OMAP730_DSPREG_START 0xE1000000
46
47/*
48 * ----------------------------------------------------------------------------
49 * OMAP730 specific configuration registers
50 * ----------------------------------------------------------------------------
51 */
52#define OMAP730_CONFIG_BASE 0xfffe1000
53#define OMAP730_IO_CONF_0 0xfffe1070
54#define OMAP730_IO_CONF_1 0xfffe1074
55#define OMAP730_IO_CONF_2 0xfffe1078
56#define OMAP730_IO_CONF_3 0xfffe107c
57#define OMAP730_IO_CONF_4 0xfffe1080
58#define OMAP730_IO_CONF_5 0xfffe1084
59#define OMAP730_IO_CONF_6 0xfffe1088
60#define OMAP730_IO_CONF_7 0xfffe108c
61#define OMAP730_IO_CONF_8 0xfffe1090
62#define OMAP730_IO_CONF_9 0xfffe1094
63#define OMAP730_IO_CONF_10 0xfffe1098
64#define OMAP730_IO_CONF_11 0xfffe109c
65#define OMAP730_IO_CONF_12 0xfffe10a0
66#define OMAP730_IO_CONF_13 0xfffe10a4
67
68#define OMAP730_MODE_1 0xfffe1010
69#define OMAP730_MODE_2 0xfffe1014
70
71/* CSMI specials: in terms of base + offset */
72#define OMAP730_MODE2_OFFSET 0x14
73
74/*
75 * ----------------------------------------------------------------------------
76 * OMAP730 traffic controller configuration registers
77 * ----------------------------------------------------------------------------
78 */
79#define OMAP730_FLASH_CFG_0 0xfffecc10
80#define OMAP730_FLASH_ACFG_0 0xfffecc50
81#define OMAP730_FLASH_CFG_1 0xfffecc14
82#define OMAP730_FLASH_ACFG_1 0xfffecc54
83
84/*
85 * ----------------------------------------------------------------------------
86 * OMAP730 DSP control registers
87 * ----------------------------------------------------------------------------
88 */
89#define OMAP730_ICR_BASE 0xfffbb800
90#define OMAP730_DSP_M_CTL 0xfffbb804
91#define OMAP730_DSP_MMU_BASE 0xfffed200
92
93/*
94 * ----------------------------------------------------------------------------
95 * OMAP730 PCC_UPLD configuration registers
96 * ----------------------------------------------------------------------------
97 */
98#define OMAP730_PCC_UPLD_CTRL_BASE (0xfffe0900)
99#define OMAP730_PCC_UPLD_CTRL (OMAP730_PCC_UPLD_CTRL_BASE + 0x00)
100
101#endif /* __ASM_ARCH_OMAP730_H */
102
diff --git a/arch/arm/plat-omap/include/plat/omap7xx.h b/arch/arm/plat-omap/include/plat/omap7xx.h
new file mode 100644
index 000000000000..53f52414b0e9
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap7xx.h
@@ -0,0 +1,104 @@
1/* arch/arm/plat-omap/include/mach/omap7xx.h
2 *
3 * Hardware definitions for TI OMAP7XX processor.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
7 * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#ifndef __ASM_ARCH_OMAP7XX_H
31#define __ASM_ARCH_OMAP7XX_H
32
33/*
34 * ----------------------------------------------------------------------------
35 * Base addresses
36 * ----------------------------------------------------------------------------
37 */
38
39/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
40
41#define OMAP7XX_DSP_BASE 0xE0000000
42#define OMAP7XX_DSP_SIZE 0x50000
43#define OMAP7XX_DSP_START 0xE0000000
44
45#define OMAP7XX_DSPREG_BASE 0xE1000000
46#define OMAP7XX_DSPREG_SIZE SZ_128K
47#define OMAP7XX_DSPREG_START 0xE1000000
48
49/*
50 * ----------------------------------------------------------------------------
51 * OMAP7XX specific configuration registers
52 * ----------------------------------------------------------------------------
53 */
54#define OMAP7XX_CONFIG_BASE 0xfffe1000
55#define OMAP7XX_IO_CONF_0 0xfffe1070
56#define OMAP7XX_IO_CONF_1 0xfffe1074
57#define OMAP7XX_IO_CONF_2 0xfffe1078
58#define OMAP7XX_IO_CONF_3 0xfffe107c
59#define OMAP7XX_IO_CONF_4 0xfffe1080
60#define OMAP7XX_IO_CONF_5 0xfffe1084
61#define OMAP7XX_IO_CONF_6 0xfffe1088
62#define OMAP7XX_IO_CONF_7 0xfffe108c
63#define OMAP7XX_IO_CONF_8 0xfffe1090
64#define OMAP7XX_IO_CONF_9 0xfffe1094
65#define OMAP7XX_IO_CONF_10 0xfffe1098
66#define OMAP7XX_IO_CONF_11 0xfffe109c
67#define OMAP7XX_IO_CONF_12 0xfffe10a0
68#define OMAP7XX_IO_CONF_13 0xfffe10a4
69
70#define OMAP7XX_MODE_1 0xfffe1010
71#define OMAP7XX_MODE_2 0xfffe1014
72
73/* CSMI specials: in terms of base + offset */
74#define OMAP7XX_MODE2_OFFSET 0x14
75
76/*
77 * ----------------------------------------------------------------------------
78 * OMAP7XX traffic controller configuration registers
79 * ----------------------------------------------------------------------------
80 */
81#define OMAP7XX_FLASH_CFG_0 0xfffecc10
82#define OMAP7XX_FLASH_ACFG_0 0xfffecc50
83#define OMAP7XX_FLASH_CFG_1 0xfffecc14
84#define OMAP7XX_FLASH_ACFG_1 0xfffecc54
85
86/*
87 * ----------------------------------------------------------------------------
88 * OMAP7XX DSP control registers
89 * ----------------------------------------------------------------------------
90 */
91#define OMAP7XX_ICR_BASE 0xfffbb800
92#define OMAP7XX_DSP_M_CTL 0xfffbb804
93#define OMAP7XX_DSP_MMU_BASE 0xfffed200
94
95/*
96 * ----------------------------------------------------------------------------
97 * OMAP7XX PCC_UPLD configuration registers
98 * ----------------------------------------------------------------------------
99 */
100#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900)
101#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
102
103#endif /* __ASM_ARCH_OMAP7XX_H */
104
diff --git a/arch/arm/plat-omap/include/plat/omap850.h b/arch/arm/plat-omap/include/plat/omap850.h
new file mode 100644
index 000000000000..c33f67981712
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap850.h
@@ -0,0 +1,102 @@
1/* arch/arm/plat-omap/include/mach/omap850.h
2 *
3 * Hardware definitions for TI OMAP850 processor.
4 *
5 * Derived from omap730.h by Zebediah C. McClure <zmc@lurian.net>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __ASM_ARCH_OMAP850_H
29#define __ASM_ARCH_OMAP850_H
30
31/*
32 * ----------------------------------------------------------------------------
33 * Base addresses
34 * ----------------------------------------------------------------------------
35 */
36
37/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
38
39#define OMAP850_DSP_BASE 0xE0000000
40#define OMAP850_DSP_SIZE 0x50000
41#define OMAP850_DSP_START 0xE0000000
42
43#define OMAP850_DSPREG_BASE 0xE1000000
44#define OMAP850_DSPREG_SIZE SZ_128K
45#define OMAP850_DSPREG_START 0xE1000000
46
47/*
48 * ----------------------------------------------------------------------------
49 * OMAP850 specific configuration registers
50 * ----------------------------------------------------------------------------
51 */
52#define OMAP850_CONFIG_BASE 0xfffe1000
53#define OMAP850_IO_CONF_0 0xfffe1070
54#define OMAP850_IO_CONF_1 0xfffe1074
55#define OMAP850_IO_CONF_2 0xfffe1078
56#define OMAP850_IO_CONF_3 0xfffe107c
57#define OMAP850_IO_CONF_4 0xfffe1080
58#define OMAP850_IO_CONF_5 0xfffe1084
59#define OMAP850_IO_CONF_6 0xfffe1088
60#define OMAP850_IO_CONF_7 0xfffe108c
61#define OMAP850_IO_CONF_8 0xfffe1090
62#define OMAP850_IO_CONF_9 0xfffe1094
63#define OMAP850_IO_CONF_10 0xfffe1098
64#define OMAP850_IO_CONF_11 0xfffe109c
65#define OMAP850_IO_CONF_12 0xfffe10a0
66#define OMAP850_IO_CONF_13 0xfffe10a4
67
68#define OMAP850_MODE_1 0xfffe1010
69#define OMAP850_MODE_2 0xfffe1014
70
71/* CSMI specials: in terms of base + offset */
72#define OMAP850_MODE2_OFFSET 0x14
73
74/*
75 * ----------------------------------------------------------------------------
76 * OMAP850 traffic controller configuration registers
77 * ----------------------------------------------------------------------------
78 */
79#define OMAP850_FLASH_CFG_0 0xfffecc10
80#define OMAP850_FLASH_ACFG_0 0xfffecc50
81#define OMAP850_FLASH_CFG_1 0xfffecc14
82#define OMAP850_FLASH_ACFG_1 0xfffecc54
83
84/*
85 * ----------------------------------------------------------------------------
86 * OMAP850 DSP control registers
87 * ----------------------------------------------------------------------------
88 */
89#define OMAP850_ICR_BASE 0xfffbb800
90#define OMAP850_DSP_M_CTL 0xfffbb804
91#define OMAP850_DSP_MMU_BASE 0xfffed200
92
93/*
94 * ----------------------------------------------------------------------------
95 * OMAP850 PCC_UPLD configuration registers
96 * ----------------------------------------------------------------------------
97 */
98#define OMAP850_PCC_UPLD_CTRL_BASE (0xfffe0900)
99#define OMAP850_PCC_UPLD_CTRL (OMAP850_PCC_UPLD_CTRL_BASE + 0x00)
100
101#endif /* __ASM_ARCH_OMAP850_H */
102
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
new file mode 100644
index 000000000000..11a9773a4e7f
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -0,0 +1,141 @@
1/*
2 * omap_device headers
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Paul Walmsley
6 *
7 * Developed in collaboration with (alphabetical order): Benoit
8 * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram
9 * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
10 * Woodruff
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * Eventually this type of functionality should either be
17 * a) implemented via arch-specific pointers in platform_device
18 * or
19 * b) implemented as a proper omap_bus/omap_device in Linux, no more
20 * platform_device
21 *
22 * omap_device differs from omap_hwmod in that it includes external
23 * (e.g., board- and system-level) integration details. omap_hwmod
24 * stores hardware data that is invariant for a given OMAP chip.
25 *
26 * To do:
27 * - GPIO integration
28 * - regulator integration
29 *
30 */
31#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
32#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
33
34#include <linux/kernel.h>
35#include <linux/platform_device.h>
36
37#include <plat/omap_hwmod.h>
38
39/* omap_device._state values */
40#define OMAP_DEVICE_STATE_UNKNOWN 0
41#define OMAP_DEVICE_STATE_ENABLED 1
42#define OMAP_DEVICE_STATE_IDLE 2
43#define OMAP_DEVICE_STATE_SHUTDOWN 3
44
45/**
46 * struct omap_device - omap_device wrapper for platform_devices
47 * @pdev: platform_device
48 * @hwmods: (one .. many per omap_device)
49 * @hwmods_cnt: ARRAY_SIZE() of @hwmods
50 * @pm_lats: ptr to an omap_device_pm_latency table
51 * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
52 * @pm_lat_level: array index of the last odpl entry executed - -1 if never
53 * @dev_wakeup_lat: dev wakeup latency in microseconds
54 * @_dev_wakeup_lat_limit: dev wakeup latency limit in usec - set by OMAP PM
55 * @_state: one of OMAP_DEVICE_STATE_* (see above)
56 * @flags: device flags
57 *
58 * Integrates omap_hwmod data into Linux platform_device.
59 *
60 * Field names beginning with underscores are for the internal use of
61 * the omap_device code.
62 *
63 */
64struct omap_device {
65 struct platform_device pdev;
66 struct omap_hwmod **hwmods;
67 struct omap_device_pm_latency *pm_lats;
68 u32 dev_wakeup_lat;
69 u32 _dev_wakeup_lat_limit;
70 u8 pm_lats_cnt;
71 s8 pm_lat_level;
72 u8 hwmods_cnt;
73 u8 _state;
74};
75
76/* Device driver interface (call via platform_data fn ptrs) */
77
78int omap_device_enable(struct platform_device *pdev);
79int omap_device_idle(struct platform_device *pdev);
80int omap_device_shutdown(struct platform_device *pdev);
81
82/* Core code interface */
83
84int omap_device_count_resources(struct omap_device *od);
85int omap_device_fill_resources(struct omap_device *od, struct resource *res);
86
87struct omap_device *omap_device_build(const char *pdev_name, int pdev_id,
88 struct omap_hwmod *oh, void *pdata,
89 int pdata_len,
90 struct omap_device_pm_latency *pm_lats,
91 int pm_lats_cnt);
92
93struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
94 struct omap_hwmod **oh, int oh_cnt,
95 void *pdata, int pdata_len,
96 struct omap_device_pm_latency *pm_lats,
97 int pm_lats_cnt);
98
99int omap_device_register(struct omap_device *od);
100
101/* OMAP PM interface */
102int omap_device_align_pm_lat(struct platform_device *pdev,
103 u32 new_wakeup_lat_limit);
104struct powerdomain *omap_device_get_pwrdm(struct omap_device *od);
105
106/* Other */
107
108int omap_device_idle_hwmods(struct omap_device *od);
109int omap_device_enable_hwmods(struct omap_device *od);
110
111int omap_device_disable_clocks(struct omap_device *od);
112int omap_device_enable_clocks(struct omap_device *od);
113
114
115/*
116 * Entries should be kept in latency order ascending
117 *
118 * deact_lat is the maximum number of microseconds required to complete
119 * deactivate_func() at the device's slowest OPP.
120 *
121 * act_lat is the maximum number of microseconds required to complete
122 * activate_func() at the device's slowest OPP.
123 *
124 * This will result in some suboptimal power management decisions at fast
125 * OPPs, but avoids having to recompute all device power management decisions
126 * if the system shifts from a fast OPP to a slow OPP (in order to meet
127 * latency requirements).
128 *
129 * XXX should deactivate_func/activate_func() take platform_device pointers
130 * rather than omap_device pointers?
131 */
132struct omap_device_pm_latency {
133 u32 deactivate_lat;
134 int (*deactivate_func)(struct omap_device *od);
135 u32 activate_lat;
136 int (*activate_func)(struct omap_device *od);
137};
138
139
140#endif
141
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
new file mode 100644
index 000000000000..dbdd123eca16
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -0,0 +1,447 @@
1/*
2 * omap_hwmod macros, structures
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Paul Walmsley
6 *
7 * Created in collaboration with (alphabetical order): Benoit Cousson,
8 * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
9 * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * These headers and macros are used to define OMAP on-chip module
16 * data and their integration with other OMAP modules and Linux.
17 *
18 * References:
19 * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
20 * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
21 * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
22 * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
23 * - Open Core Protocol Specification 2.2
24 *
25 * To do:
26 * - add interconnect error log structures
27 * - add pinmuxing
28 * - init_conn_id_bit (CONNID_BIT_VECTOR)
29 * - implement default hwmod SMS/SDRC flags?
30 *
31 */
32#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
33#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
34
35#include <linux/kernel.h>
36#include <linux/ioport.h>
37
38#include <plat/cpu.h>
39
40struct omap_device;
41
42/* OCP SYSCONFIG bit shifts/masks */
43#define SYSC_MIDLEMODE_SHIFT 12
44#define SYSC_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT)
45#define SYSC_CLOCKACTIVITY_SHIFT 8
46#define SYSC_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT)
47#define SYSC_SIDLEMODE_SHIFT 3
48#define SYSC_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT)
49#define SYSC_ENAWAKEUP_SHIFT 2
50#define SYSC_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT)
51#define SYSC_SOFTRESET_SHIFT 1
52#define SYSC_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT)
53
54/* OCP SYSSTATUS bit shifts/masks */
55#define SYSS_RESETDONE_SHIFT 0
56#define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT)
57
58/* Master standby/slave idle mode flags */
59#define HWMOD_IDLEMODE_FORCE (1 << 0)
60#define HWMOD_IDLEMODE_NO (1 << 1)
61#define HWMOD_IDLEMODE_SMART (1 << 2)
62
63
64/**
65 * struct omap_hwmod_dma_info - MPU address space handled by the hwmod
66 * @name: name of the DMA channel (module local name)
67 * @dma_ch: DMA channel ID
68 *
69 * @name should be something short, e.g., "tx" or "rx". It is for use
70 * by platform_get_resource_byname(). It is defined locally to the
71 * hwmod.
72 */
73struct omap_hwmod_dma_info {
74 const char *name;
75 u16 dma_ch;
76};
77
78/**
79 * struct omap_hwmod_opt_clk - optional clocks used by this hwmod
80 * @role: "sys", "32k", "tv", etc -- for use in clk_get()
81 * @clkdev_dev_id: opt clock: clkdev dev_id string
82 * @clkdev_con_id: opt clock: clkdev con_id string
83 * @_clk: pointer to the struct clk (filled in at runtime)
84 *
85 * The module's interface clock and main functional clock should not
86 * be added as optional clocks.
87 */
88struct omap_hwmod_opt_clk {
89 const char *role;
90 const char *clkdev_dev_id;
91 const char *clkdev_con_id;
92 struct clk *_clk;
93};
94
95
96/* omap_hwmod_omap2_firewall.flags bits */
97#define OMAP_FIREWALL_L3 (1 << 0)
98#define OMAP_FIREWALL_L4 (1 << 1)
99
100/**
101 * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data
102 * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_*
103 * @l4_fw_region: L4 firewall region ID
104 * @l4_prot_group: L4 protection group ID
105 * @flags: (see omap_hwmod_omap2_firewall.flags macros above)
106 */
107struct omap_hwmod_omap2_firewall {
108 u8 l3_perm_bit;
109 u8 l4_fw_region;
110 u8 l4_prot_group;
111 u8 flags;
112};
113
114
115/*
116 * omap_hwmod_addr_space.flags bits
117 *
118 * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init.
119 * ADDR_TYPE_RT: Address space contains module register target data.
120 */
121#define ADDR_MAP_ON_INIT (1 << 0)
122#define ADDR_TYPE_RT (1 << 1)
123
124/**
125 * struct omap_hwmod_addr_space - MPU address space handled by the hwmod
126 * @pa_start: starting physical address
127 * @pa_end: ending physical address
128 * @flags: (see omap_hwmod_addr_space.flags macros above)
129 *
130 * Address space doesn't necessarily follow physical interconnect
131 * structure. GPMC is one example.
132 */
133struct omap_hwmod_addr_space {
134 u32 pa_start;
135 u32 pa_end;
136 u8 flags;
137};
138
139
140/*
141 * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
142 * interface to interact with the hwmod. Used to add sleep dependencies
143 * when the module is enabled or disabled.
144 */
145#define OCP_USER_MPU (1 << 0)
146#define OCP_USER_SDMA (1 << 1)
147
148/* omap_hwmod_ocp_if.flags bits */
149#define OCPIF_HAS_IDLEST (1 << 0)
150#define OCPIF_SWSUP_IDLE (1 << 1)
151#define OCPIF_CAN_BURST (1 << 2)
152
153/**
154 * struct omap_hwmod_ocp_if - OCP interface data
155 * @master: struct omap_hwmod that initiates OCP transactions on this link
156 * @slave: struct omap_hwmod that responds to OCP transactions on this link
157 * @addr: address space associated with this link
158 * @clkdev_dev_id: interface clock: clkdev dev_id string
159 * @clkdev_con_id: interface clock: clkdev con_id string
160 * @_clk: pointer to the interface struct clk (filled in at runtime)
161 * @fw: interface firewall data
162 * @addr_cnt: ARRAY_SIZE(@addr)
163 * @width: OCP data width
164 * @thread_cnt: number of threads
165 * @max_burst_len: maximum burst length in @width sized words (0 if unlimited)
166 * @user: initiators using this interface (see OCP_USER_* macros above)
167 * @flags: OCP interface flags (see OCPIF_* macros above)
168 *
169 * It may also be useful to add a tag_cnt field for OCP2.x devices.
170 *
171 * Parameter names beginning with an underscore are managed internally by
172 * the omap_hwmod code and should not be set during initialization.
173 */
174struct omap_hwmod_ocp_if {
175 struct omap_hwmod *master;
176 struct omap_hwmod *slave;
177 struct omap_hwmod_addr_space *addr;
178 const char *clkdev_dev_id;
179 const char *clkdev_con_id;
180 struct clk *_clk;
181 union {
182 struct omap_hwmod_omap2_firewall omap2;
183 } fw;
184 u8 addr_cnt;
185 u8 width;
186 u8 thread_cnt;
187 u8 max_burst_len;
188 u8 user;
189 u8 flags;
190};
191
192
193/* Macros for use in struct omap_hwmod_sysconfig */
194
195/* Flags for use in omap_hwmod_sysconfig.idlemodes */
196#define MASTER_STANDBY_SHIFT 2
197#define SLAVE_IDLE_SHIFT 0
198#define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
199#define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
200#define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
201#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
202#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
203#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
204
205/* omap_hwmod_sysconfig.sysc_flags capability flags */
206#define SYSC_HAS_AUTOIDLE (1 << 0)
207#define SYSC_HAS_SOFTRESET (1 << 1)
208#define SYSC_HAS_ENAWAKEUP (1 << 2)
209#define SYSC_HAS_EMUFREE (1 << 3)
210#define SYSC_HAS_CLOCKACTIVITY (1 << 4)
211#define SYSC_HAS_SIDLEMODE (1 << 5)
212#define SYSC_HAS_MIDLEMODE (1 << 6)
213#define SYSS_MISSING (1 << 7)
214
215/* omap_hwmod_sysconfig.clockact flags */
216#define CLOCKACT_TEST_BOTH 0x0
217#define CLOCKACT_TEST_MAIN 0x1
218#define CLOCKACT_TEST_ICLK 0x2
219#define CLOCKACT_TEST_NONE 0x3
220
221/**
222 * struct omap_hwmod_sysconfig - hwmod OCP_SYSCONFIG/OCP_SYSSTATUS data
223 * @rev_offs: IP block revision register offset (from module base addr)
224 * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
225 * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
226 * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
227 * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
228 * @clockact: the default value of the module CLOCKACTIVITY bits
229 *
230 * @clockact describes to the module which clocks are likely to be
231 * disabled when the PRCM issues its idle request to the module. Some
232 * modules have separate clockdomains for the interface clock and main
233 * functional clock, and can check whether they should acknowledge the
234 * idle request based on the internal module functionality that has
235 * been associated with the clocks marked in @clockact. This field is
236 * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
237 *
238 */
239struct omap_hwmod_sysconfig {
240 u16 rev_offs;
241 u16 sysc_offs;
242 u16 syss_offs;
243 u8 idlemodes;
244 u8 sysc_flags;
245 u8 clockact;
246};
247
248/**
249 * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
250 * @module_offs: PRCM submodule offset from the start of the PRM/CM
251 * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3)
252 * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs
253 * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
254 * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
255 * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit
256 *
257 * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
258 * WKEN, GRPSEL registers. In an ideal world, no extra information
259 * would be needed for IDLEST information, but alas, there are some
260 * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit
261 * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST)
262 */
263struct omap_hwmod_omap2_prcm {
264 s16 module_offs;
265 u8 prcm_reg_id;
266 u8 module_bit;
267 u8 idlest_reg_id;
268 u8 idlest_idle_bit;
269 u8 idlest_stdby_bit;
270};
271
272
273/**
274 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
275 * @module_offs: PRCM submodule offset from the start of the PRM/CM1/CM2
276 * @device_offs: device register offset from @module_offs
277 * @submodule_wkdep_bit: bit shift of the WKDEP range
278 */
279struct omap_hwmod_omap4_prcm {
280 u32 module_offs;
281 u16 device_offs;
282 u8 submodule_wkdep_bit;
283};
284
285
286/*
287 * omap_hwmod.flags definitions
288 *
289 * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
290 * of idle, rather than relying on module smart-idle
291 * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
292 * of standby, rather than relying on module smart-standby
293 * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
294 * SDRAM controller, etc.
295 * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
296 * controller, etc.
297 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
298 */
299#define HWMOD_SWSUP_SIDLE (1 << 0)
300#define HWMOD_SWSUP_MSTANDBY (1 << 1)
301#define HWMOD_INIT_NO_RESET (1 << 2)
302#define HWMOD_INIT_NO_IDLE (1 << 3)
303#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 4)
304
305/*
306 * omap_hwmod._int_flags definitions
307 * These are for internal use only and are managed by the omap_hwmod code.
308 *
309 * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
310 * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
311 * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
312 */
313#define _HWMOD_NO_MPU_PORT (1 << 0)
314#define _HWMOD_WAKEUP_ENABLED (1 << 1)
315#define _HWMOD_SYSCONFIG_LOADED (1 << 2)
316
317/*
318 * omap_hwmod._state definitions
319 *
320 * INITIALIZED: reset (optionally), initialized, enabled, disabled
321 * (optionally)
322 *
323 *
324 */
325#define _HWMOD_STATE_UNKNOWN 0
326#define _HWMOD_STATE_REGISTERED 1
327#define _HWMOD_STATE_CLKS_INITED 2
328#define _HWMOD_STATE_INITIALIZED 3
329#define _HWMOD_STATE_ENABLED 4
330#define _HWMOD_STATE_IDLE 5
331#define _HWMOD_STATE_DISABLED 6
332
333/**
334 * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
335 * @name: name of the hwmod
336 * @od: struct omap_device currently associated with this hwmod (internal use)
337 * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
338 * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt)
339 * @prcm: PRCM data pertaining to this hwmod
340 * @clkdev_dev_id: main clock: clkdev dev_id string
341 * @clkdev_con_id: main clock: clkdev con_id string
342 * @_clk: pointer to the main struct clk (filled in at runtime)
343 * @opt_clks: other device clocks that drivers can request (0..*)
344 * @masters: ptr to array of OCP ifs that this hwmod can initiate on
345 * @slaves: ptr to array of OCP ifs that this hwmod can respond on
346 * @sysconfig: device SYSCONFIG/SYSSTATUS register data
347 * @dev_attr: arbitrary device attributes that can be passed to the driver
348 * @_sysc_cache: internal-use hwmod flags
349 * @_rt_va: cached register target start address (internal use)
350 * @_mpu_port_index: cached MPU register target slave ID (internal use)
351 * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
352 * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
353 * @mpu_irqs_cnt: number of @mpu_irqs
354 * @sdma_chs_cnt: number of @sdma_chs
355 * @opt_clks_cnt: number of @opt_clks
356 * @master_cnt: number of @master entries
357 * @slaves_cnt: number of @slave entries
358 * @response_lat: device OCP response latency (in interface clock cycles)
359 * @_int_flags: internal-use hwmod flags
360 * @_state: internal-use hwmod state
361 * @flags: hwmod flags (documented below)
362 * @omap_chip: OMAP chips this hwmod is present on
363 * @node: list node for hwmod list (internal use)
364 *
365 * @clkdev_dev_id, @clkdev_con_id, and @clk all refer to this module's "main
366 * clock," which for our purposes is defined as "the functional clock needed
367 * for register accesses to complete." Modules may not have a main clock if
368 * the interface clock also serves as a main clock.
369 *
370 * Parameter names beginning with an underscore are managed internally by
371 * the omap_hwmod code and should not be set during initialization.
372 */
373struct omap_hwmod {
374 const char *name;
375 struct omap_device *od;
376 u8 *mpu_irqs;
377 struct omap_hwmod_dma_info *sdma_chs;
378 union {
379 struct omap_hwmod_omap2_prcm omap2;
380 struct omap_hwmod_omap4_prcm omap4;
381 } prcm;
382 const char *clkdev_dev_id;
383 const char *clkdev_con_id;
384 struct clk *_clk;
385 struct omap_hwmod_opt_clk *opt_clks;
386 struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
387 struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */
388 struct omap_hwmod_sysconfig *sysconfig;
389 void *dev_attr;
390 u32 _sysc_cache;
391 void __iomem *_rt_va;
392 struct list_head node;
393 u16 flags;
394 u8 _mpu_port_index;
395 u8 msuspendmux_reg_id;
396 u8 msuspendmux_shift;
397 u8 response_lat;
398 u8 mpu_irqs_cnt;
399 u8 sdma_chs_cnt;
400 u8 opt_clks_cnt;
401 u8 masters_cnt;
402 u8 slaves_cnt;
403 u8 hwmods_cnt;
404 u8 _int_flags;
405 u8 _state;
406 const struct omap_chip_id omap_chip;
407};
408
409int omap_hwmod_init(struct omap_hwmod **ohs);
410int omap_hwmod_register(struct omap_hwmod *oh);
411int omap_hwmod_unregister(struct omap_hwmod *oh);
412struct omap_hwmod *omap_hwmod_lookup(const char *name);
413int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh));
414int omap_hwmod_late_init(void);
415
416int omap_hwmod_enable(struct omap_hwmod *oh);
417int omap_hwmod_idle(struct omap_hwmod *oh);
418int omap_hwmod_shutdown(struct omap_hwmod *oh);
419
420int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
421int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
422
423int omap_hwmod_reset(struct omap_hwmod *oh);
424void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
425
426void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs);
427u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs);
428
429int omap_hwmod_count_resources(struct omap_hwmod *oh);
430int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
431
432struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
433
434int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
435 struct omap_hwmod *init_oh);
436int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
437 struct omap_hwmod *init_oh);
438
439int omap_hwmod_set_clockact_both(struct omap_hwmod *oh);
440int omap_hwmod_set_clockact_main(struct omap_hwmod *oh);
441int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh);
442int omap_hwmod_set_clockact_none(struct omap_hwmod *oh);
443
444int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
445int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
446
447#endif
diff --git a/arch/arm/plat-omap/include/plat/omapfb.h b/arch/arm/plat-omap/include/plat/omapfb.h
new file mode 100644
index 000000000000..bfef7ab95f17
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omapfb.h
@@ -0,0 +1,398 @@
1/*
2 * File: arch/arm/plat-omap/include/mach/omapfb.h
3 *
4 * Framebuffer driver for TI OMAP boards
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 * Author: Imre Deak <imre.deak@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#ifndef __OMAPFB_H
25#define __OMAPFB_H
26
27#include <asm/ioctl.h>
28#include <asm/types.h>
29
30/* IOCTL commands. */
31
32#define OMAP_IOW(num, dtype) _IOW('O', num, dtype)
33#define OMAP_IOR(num, dtype) _IOR('O', num, dtype)
34#define OMAP_IOWR(num, dtype) _IOWR('O', num, dtype)
35#define OMAP_IO(num) _IO('O', num)
36
37#define OMAPFB_MIRROR OMAP_IOW(31, int)
38#define OMAPFB_SYNC_GFX OMAP_IO(37)
39#define OMAPFB_VSYNC OMAP_IO(38)
40#define OMAPFB_SET_UPDATE_MODE OMAP_IOW(40, int)
41#define OMAPFB_GET_CAPS OMAP_IOR(42, struct omapfb_caps)
42#define OMAPFB_GET_UPDATE_MODE OMAP_IOW(43, int)
43#define OMAPFB_LCD_TEST OMAP_IOW(45, int)
44#define OMAPFB_CTRL_TEST OMAP_IOW(46, int)
45#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old)
46#define OMAPFB_SET_COLOR_KEY OMAP_IOW(50, struct omapfb_color_key)
47#define OMAPFB_GET_COLOR_KEY OMAP_IOW(51, struct omapfb_color_key)
48#define OMAPFB_SETUP_PLANE OMAP_IOW(52, struct omapfb_plane_info)
49#define OMAPFB_QUERY_PLANE OMAP_IOW(53, struct omapfb_plane_info)
50#define OMAPFB_UPDATE_WINDOW OMAP_IOW(54, struct omapfb_update_window)
51#define OMAPFB_SETUP_MEM OMAP_IOW(55, struct omapfb_mem_info)
52#define OMAPFB_QUERY_MEM OMAP_IOW(56, struct omapfb_mem_info)
53
54#define OMAPFB_CAPS_GENERIC_MASK 0x00000fff
55#define OMAPFB_CAPS_LCDC_MASK 0x00fff000
56#define OMAPFB_CAPS_PANEL_MASK 0xff000000
57
58#define OMAPFB_CAPS_MANUAL_UPDATE 0x00001000
59#define OMAPFB_CAPS_TEARSYNC 0x00002000
60#define OMAPFB_CAPS_PLANE_RELOCATE_MEM 0x00004000
61#define OMAPFB_CAPS_PLANE_SCALE 0x00008000
62#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
63#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000
64#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000
65#define OMAPFB_CAPS_WINDOW_ROTATE 0x00080000
66#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000
67
68/* Values from DSP must map to lower 16-bits */
69#define OMAPFB_FORMAT_MASK 0x00ff
70#define OMAPFB_FORMAT_FLAG_DOUBLE 0x0100
71#define OMAPFB_FORMAT_FLAG_TEARSYNC 0x0200
72#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC 0x0400
73#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY 0x0800
74#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY 0x1000
75
76#define OMAPFB_EVENT_READY 1
77#define OMAPFB_EVENT_DISABLED 2
78
79#define OMAPFB_MEMTYPE_SDRAM 0
80#define OMAPFB_MEMTYPE_SRAM 1
81#define OMAPFB_MEMTYPE_MAX 1
82
83enum omapfb_color_format {
84 OMAPFB_COLOR_RGB565 = 0,
85 OMAPFB_COLOR_YUV422,
86 OMAPFB_COLOR_YUV420,
87 OMAPFB_COLOR_CLUT_8BPP,
88 OMAPFB_COLOR_CLUT_4BPP,
89 OMAPFB_COLOR_CLUT_2BPP,
90 OMAPFB_COLOR_CLUT_1BPP,
91 OMAPFB_COLOR_RGB444,
92 OMAPFB_COLOR_YUY422,
93};
94
95struct omapfb_update_window {
96 __u32 x, y;
97 __u32 width, height;
98 __u32 format;
99 __u32 out_x, out_y;
100 __u32 out_width, out_height;
101 __u32 reserved[8];
102};
103
104struct omapfb_update_window_old {
105 __u32 x, y;
106 __u32 width, height;
107 __u32 format;
108};
109
110enum omapfb_plane {
111 OMAPFB_PLANE_GFX = 0,
112 OMAPFB_PLANE_VID1,
113 OMAPFB_PLANE_VID2,
114};
115
116enum omapfb_channel_out {
117 OMAPFB_CHANNEL_OUT_LCD = 0,
118 OMAPFB_CHANNEL_OUT_DIGIT,
119};
120
121struct omapfb_plane_info {
122 __u32 pos_x;
123 __u32 pos_y;
124 __u8 enabled;
125 __u8 channel_out;
126 __u8 mirror;
127 __u8 reserved1;
128 __u32 out_width;
129 __u32 out_height;
130 __u32 reserved2[12];
131};
132
133struct omapfb_mem_info {
134 __u32 size;
135 __u8 type;
136 __u8 reserved[3];
137};
138
139struct omapfb_caps {
140 __u32 ctrl;
141 __u32 plane_color;
142 __u32 wnd_color;
143};
144
145enum omapfb_color_key_type {
146 OMAPFB_COLOR_KEY_DISABLED = 0,
147 OMAPFB_COLOR_KEY_GFX_DST,
148 OMAPFB_COLOR_KEY_VID_SRC,
149};
150
151struct omapfb_color_key {
152 __u8 channel_out;
153 __u32 background;
154 __u32 trans_key;
155 __u8 key_type;
156};
157
158enum omapfb_update_mode {
159 OMAPFB_UPDATE_DISABLED = 0,
160 OMAPFB_AUTO_UPDATE,
161 OMAPFB_MANUAL_UPDATE
162};
163
164#ifdef __KERNEL__
165
166#include <linux/completion.h>
167#include <linux/interrupt.h>
168#include <linux/fb.h>
169#include <linux/mutex.h>
170
171#include <plat/board.h>
172
173#define OMAP_LCDC_INV_VSYNC 0x0001
174#define OMAP_LCDC_INV_HSYNC 0x0002
175#define OMAP_LCDC_INV_PIX_CLOCK 0x0004
176#define OMAP_LCDC_INV_OUTPUT_EN 0x0008
177#define OMAP_LCDC_HSVS_RISING_EDGE 0x0010
178#define OMAP_LCDC_HSVS_OPPOSITE 0x0020
179
180#define OMAP_LCDC_SIGNAL_MASK 0x003f
181
182#define OMAP_LCDC_PANEL_TFT 0x0100
183
184#define OMAPFB_PLANE_XRES_MIN 8
185#define OMAPFB_PLANE_YRES_MIN 8
186
187#ifdef CONFIG_ARCH_OMAP1
188#define OMAPFB_PLANE_NUM 1
189#else
190#define OMAPFB_PLANE_NUM 3
191#endif
192
193struct omapfb_device;
194
195struct lcd_panel {
196 const char *name;
197 int config; /* TFT/STN, signal inversion */
198 int bpp; /* Pixel format in fb mem */
199 int data_lines; /* Lines on LCD HW interface */
200
201 int x_res, y_res;
202 int pixel_clock; /* In kHz */
203 int hsw; /* Horizontal synchronization
204 pulse width */
205 int hfp; /* Horizontal front porch */
206 int hbp; /* Horizontal back porch */
207 int vsw; /* Vertical synchronization
208 pulse width */
209 int vfp; /* Vertical front porch */
210 int vbp; /* Vertical back porch */
211 int acb; /* ac-bias pin frequency */
212 int pcd; /* pixel clock divider.
213 Obsolete use pixel_clock instead */
214
215 int (*init) (struct lcd_panel *panel,
216 struct omapfb_device *fbdev);
217 void (*cleanup) (struct lcd_panel *panel);
218 int (*enable) (struct lcd_panel *panel);
219 void (*disable) (struct lcd_panel *panel);
220 unsigned long (*get_caps) (struct lcd_panel *panel);
221 int (*set_bklight_level)(struct lcd_panel *panel,
222 unsigned int level);
223 unsigned int (*get_bklight_level)(struct lcd_panel *panel);
224 unsigned int (*get_bklight_max) (struct lcd_panel *panel);
225 int (*run_test) (struct lcd_panel *panel, int test_num);
226};
227
228struct extif_timings {
229 int cs_on_time;
230 int cs_off_time;
231 int we_on_time;
232 int we_off_time;
233 int re_on_time;
234 int re_off_time;
235 int we_cycle_time;
236 int re_cycle_time;
237 int cs_pulse_width;
238 int access_time;
239
240 int clk_div;
241
242 u32 tim[5]; /* set by extif->convert_timings */
243
244 int converted;
245};
246
247struct lcd_ctrl_extif {
248 int (*init) (struct omapfb_device *fbdev);
249 void (*cleanup) (void);
250 void (*get_clk_info) (u32 *clk_period, u32 *max_clk_div);
251 unsigned long (*get_max_tx_rate)(void);
252 int (*convert_timings) (struct extif_timings *timings);
253 void (*set_timings) (const struct extif_timings *timings);
254 void (*set_bits_per_cycle)(int bpc);
255 void (*write_command) (const void *buf, unsigned int len);
256 void (*read_data) (void *buf, unsigned int len);
257 void (*write_data) (const void *buf, unsigned int len);
258 void (*transfer_area) (int width, int height,
259 void (callback)(void * data), void *data);
260 int (*setup_tearsync) (unsigned pin_cnt,
261 unsigned hs_pulse_time, unsigned vs_pulse_time,
262 int hs_pol_inv, int vs_pol_inv, int div);
263 int (*enable_tearsync) (int enable, unsigned line);
264
265 unsigned long max_transmit_size;
266};
267
268struct omapfb_notifier_block {
269 struct notifier_block nb;
270 void *data;
271 int plane_idx;
272};
273
274typedef int (*omapfb_notifier_callback_t)(struct notifier_block *,
275 unsigned long event,
276 void *fbi);
277
278struct omapfb_mem_region {
279 u32 paddr;
280 void __iomem *vaddr;
281 unsigned long size;
282 u8 type; /* OMAPFB_PLANE_MEM_* */
283 unsigned alloc:1; /* allocated by the driver */
284 unsigned map:1; /* kernel mapped by the driver */
285};
286
287struct omapfb_mem_desc {
288 int region_cnt;
289 struct omapfb_mem_region region[OMAPFB_PLANE_NUM];
290};
291
292struct lcd_ctrl {
293 const char *name;
294 void *data;
295
296 int (*init) (struct omapfb_device *fbdev,
297 int ext_mode,
298 struct omapfb_mem_desc *req_md);
299 void (*cleanup) (void);
300 void (*bind_client) (struct omapfb_notifier_block *nb);
301 void (*get_caps) (int plane, struct omapfb_caps *caps);
302 int (*set_update_mode)(enum omapfb_update_mode mode);
303 enum omapfb_update_mode (*get_update_mode)(void);
304 int (*setup_plane) (int plane, int channel_out,
305 unsigned long offset,
306 int screen_width,
307 int pos_x, int pos_y, int width,
308 int height, int color_mode);
309 int (*set_rotate) (int angle);
310 int (*setup_mem) (int plane, size_t size,
311 int mem_type, unsigned long *paddr);
312 int (*mmap) (struct fb_info *info,
313 struct vm_area_struct *vma);
314 int (*set_scale) (int plane,
315 int orig_width, int orig_height,
316 int out_width, int out_height);
317 int (*enable_plane) (int plane, int enable);
318 int (*update_window) (struct fb_info *fbi,
319 struct omapfb_update_window *win,
320 void (*callback)(void *),
321 void *callback_data);
322 void (*sync) (void);
323 void (*suspend) (void);
324 void (*resume) (void);
325 int (*run_test) (int test_num);
326 int (*setcolreg) (u_int regno, u16 red, u16 green,
327 u16 blue, u16 transp,
328 int update_hw_mem);
329 int (*set_color_key) (struct omapfb_color_key *ck);
330 int (*get_color_key) (struct omapfb_color_key *ck);
331};
332
333enum omapfb_state {
334 OMAPFB_DISABLED = 0,
335 OMAPFB_SUSPENDED= 99,
336 OMAPFB_ACTIVE = 100
337};
338
339struct omapfb_plane_struct {
340 int idx;
341 struct omapfb_plane_info info;
342 enum omapfb_color_format color_mode;
343 struct omapfb_device *fbdev;
344};
345
346struct omapfb_device {
347 int state;
348 int ext_lcdc; /* Using external
349 LCD controller */
350 struct mutex rqueue_mutex;
351
352 int palette_size;
353 u32 pseudo_palette[17];
354
355 struct lcd_panel *panel; /* LCD panel */
356 const struct lcd_ctrl *ctrl; /* LCD controller */
357 const struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */
358 struct lcd_ctrl_extif *ext_if; /* LCD ctrl external
359 interface */
360 struct device *dev;
361 struct fb_var_screeninfo new_var; /* for mode changes */
362
363 struct omapfb_mem_desc mem_desc;
364 struct fb_info *fb_info[OMAPFB_PLANE_NUM];
365};
366
367struct omapfb_platform_data {
368 struct omap_lcd_config lcd;
369 struct omapfb_mem_desc mem_desc;
370 void *ctrl_platform_data;
371};
372
373#ifdef CONFIG_ARCH_OMAP1
374extern struct lcd_ctrl omap1_lcd_ctrl;
375#else
376extern struct lcd_ctrl omap2_disp_ctrl;
377#endif
378
379extern void omapfb_reserve_sdram(void);
380extern void omapfb_register_panel(struct lcd_panel *panel);
381extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
382extern void omapfb_notify_clients(struct omapfb_device *fbdev,
383 unsigned long event);
384extern int omapfb_register_client(struct omapfb_notifier_block *nb,
385 omapfb_notifier_callback_t callback,
386 void *callback_data);
387extern int omapfb_unregister_client(struct omapfb_notifier_block *nb);
388extern int omapfb_update_window_async(struct fb_info *fbi,
389 struct omapfb_update_window *win,
390 void (*callback)(void *),
391 void *callback_data);
392
393/* in arch/arm/plat-omap/fb.c */
394extern void omapfb_set_ctrl_platform_data(void *pdata);
395
396#endif /* __KERNEL__ */
397
398#endif /* __OMAPFB_H */
diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h
new file mode 100644
index 000000000000..72f433d7d827
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/onenand.h
@@ -0,0 +1,43 @@
1/*
2 * arch/arm/plat-omap/include/mach/onenand.h
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Author: Juha Yrjola
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/mtd/mtd.h>
13#include <linux/mtd/partitions.h>
14
15#define ONENAND_SYNC_READ (1 << 0)
16#define ONENAND_SYNC_READWRITE (1 << 1)
17
18struct omap_onenand_platform_data {
19 int cs;
20 int gpio_irq;
21 struct mtd_partition *parts;
22 int nr_parts;
23 int (*onenand_setup)(void __iomem *, int freq);
24 int dma_channel;
25 u8 flags;
26};
27
28#define ONENAND_MAX_PARTITIONS 8
29
30#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
31 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
32
33extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
34
35#else
36
37#define board_onenand_data NULL
38
39static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
40{
41}
42
43#endif
diff --git a/arch/arm/plat-omap/include/plat/param.h b/arch/arm/plat-omap/include/plat/param.h
new file mode 100644
index 000000000000..1eb4dc326979
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/param.h
@@ -0,0 +1,8 @@
1/*
2 * arch/arm/plat-omap/include/mach/param.h
3 *
4 */
5
6#ifdef CONFIG_OMAP_32K_TIMER_HZ
7#define HZ CONFIG_OMAP_32K_TIMER_HZ
8#endif
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
new file mode 100644
index 000000000000..3d45ee1d3cf4
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -0,0 +1,182 @@
1/*
2 * OMAP2/3 powerdomain control
3 *
4 * Copyright (C) 2007-8 Texas Instruments, Inc.
5 * Copyright (C) 2007-8 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
15#define ASM_ARM_ARCH_OMAP_POWERDOMAIN
16
17#include <linux/types.h>
18#include <linux/list.h>
19
20#include <asm/atomic.h>
21
22#include <plat/cpu.h>
23
24
25/* Powerdomain basic power states */
26#define PWRDM_POWER_OFF 0x0
27#define PWRDM_POWER_RET 0x1
28#define PWRDM_POWER_INACTIVE 0x2
29#define PWRDM_POWER_ON 0x3
30
31/* Powerdomain allowable state bitfields */
32#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
33 (1 << PWRDM_POWER_ON))
34
35#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
36 (1 << PWRDM_POWER_RET))
37
38#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
39
40
41/* Powerdomain flags */
42#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
43
44
45/*
46 * Number of memory banks that are power-controllable. On OMAP3430, the
47 * maximum is 4.
48 */
49#define PWRDM_MAX_MEM_BANKS 4
50
51/*
52 * Maximum number of clockdomains that can be associated with a powerdomain.
53 * CORE powerdomain on OMAP3 is the worst case
54 */
55#define PWRDM_MAX_CLKDMS 4
56
57/* XXX A completely arbitrary number. What is reasonable here? */
58#define PWRDM_TRANSITION_BAILOUT 100000
59
60struct clockdomain;
61struct powerdomain;
62
63/* Encodes dependencies between powerdomains - statically defined */
64struct pwrdm_dep {
65
66 /* Powerdomain name */
67 const char *pwrdm_name;
68
69 /* Powerdomain pointer - resolved by the powerdomain code */
70 struct powerdomain *pwrdm;
71
72 /* Flags to mark OMAP chip restrictions, etc. */
73 const struct omap_chip_id omap_chip;
74
75};
76
77struct powerdomain {
78
79 /* Powerdomain name */
80 const char *name;
81
82 /* the address offset from CM_BASE/PRM_BASE */
83 const s16 prcm_offs;
84
85 /* Used to represent the OMAP chip types containing this pwrdm */
86 const struct omap_chip_id omap_chip;
87
88 /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
89 const u8 dep_bit;
90
91 /* Powerdomains that can be told to wake this powerdomain up */
92 struct pwrdm_dep *wkdep_srcs;
93
94 /* Powerdomains that can be told to keep this pwrdm from inactivity */
95 struct pwrdm_dep *sleepdep_srcs;
96
97 /* Possible powerdomain power states */
98 const u8 pwrsts;
99
100 /* Possible logic power states when pwrdm in RETENTION */
101 const u8 pwrsts_logic_ret;
102
103 /* Powerdomain flags */
104 const u8 flags;
105
106 /* Number of software-controllable memory banks in this powerdomain */
107 const u8 banks;
108
109 /* Possible memory bank pwrstates when pwrdm in RETENTION */
110 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
111
112 /* Possible memory bank pwrstates when pwrdm is ON */
113 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
114
115 /* Clockdomains in this powerdomain */
116 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
117
118 struct list_head node;
119
120 int state;
121 unsigned state_counter[4];
122
123#ifdef CONFIG_PM_DEBUG
124 s64 timer;
125 s64 state_timer[4];
126#endif
127};
128
129
130void pwrdm_init(struct powerdomain **pwrdm_list);
131
132int pwrdm_register(struct powerdomain *pwrdm);
133int pwrdm_unregister(struct powerdomain *pwrdm);
134struct powerdomain *pwrdm_lookup(const char *name);
135
136int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
137 void *user);
138int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
139 void *user);
140
141int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
142int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
143int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
144 int (*fn)(struct powerdomain *pwrdm,
145 struct clockdomain *clkdm));
146
147int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
148int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
149int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
150int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
151int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
152int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
153
154int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
155
156int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
157int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
158int pwrdm_read_pwrst(struct powerdomain *pwrdm);
159int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
160int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
161
162int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
163int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
164int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
165
166int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
167int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
168int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
169int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
170
171int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
172int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
173bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
174
175int pwrdm_wait_transition(struct powerdomain *pwrdm);
176
177int pwrdm_state_switch(struct powerdomain *pwrdm);
178int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
179int pwrdm_pre_transition(void);
180int pwrdm_post_transition(void);
181
182#endif
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
new file mode 100644
index 000000000000..e63e94e18975
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -0,0 +1,39 @@
1/*
2 * arch/arm/plat-omap/include/mach/prcm.h
3 *
4 * Access definations for use in OMAP24XX clock and power management
5 *
6 * Copyright (C) 2005 Texas Instruments, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __ASM_ARM_ARCH_OMAP_PRCM_H
24#define __ASM_ARM_ARCH_OMAP_PRCM_H
25
26u32 omap_prcm_get_reset_sources(void);
27void omap_prcm_arch_reset(char mode);
28int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
29
30#define START_PADCONF_SAVE 0x2
31#define PADCONF_SAVE_DONE 0x1
32
33void omap3_prcm_save_context(void);
34void omap3_prcm_restore_context(void);
35
36#endif
37
38
39
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
new file mode 100644
index 000000000000..f704030d2a70
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/sdrc.h
@@ -0,0 +1,151 @@
1#ifndef ____ASM_ARCH_SDRC_H
2#define ____ASM_ARCH_SDRC_H
3
4/*
5 * OMAP2/3 SDRC/SMS register definitions
6 *
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
9 *
10 * Tony Lindgren
11 * Paul Walmsley
12 * Richard Woodruff
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <mach/io.h>
20
21/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
22
23#define SDRC_SYSCONFIG 0x010
24#define SDRC_CS_CFG 0x040
25#define SDRC_SHARING 0x044
26#define SDRC_ERR_TYPE 0x04C
27#define SDRC_DLLA_CTRL 0x060
28#define SDRC_DLLA_STATUS 0x064
29#define SDRC_DLLB_CTRL 0x068
30#define SDRC_DLLB_STATUS 0x06C
31#define SDRC_POWER 0x070
32#define SDRC_MCFG_0 0x080
33#define SDRC_MR_0 0x084
34#define SDRC_EMR2_0 0x08c
35#define SDRC_ACTIM_CTRL_A_0 0x09c
36#define SDRC_ACTIM_CTRL_B_0 0x0a0
37#define SDRC_RFR_CTRL_0 0x0a4
38#define SDRC_MANUAL_0 0x0a8
39#define SDRC_MCFG_1 0x0B0
40#define SDRC_MR_1 0x0B4
41#define SDRC_EMR2_1 0x0BC
42#define SDRC_ACTIM_CTRL_A_1 0x0C4
43#define SDRC_ACTIM_CTRL_B_1 0x0C8
44#define SDRC_RFR_CTRL_1 0x0D4
45#define SDRC_MANUAL_1 0x0D8
46
47#define SDRC_POWER_AUTOCOUNT_SHIFT 8
48#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
49#define SDRC_POWER_CLKCTRL_SHIFT 4
50#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
51#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
52
53/*
54 * These values represent the number of memory clock cycles between
55 * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
56 * rows per device, and include a subtraction of a 50 cycle window in the
57 * event that the autorefresh command is delayed due to other SDRC activity.
58 * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
59 * counter reaches 0.
60 *
61 * These represent optimal values for common parts, it won't work for all.
62 * As long as you scale down, most parameters are still work, they just
63 * become sub-optimal. The RFR value goes in the opposite direction. If you
64 * don't adjust it down as your clock period increases the refresh interval
65 * will not be met. Setting all parameters for complete worst case may work,
66 * but may cut memory performance by 2x. Due to errata the DLLs need to be
67 * unlocked and their value needs run time calibration. A dynamic call is
68 * need for that as no single right value exists acorss production samples.
69 *
70 * Only the FULL speed values are given. Current code is such that rate
71 * changes must be made at DPLLoutx2. The actual value adjustment for low
72 * frequency operation will be handled by omap_set_performance()
73 *
74 * By having the boot loader boot up in the fastest L4 speed available likely
75 * will result in something which you can switch between.
76 */
77#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
78#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
79#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
80#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
81#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
82
83
84/*
85 * SMS register access
86 */
87
88#define OMAP242X_SMS_REGADDR(reg) \
89 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
90#define OMAP243X_SMS_REGADDR(reg) \
91 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
92#define OMAP343X_SMS_REGADDR(reg) \
93 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
94
95/* SMS register offsets - read/write with sms_{read,write}_reg() */
96
97#define SMS_SYSCONFIG 0x010
98/* REVISIT: fill in other SMS registers here */
99
100
101#ifndef __ASSEMBLER__
102
103/**
104 * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
105 * @rate: SDRC clock rate (in Hz)
106 * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
107 * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
108 * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
109 * @mr: Value to program to SDRC_MR for this rate
110 *
111 * This structure holds a pre-computed set of register values for the
112 * SDRC for a given SDRC clock rate and SDRAM chip. These are
113 * intended to be pre-computed and specified in an array in the board-*.c
114 * files. The structure is keyed off the 'rate' field.
115 */
116struct omap_sdrc_params {
117 unsigned long rate;
118 u32 actim_ctrla;
119 u32 actim_ctrlb;
120 u32 rfr_ctrl;
121 u32 mr;
122};
123
124void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
125 struct omap_sdrc_params *sdrc_cs1);
126int omap2_sdrc_get_params(unsigned long r,
127 struct omap_sdrc_params **sdrc_cs0,
128 struct omap_sdrc_params **sdrc_cs1);
129void omap2_sms_save_context(void);
130void omap2_sms_restore_context(void);
131
132#ifdef CONFIG_ARCH_OMAP2
133
134struct memory_timings {
135 u32 m_type; /* ddr = 1, sdr = 0 */
136 u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
137 u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
138 u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
139 u32 base_cs; /* base chip select to use for calculations */
140};
141
142extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
143
144u32 omap2xxx_sdrc_dll_is_unlocked(void);
145u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
146
147#endif /* CONFIG_ARCH_OMAP2 */
148
149#endif /* __ASSEMBLER__ */
150
151#endif
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
new file mode 100644
index 000000000000..e249186d26e2
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -0,0 +1,68 @@
1/*
2 * arch/arm/plat-omap/include/mach/serial.h
3 *
4 * Copyright (C) 2009 Texas Instruments
5 * Addded OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __ASM_ARCH_SERIAL_H
14#define __ASM_ARCH_SERIAL_H
15
16#include <linux/init.h>
17
18#if defined(CONFIG_ARCH_OMAP1)
19/* OMAP1 serial ports */
20#define OMAP_UART1_BASE 0xfffb0000
21#define OMAP_UART2_BASE 0xfffb0800
22#define OMAP_UART3_BASE 0xfffb9800
23#define OMAP_MAX_NR_PORTS 3
24#elif defined(CONFIG_ARCH_OMAP2)
25/* OMAP2 serial ports */
26#define OMAP_UART1_BASE 0x4806a000
27#define OMAP_UART2_BASE 0x4806c000
28#define OMAP_UART3_BASE 0x4806e000
29#define OMAP_MAX_NR_PORTS 3
30#elif defined(CONFIG_ARCH_OMAP3)
31/* OMAP3 serial ports */
32#define OMAP_UART1_BASE 0x4806a000
33#define OMAP_UART2_BASE 0x4806c000
34#define OMAP_UART3_BASE 0x49020000
35#define OMAP_MAX_NR_PORTS 3
36#elif defined(CONFIG_ARCH_OMAP4)
37/* OMAP4 serial ports */
38#define OMAP_UART1_BASE 0x4806a000
39#define OMAP_UART2_BASE 0x4806c000
40#define OMAP_UART3_BASE 0x48020000
41#define OMAP_UART4_BASE 0x4806e000
42#define OMAP_MAX_NR_PORTS 4
43#endif
44
45#define OMAP1510_BASE_BAUD (12000000/16)
46#define OMAP16XX_BASE_BAUD (48000000/16)
47#define OMAP24XX_BASE_BAUD (48000000/16)
48
49#define is_omap_port(pt) ({int __ret = 0; \
50 if ((pt)->port.mapbase == OMAP_UART1_BASE || \
51 (pt)->port.mapbase == OMAP_UART2_BASE || \
52 (pt)->port.mapbase == OMAP_UART3_BASE) \
53 __ret = 1; \
54 __ret; \
55 })
56
57#ifndef __ASSEMBLER__
58extern void __init omap_serial_early_init(void);
59extern void omap_serial_init(void);
60extern int omap_uart_can_sleep(void);
61extern void omap_uart_check_wakeup(void);
62extern void omap_uart_prepare_suspend(void);
63extern void omap_uart_prepare_idle(int num);
64extern void omap_uart_resume_idle(int num);
65extern void omap_uart_enable_irqs(int enable);
66#endif
67
68#endif
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
new file mode 100644
index 000000000000..dcaa8fde7063
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -0,0 +1,51 @@
1/*
2 * OMAP4 machine specific smp.h
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc.
5 *
6 * Author:
7 * Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * Interface functions needed for the SMP. This file is based on arm
10 * realview smp platform.
11 * Copyright (c) 2003 ARM Limited.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#ifndef OMAP_ARCH_SMP_H
18#define OMAP_ARCH_SMP_H
19
20#include <asm/hardware/gic.h>
21
22/*
23 * set_event() is used to wake up secondary core from wfe using sev. ROM
24 * code puts the second core into wfe(standby).
25 *
26 */
27#define set_event() __asm__ __volatile__ ("sev" : : : "memory")
28
29/* Needed for secondary core boot */
30extern void omap_secondary_startup(void);
31
32/*
33 * We use Soft IRQ1 as the IPI
34 */
35static inline void smp_cross_call(const struct cpumask *mask)
36{
37 gic_raise_softirq(mask, 1);
38}
39
40/*
41 * Read MPIDR: Multiprocessor affinity register
42 */
43#define hard_smp_processor_id() \
44 ({ \
45 unsigned int cpunum; \
46 __asm__("mrc p15, 0, %0, c0, c0, 5" \
47 : "=r" (cpunum)); \
48 cpunum &= 0x0F; \
49 })
50
51#endif
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
new file mode 100644
index 000000000000..16a1b458d53c
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -0,0 +1,78 @@
1/*
2 * arch/arm/plat-omap/include/mach/sram.h
3 *
4 * Interface for functions that need to be run in internal SRAM
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ARCH_ARM_OMAP_SRAM_H
12#define __ARCH_ARM_OMAP_SRAM_H
13
14extern int __init omap_sram_init(void);
15extern void * omap_sram_push(void * start, unsigned long size);
16extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
17
18extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
19 u32 base_cs, u32 force_unlock);
20extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
21 u32 mem_type);
22extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
23
24extern u32 omap3_configure_core_dpll(
25 u32 m2, u32 unlock_dll, u32 f, u32 inc,
26 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
27 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
28 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
29 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
30extern void omap3_sram_restore_context(void);
31
32/* Do not use these */
33extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
34extern unsigned long omap1_sram_reprogram_clock_sz;
35
36extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
37extern unsigned long omap24xx_sram_reprogram_clock_sz;
38
39extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
40 u32 base_cs, u32 force_unlock);
41extern unsigned long omap242x_sram_ddr_init_sz;
42
43extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
44 int bypass);
45extern unsigned long omap242x_sram_set_prcm_sz;
46
47extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
48 u32 mem_type);
49extern unsigned long omap242x_sram_reprogram_sdrc_sz;
50
51
52extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
53 u32 base_cs, u32 force_unlock);
54extern unsigned long omap243x_sram_ddr_init_sz;
55
56extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
57 int bypass);
58extern unsigned long omap243x_sram_set_prcm_sz;
59
60extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
61 u32 mem_type);
62extern unsigned long omap243x_sram_reprogram_sdrc_sz;
63
64extern u32 omap3_sram_configure_core_dpll(
65 u32 m2, u32 unlock_dll, u32 f, u32 inc,
66 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
67 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
68 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
69 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
70extern unsigned long omap3_sram_configure_core_dpll_sz;
71
72#ifdef CONFIG_PM
73extern void omap_push_sram_idle(void);
74#else
75static inline void omap_push_sram_idle(void) {}
76#endif /* CONFIG_PM */
77
78#endif
diff --git a/arch/arm/plat-omap/include/plat/system.h b/arch/arm/plat-omap/include/plat/system.h
new file mode 100644
index 000000000000..c58a4ef42a45
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/system.h
@@ -0,0 +1,51 @@
1/*
2 * Copied from arch/arm/mach-sa1100/include/mach/system.h
3 * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
4 */
5#ifndef __ASM_ARCH_SYSTEM_H
6#define __ASM_ARCH_SYSTEM_H
7#include <linux/clk.h>
8
9#include <asm/mach-types.h>
10#include <mach/hardware.h>
11
12#include <plat/prcm.h>
13
14#ifndef CONFIG_MACH_VOICEBLUE
15#define voiceblue_reset() do {} while (0)
16#else
17extern void voiceblue_reset(void);
18#endif
19
20static inline void arch_idle(void)
21{
22 cpu_do_idle();
23}
24
25static inline void omap1_arch_reset(char mode)
26{
27 /*
28 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
29 * "Global Software Reset Affects Traffic Controller Frequency".
30 */
31 if (cpu_is_omap5912()) {
32 omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
33 DPLL_CTL);
34 omap_writew(0x8, ARM_RSTCT1);
35 }
36
37 if (machine_is_voiceblue())
38 voiceblue_reset();
39 else
40 omap_writew(1, ARM_RSTCT1);
41}
42
43static inline void arch_reset(char mode, const char *cmd)
44{
45 if (!cpu_class_is_omap2())
46 omap1_arch_reset(mode);
47 else
48 omap_prcm_arch_reset(mode);
49}
50
51#endif
diff --git a/arch/arm/plat-omap/include/plat/tc.h b/arch/arm/plat-omap/include/plat/tc.h
new file mode 100644
index 000000000000..d2fcd789bb9a
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/tc.h
@@ -0,0 +1,106 @@
1/*
2 * arch/arm/plat-omap/include/mach/tc.h
3 *
4 * OMAP Traffic Controller
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 * Author: Imre Deak <imre.deak@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#ifndef __ASM_ARCH_TC_H
25#define __ASM_ARCH_TC_H
26
27#define TCMIF_BASE 0xfffecc00
28#define OMAP_TC_OCPT1_PRIOR (TCMIF_BASE + 0x00)
29#define OMAP_TC_EMIFS_PRIOR (TCMIF_BASE + 0x04)
30#define OMAP_TC_EMIFF_PRIOR (TCMIF_BASE + 0x08)
31#define EMIFS_CONFIG (TCMIF_BASE + 0x0c)
32#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10)
33#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14)
34#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18)
35#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c)
36#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20)
37#define EMIFF_MRS (TCMIF_BASE + 0x24)
38#define TC_TIMEOUT1 (TCMIF_BASE + 0x28)
39#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c)
40#define TC_TIMEOUT3 (TCMIF_BASE + 0x30)
41#define TC_ENDIANISM (TCMIF_BASE + 0x34)
42#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c)
43#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40)
44#define EMIFS_ACS0 (TCMIF_BASE + 0x50)
45#define EMIFS_ACS1 (TCMIF_BASE + 0x54)
46#define EMIFS_ACS2 (TCMIF_BASE + 0x58)
47#define EMIFS_ACS3 (TCMIF_BASE + 0x5c)
48#define OMAP_TC_OCPT2_PRIOR (TCMIF_BASE + 0xd0)
49
50/* external EMIFS chipselect regions */
51#define OMAP_CS0_PHYS 0x00000000
52#define OMAP_CS0_SIZE SZ_64M
53
54#define OMAP_CS1_PHYS 0x04000000
55#define OMAP_CS1_SIZE SZ_64M
56
57#define OMAP_CS1A_PHYS OMAP_CS1_PHYS
58#define OMAP_CS1A_SIZE SZ_32M
59
60#define OMAP_CS1B_PHYS (OMAP_CS1A_PHYS + OMAP_CS1A_SIZE)
61#define OMAP_CS1B_SIZE SZ_32M
62
63#define OMAP_CS2_PHYS 0x08000000
64#define OMAP_CS2_SIZE SZ_64M
65
66#define OMAP_CS2A_PHYS OMAP_CS2_PHYS
67#define OMAP_CS2A_SIZE SZ_32M
68
69#define OMAP_CS2B_PHYS (OMAP_CS2A_PHYS + OMAP_CS2A_SIZE)
70#define OMAP_CS2B_SIZE SZ_32M
71
72#define OMAP_CS3_PHYS 0x0c000000
73#define OMAP_CS3_SIZE SZ_64M
74
75#ifndef __ASSEMBLER__
76
77/* EMIF Slow Interface Configuration Register */
78#define OMAP_EMIFS_CONFIG_FR (1 << 4)
79#define OMAP_EMIFS_CONFIG_PDE (1 << 3)
80#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2)
81#define OMAP_EMIFS_CONFIG_BM (1 << 1)
82#define OMAP_EMIFS_CONFIG_WP (1 << 0)
83
84#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n)))
85#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n)))
86
87/* Almost all documentation for chip and board memory maps assumes
88 * BM is clear. Most devel boards have a switch to control booting
89 * from NOR flash (using external chipselect 3) rather than mask ROM,
90 * which uses BM to interchange the physical CS0 and CS3 addresses.
91 */
92static inline u32 omap_cs0_phys(void)
93{
94 return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
95 ? OMAP_CS3_PHYS : 0;
96}
97
98static inline u32 omap_cs3_phys(void)
99{
100 return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
101 ? 0 : OMAP_CS3_PHYS;
102}
103
104#endif /* __ASSEMBLER__ */
105
106#endif /* __ASM_ARCH_TC_H */
diff --git a/arch/arm/plat-omap/include/plat/timer-gp.h b/arch/arm/plat-omap/include/plat/timer-gp.h
new file mode 100644
index 000000000000..c88d346b59d9
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/timer-gp.h
@@ -0,0 +1,17 @@
1/*
2 * OMAP2/3 GPTIMER support.headers
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
12#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
13
14int __init omap2_gp_clockevent_set_gptimer(u8 id);
15
16#endif
17
diff --git a/arch/arm/plat-omap/include/plat/timex.h b/arch/arm/plat-omap/include/plat/timex.h
new file mode 100644
index 000000000000..6d35767bc48f
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/timex.h
@@ -0,0 +1,41 @@
1/*
2 * arch/arm/plat-omap/include/mach/timex.h
3 *
4 * Copyright (C) 2000 RidgeRun, Inc.
5 * Author: Greg Lonnon <glonnon@ridgerun.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
29#define __ASM_ARCH_OMAP_TIMEX_H
30
31/*
32 * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer,
33 * and that's why the CLOCK_TICK_RATE is not 32768.
34 */
35#ifdef CONFIG_OMAP_32K_TIMER
36#define CLOCK_TICK_RATE (CONFIG_OMAP_32K_TIMER_HZ)
37#else
38#define CLOCK_TICK_RATE (HZ * 100000UL)
39#endif
40
41#endif /* __ASM_ARCH_OMAP_TIMEX_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
new file mode 100644
index 000000000000..e22f57564b59
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -0,0 +1,84 @@
1/*
2 * arch/arm/plat-omap/include/mach/uncompress.h
3 *
4 * Serial port stubs for kernel decompress status messages
5 *
6 * Initially based on:
7 * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
8 * Copyright (C) 2000 RidgeRun, Inc.
9 * Author: Greg Lonnon <glonnon@ridgerun.com>
10 *
11 * Rewritten by:
12 * Author: <source@mvista.com>
13 * 2004 (c) MontaVista Software, Inc.
14 *
15 * This file is licensed under the terms of the GNU General Public License
16 * version 2. This program is licensed "as is" without any warranty of any
17 * kind, whether express or implied.
18 */
19
20#include <linux/types.h>
21#include <linux/serial_reg.h>
22#include <plat/serial.h>
23
24unsigned int system_rev;
25
26#define UART_OMAP_MDR1 0x08 /* mode definition register */
27#define OMAP_ID_730 0x355F
28#define OMAP_ID_850 0x362C
29#define ID_MASK 0x7fff
30#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
31#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
32
33static void putc(int c)
34{
35 volatile u8 * uart = 0;
36 int shift = 2;
37
38#ifdef CONFIG_MACH_OMAP_PALMTE
39 return;
40#endif
41
42#ifdef CONFIG_ARCH_OMAP
43#ifdef CONFIG_OMAP_LL_DEBUG_UART3
44 uart = (volatile u8 *)(OMAP_UART3_BASE);
45#elif defined(CONFIG_OMAP_LL_DEBUG_UART2)
46 uart = (volatile u8 *)(OMAP_UART2_BASE);
47#else
48 uart = (volatile u8 *)(OMAP_UART1_BASE);
49#endif
50
51#ifdef CONFIG_ARCH_OMAP1
52 /* Determine which serial port to use */
53 do {
54 /* MMU is not on, so cpu_is_omapXXXX() won't work here */
55 unsigned int omap_id = omap_get_id();
56
57 if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850)
58 shift = 0;
59
60 if (check_port(uart, shift))
61 break;
62 /* Silent boot if no serial ports are enabled. */
63 return;
64 } while (0);
65#endif /* CONFIG_ARCH_OMAP1 */
66#endif
67
68 /*
69 * Now, xmit each character
70 */
71 while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
72 barrier();
73 uart[UART_TX << shift] = c;
74}
75
76static inline void flush(void)
77{
78}
79
80/*
81 * nothing to do
82 */
83#define arch_decomp_setup()
84#define arch_decomp_wdog()
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
new file mode 100644
index 000000000000..33e72ca125d7
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -0,0 +1,145 @@
1// include/asm-arm/mach-omap/usb.h
2
3#ifndef __ASM_ARCH_OMAP_USB_H
4#define __ASM_ARCH_OMAP_USB_H
5
6#include <plat/board.h>
7
8/*-------------------------------------------------------------------------*/
9
10#define OMAP1_OTG_BASE 0xfffb0400
11#define OMAP1_UDC_BASE 0xfffb4000
12#define OMAP1_OHCI_BASE 0xfffba000
13
14#define OMAP2_OHCI_BASE 0x4805e000
15#define OMAP2_UDC_BASE 0x4805e200
16#define OMAP2_OTG_BASE 0x4805e300
17
18#ifdef CONFIG_ARCH_OMAP1
19
20#define OTG_BASE OMAP1_OTG_BASE
21#define UDC_BASE OMAP1_UDC_BASE
22#define OMAP_OHCI_BASE OMAP1_OHCI_BASE
23
24#else
25
26#define OTG_BASE OMAP2_OTG_BASE
27#define UDC_BASE OMAP2_UDC_BASE
28#define OMAP_OHCI_BASE OMAP2_OHCI_BASE
29
30extern void usb_musb_init(void);
31
32#endif
33
34void omap_usb_init(struct omap_usb_config *pdata);
35
36/*-------------------------------------------------------------------------*/
37
38/*
39 * OTG and transceiver registers, for OMAPs starting with ARM926
40 */
41#define OTG_REV (OTG_BASE + 0x00)
42#define OTG_SYSCON_1 (OTG_BASE + 0x04)
43# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
44# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
45# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
46# define OTG_IDLE_EN (1 << 15)
47# define HST_IDLE_EN (1 << 14)
48# define DEV_IDLE_EN (1 << 13)
49# define OTG_RESET_DONE (1 << 2)
50# define OTG_SOFT_RESET (1 << 1)
51#define OTG_SYSCON_2 (OTG_BASE + 0x08)
52# define OTG_EN (1 << 31)
53# define USBX_SYNCHRO (1 << 30)
54# define OTG_MST16 (1 << 29)
55# define SRP_GPDATA (1 << 28)
56# define SRP_GPDVBUS (1 << 27)
57# define SRP_GPUVBUS(w) (((w)>>24)&0x07)
58# define A_WAIT_VRISE(w) (((w)>>20)&0x07)
59# define B_ASE_BRST(w) (((w)>>16)&0x07)
60# define SRP_DPW (1 << 14)
61# define SRP_DATA (1 << 13)
62# define SRP_VBUS (1 << 12)
63# define OTG_PADEN (1 << 10)
64# define HMC_PADEN (1 << 9)
65# define UHOST_EN (1 << 8)
66# define HMC_TLLSPEED (1 << 7)
67# define HMC_TLLATTACH (1 << 6)
68# define OTG_HMC(w) (((w)>>0)&0x3f)
69#define OTG_CTRL (OTG_BASE + 0x0c)
70# define OTG_USB2_EN (1 << 29)
71# define OTG_USB2_DP (1 << 28)
72# define OTG_USB2_DM (1 << 27)
73# define OTG_USB1_EN (1 << 26)
74# define OTG_USB1_DP (1 << 25)
75# define OTG_USB1_DM (1 << 24)
76# define OTG_USB0_EN (1 << 23)
77# define OTG_USB0_DP (1 << 22)
78# define OTG_USB0_DM (1 << 21)
79# define OTG_ASESSVLD (1 << 20)
80# define OTG_BSESSEND (1 << 19)
81# define OTG_BSESSVLD (1 << 18)
82# define OTG_VBUSVLD (1 << 17)
83# define OTG_ID (1 << 16)
84# define OTG_DRIVER_SEL (1 << 15)
85# define OTG_A_SETB_HNPEN (1 << 12)
86# define OTG_A_BUSREQ (1 << 11)
87# define OTG_B_HNPEN (1 << 9)
88# define OTG_B_BUSREQ (1 << 8)
89# define OTG_BUSDROP (1 << 7)
90# define OTG_PULLDOWN (1 << 5)
91# define OTG_PULLUP (1 << 4)
92# define OTG_DRV_VBUS (1 << 3)
93# define OTG_PD_VBUS (1 << 2)
94# define OTG_PU_VBUS (1 << 1)
95# define OTG_PU_ID (1 << 0)
96#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
97# define DRIVER_SWITCH (1 << 15)
98# define A_VBUS_ERR (1 << 13)
99# define A_REQ_TMROUT (1 << 12)
100# define A_SRP_DETECT (1 << 11)
101# define B_HNP_FAIL (1 << 10)
102# define B_SRP_TMROUT (1 << 9)
103# define B_SRP_DONE (1 << 8)
104# define B_SRP_STARTED (1 << 7)
105# define OPRT_CHG (1 << 0)
106#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
107 // same bits as in IRQ_EN
108#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
109# define OTGVPD (1 << 14)
110# define OTGVPU (1 << 13)
111# define OTGPUID (1 << 12)
112# define USB2VDR (1 << 10)
113# define USB2PDEN (1 << 9)
114# define USB2PUEN (1 << 8)
115# define USB1VDR (1 << 6)
116# define USB1PDEN (1 << 5)
117# define USB1PUEN (1 << 4)
118# define USB0VDR (1 << 2)
119# define USB0PDEN (1 << 1)
120# define USB0PUEN (1 << 0)
121#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
122#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
123
124/*-------------------------------------------------------------------------*/
125
126/* OMAP1 */
127#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
128# define CONF_USB2_UNI_R (1 << 8)
129# define CONF_USB1_UNI_R (1 << 7)
130# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
131# define CONF_USB0_ISOLATE_R (1 << 3)
132# define CONF_USB_PWRDN_DM_R (1 << 2)
133# define CONF_USB_PWRDN_DP_R (1 << 1)
134
135/* OMAP2 */
136# define USB_UNIDIR 0x0
137# define USB_UNIDIR_TLL 0x1
138# define USB_BIDIR 0x2
139# define USB_BIDIR_TLL 0x3
140# define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
141# define USBT2TLL5PI (1 << 17)
142# define USB0PUENACTLOI (1 << 16)
143# define USBSTANDBYCTRL (1 << 15)
144
145#endif /* __ASM_ARCH_OMAP_USB_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 09:14:20 -0500