diff options
Diffstat (limited to 'arch/arm/plat-omap/include/plat/irqs.h')
| -rw-r--r-- | arch/arm/plat-omap/include/plat/irqs.h | 92 |
1 files changed, 3 insertions, 89 deletions
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index e8205c13a27a..b65088a869e9 100644 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h | |||
| @@ -28,6 +28,9 @@ | |||
| 28 | #ifndef __ASM_ARCH_OMAP15XX_IRQS_H | 28 | #ifndef __ASM_ARCH_OMAP15XX_IRQS_H |
| 29 | #define __ASM_ARCH_OMAP15XX_IRQS_H | 29 | #define __ASM_ARCH_OMAP15XX_IRQS_H |
| 30 | 30 | ||
| 31 | /* All OMAP4 specific defines are moved to irqs-44xx.h */ | ||
| 32 | #include "irqs-44xx.h" | ||
| 33 | |||
| 31 | /* | 34 | /* |
| 32 | * IRQ numbers for interrupt handler 1 | 35 | * IRQ numbers for interrupt handler 1 |
| 33 | * | 36 | * |
| @@ -355,95 +358,6 @@ | |||
| 355 | #define INT_35XX_CCDC_VD1_IRQ 92 | 358 | #define INT_35XX_CCDC_VD1_IRQ 92 |
| 356 | #define INT_35XX_CCDC_VD2_IRQ 93 | 359 | #define INT_35XX_CCDC_VD2_IRQ 93 |
| 357 | 360 | ||
| 358 | #define IRQ_GIC_START 32 | ||
| 359 | #define INT_44XX_LOCALTIMER_IRQ 29 | ||
| 360 | #define INT_44XX_LOCALWDT_IRQ 30 | ||
| 361 | |||
| 362 | #define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START) | ||
| 363 | #define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START) | ||
| 364 | #define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START) | ||
| 365 | #define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START) | ||
| 366 | #define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START) | ||
| 367 | #define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START) | ||
| 368 | #define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START) | ||
| 369 | #define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START) | ||
| 370 | #define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START) | ||
| 371 | #define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START) | ||
| 372 | #define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START) | ||
| 373 | #define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START) | ||
| 374 | #define INT_44XX_DSP_MMU (28 + IRQ_GIC_START) | ||
| 375 | #define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START) | ||
| 376 | #define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START) | ||
| 377 | #define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START) | ||
| 378 | #define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START) | ||
| 379 | #define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START) | ||
| 380 | #define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START) | ||
| 381 | #define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START) | ||
| 382 | #define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START) | ||
| 383 | #define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START) | ||
| 384 | #define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START) | ||
| 385 | #define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START) | ||
| 386 | #define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START) | ||
| 387 | #define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START) | ||
| 388 | #define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START) | ||
| 389 | #define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START) | ||
| 390 | #define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START) | ||
| 391 | #define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START) | ||
| 392 | #define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START) | ||
| 393 | #define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START) | ||
| 394 | #define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START) | ||
| 395 | #define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START) | ||
| 396 | #define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START) | ||
| 397 | #define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START) | ||
| 398 | #define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START) | ||
| 399 | #define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START) | ||
| 400 | #define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START) | ||
| 401 | #define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START) | ||
| 402 | #define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START) | ||
| 403 | #define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START) | ||
| 404 | #define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START) | ||
| 405 | #define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START) | ||
| 406 | #define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START) | ||
| 407 | #define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START) | ||
| 408 | #define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START) | ||
| 409 | #define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START) | ||
| 410 | #define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START) | ||
| 411 | #define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START) | ||
| 412 | #define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START) | ||
| 413 | |||
| 414 | #define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START) | ||
| 415 | #define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START) | ||
| 416 | #define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START) | ||
| 417 | #define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START) | ||
| 418 | #define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START) | ||
| 419 | #define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START) | ||
| 420 | #define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START) | ||
| 421 | |||
| 422 | #define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START) | ||
| 423 | #define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START) | ||
| 424 | #define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START) | ||
| 425 | #define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START) | ||
| 426 | #define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START) | ||
| 427 | #define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START) | ||
| 428 | #define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START) | ||
| 429 | #define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START) | ||
| 430 | #define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START) | ||
| 431 | #define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START) | ||
| 432 | #define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START) | ||
| 433 | #define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START) | ||
| 434 | #define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START) | ||
| 435 | #define INT_44XX_MMC5_IRQ (59 + IRQ_GIC_START) | ||
| 436 | #define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START) | ||
| 437 | #define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START) | ||
| 438 | #define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START) | ||
| 439 | #define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START) | ||
| 440 | #define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START) | ||
| 441 | #define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START) | ||
| 442 | #define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START) | ||
| 443 | #define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START) | ||
| 444 | #define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START) | ||
| 445 | #define INT_44XX_MCPDM_IRQ (112 + IRQ_GIC_START) | ||
| 446 | |||
| 447 | /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and | 361 | /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and |
| 448 | * 16 MPUIO lines */ | 362 | * 16 MPUIO lines */ |
| 449 | #define OMAP_MAX_GPIO_LINES 192 | 363 | #define OMAP_MAX_GPIO_LINES 192 |