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-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h487
1 files changed, 487 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
new file mode 100644
index 000000000000..6a6d0281e1d5
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+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -0,0 +1,487 @@
1/*
2 * arch/arm/plat-omap/include/mach/irqs.h
3 *
4 * Copyright (C) Greg Lonnon 2001
5 * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
25 * are different.
26 */
27
28#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
29#define __ASM_ARCH_OMAP15XX_IRQS_H
30
31/*
32 * IRQ numbers for interrupt handler 1
33 *
34 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
35 *
36 */
37#define INT_CAMERA 1
38#define INT_FIQ 3
39#define INT_RTDX 6
40#define INT_DSP_MMU_ABORT 7
41#define INT_HOST 8
42#define INT_ABORT 9
43#define INT_BRIDGE_PRIV 13
44#define INT_GPIO_BANK1 14
45#define INT_UART3 15
46#define INT_TIMER3 16
47#define INT_DMA_CH0_6 19
48#define INT_DMA_CH1_7 20
49#define INT_DMA_CH2_8 21
50#define INT_DMA_CH3 22
51#define INT_DMA_CH4 23
52#define INT_DMA_CH5 24
53#define INT_DMA_LCD 25
54#define INT_TIMER1 26
55#define INT_WD_TIMER 27
56#define INT_BRIDGE_PUB 28
57#define INT_TIMER2 30
58#define INT_LCD_CTRL 31
59
60/*
61 * OMAP-1510 specific IRQ numbers for interrupt handler 1
62 */
63#define INT_1510_IH2_IRQ 0
64#define INT_1510_RES2 2
65#define INT_1510_SPI_TX 4
66#define INT_1510_SPI_RX 5
67#define INT_1510_DSP_MAILBOX1 10
68#define INT_1510_DSP_MAILBOX2 11
69#define INT_1510_RES12 12
70#define INT_1510_LB_MMU 17
71#define INT_1510_RES18 18
72#define INT_1510_LOCAL_BUS 29
73
74/*
75 * OMAP-1610 specific IRQ numbers for interrupt handler 1
76 */
77#define INT_1610_IH2_IRQ 0
78#define INT_1610_IH2_FIQ 2
79#define INT_1610_McBSP2_TX 4
80#define INT_1610_McBSP2_RX 5
81#define INT_1610_DSP_MAILBOX1 10
82#define INT_1610_DSP_MAILBOX2 11
83#define INT_1610_LCD_LINE 12
84#define INT_1610_GPTIMER1 17
85#define INT_1610_GPTIMER2 18
86#define INT_1610_SSR_FIFO_0 29
87
88/*
89 * OMAP-7xx specific IRQ numbers for interrupt handler 1
90 */
91#define INT_7XX_IH2_FIQ 0
92#define INT_7XX_IH2_IRQ 1
93#define INT_7XX_USB_NON_ISO 2
94#define INT_7XX_USB_ISO 3
95#define INT_7XX_ICR 4
96#define INT_7XX_EAC 5
97#define INT_7XX_GPIO_BANK1 6
98#define INT_7XX_GPIO_BANK2 7
99#define INT_7XX_GPIO_BANK3 8
100#define INT_7XX_McBSP2TX 10
101#define INT_7XX_McBSP2RX 11
102#define INT_7XX_McBSP2RX_OVF 12
103#define INT_7XX_LCD_LINE 14
104#define INT_7XX_GSM_PROTECT 15
105#define INT_7XX_TIMER3 16
106#define INT_7XX_GPIO_BANK5 17
107#define INT_7XX_GPIO_BANK6 18
108#define INT_7XX_SPGIO_WR 29
109
110/*
111 * IRQ numbers for interrupt handler 2
112 *
113 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
114 */
115#define IH2_BASE 32
116
117#define INT_KEYBOARD (1 + IH2_BASE)
118#define INT_uWireTX (2 + IH2_BASE)
119#define INT_uWireRX (3 + IH2_BASE)
120#define INT_I2C (4 + IH2_BASE)
121#define INT_MPUIO (5 + IH2_BASE)
122#define INT_USB_HHC_1 (6 + IH2_BASE)
123#define INT_McBSP3TX (10 + IH2_BASE)
124#define INT_McBSP3RX (11 + IH2_BASE)
125#define INT_McBSP1TX (12 + IH2_BASE)
126#define INT_McBSP1RX (13 + IH2_BASE)
127#define INT_UART1 (14 + IH2_BASE)
128#define INT_UART2 (15 + IH2_BASE)
129#define INT_BT_MCSI1TX (16 + IH2_BASE)
130#define INT_BT_MCSI1RX (17 + IH2_BASE)
131#define INT_SOSSI_MATCH (19 + IH2_BASE)
132#define INT_USB_W2FC (20 + IH2_BASE)
133#define INT_1WIRE (21 + IH2_BASE)
134#define INT_OS_TIMER (22 + IH2_BASE)
135#define INT_MMC (23 + IH2_BASE)
136#define INT_GAUGE_32K (24 + IH2_BASE)
137#define INT_RTC_TIMER (25 + IH2_BASE)
138#define INT_RTC_ALARM (26 + IH2_BASE)
139#define INT_MEM_STICK (27 + IH2_BASE)
140
141/*
142 * OMAP-1510 specific IRQ numbers for interrupt handler 2
143 */
144#define INT_1510_DSP_MMU (28 + IH2_BASE)
145#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
146
147/*
148 * OMAP-1610 specific IRQ numbers for interrupt handler 2
149 */
150#define INT_1610_FAC (0 + IH2_BASE)
151#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
152#define INT_1610_USB_OTG (8 + IH2_BASE)
153#define INT_1610_SoSSI (9 + IH2_BASE)
154#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
155#define INT_1610_DSP_MMU (28 + IH2_BASE)
156#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
157#define INT_1610_STI (32 + IH2_BASE)
158#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
159#define INT_1610_GPTIMER3 (34 + IH2_BASE)
160#define INT_1610_GPTIMER4 (35 + IH2_BASE)
161#define INT_1610_GPTIMER5 (36 + IH2_BASE)
162#define INT_1610_GPTIMER6 (37 + IH2_BASE)
163#define INT_1610_GPTIMER7 (38 + IH2_BASE)
164#define INT_1610_GPTIMER8 (39 + IH2_BASE)
165#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
166#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
167#define INT_1610_MMC2 (42 + IH2_BASE)
168#define INT_1610_CF (43 + IH2_BASE)
169#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
170#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
171#define INT_1610_SPI (49 + IH2_BASE)
172#define INT_1610_DMA_CH6 (53 + IH2_BASE)
173#define INT_1610_DMA_CH7 (54 + IH2_BASE)
174#define INT_1610_DMA_CH8 (55 + IH2_BASE)
175#define INT_1610_DMA_CH9 (56 + IH2_BASE)
176#define INT_1610_DMA_CH10 (57 + IH2_BASE)
177#define INT_1610_DMA_CH11 (58 + IH2_BASE)
178#define INT_1610_DMA_CH12 (59 + IH2_BASE)
179#define INT_1610_DMA_CH13 (60 + IH2_BASE)
180#define INT_1610_DMA_CH14 (61 + IH2_BASE)
181#define INT_1610_DMA_CH15 (62 + IH2_BASE)
182#define INT_1610_NAND (63 + IH2_BASE)
183#define INT_1610_SHA1MD5 (91 + IH2_BASE)
184
185/*
186 * OMAP-7xx specific IRQ numbers for interrupt handler 2
187 */
188#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
189#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
190#define INT_7XX_CFCD (2 + IH2_BASE)
191#define INT_7XX_CFIREQ (3 + IH2_BASE)
192#define INT_7XX_I2C (4 + IH2_BASE)
193#define INT_7XX_PCC (5 + IH2_BASE)
194#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
195#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
196#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
197#define INT_7XX_VLYNQ (9 + IH2_BASE)
198#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
199#define INT_7XX_McBSP1TX (11 + IH2_BASE)
200#define INT_7XX_McBSP1RX (12 + IH2_BASE)
201#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
202#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
203#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
204#define INT_7XX_MCSI (16 + IH2_BASE)
205#define INT_7XX_uWireTX (17 + IH2_BASE)
206#define INT_7XX_uWireRX (18 + IH2_BASE)
207#define INT_7XX_SMC_CD (19 + IH2_BASE)
208#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
209#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
210#define INT_7XX_TIMER32K (22 + IH2_BASE)
211#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
212#define INT_7XX_UPLD (24 + IH2_BASE)
213#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
214#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
215#define INT_7XX_USB_GENI (29 + IH2_BASE)
216#define INT_7XX_USB_OTG (30 + IH2_BASE)
217#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
218#define INT_7XX_RNG (32 + IH2_BASE)
219#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
220#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
221#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
222#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
223#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
224#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
225#define INT_7XX_MPUIO (39 + IH2_BASE)
226#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
227#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
228#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
229#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
230#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
231#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
232#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
233#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
234#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
235#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
236#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
237#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
238#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
239#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
240#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
241#define INT_7XX_NAND (63 + IH2_BASE)
242
243#define INT_24XX_SYS_NIRQ 7
244#define INT_24XX_SDMA_IRQ0 12
245#define INT_24XX_SDMA_IRQ1 13
246#define INT_24XX_SDMA_IRQ2 14
247#define INT_24XX_SDMA_IRQ3 15
248#define INT_24XX_CAM_IRQ 24
249#define INT_24XX_DSS_IRQ 25
250#define INT_24XX_MAIL_U0_MPU 26
251#define INT_24XX_DSP_UMA 27
252#define INT_24XX_DSP_MMU 28
253#define INT_24XX_GPIO_BANK1 29
254#define INT_24XX_GPIO_BANK2 30
255#define INT_24XX_GPIO_BANK3 31
256#define INT_24XX_GPIO_BANK4 32
257#define INT_24XX_GPIO_BANK5 33
258#define INT_24XX_MAIL_U3_MPU 34
259#define INT_24XX_GPTIMER1 37
260#define INT_24XX_GPTIMER2 38
261#define INT_24XX_GPTIMER3 39
262#define INT_24XX_GPTIMER4 40
263#define INT_24XX_GPTIMER5 41
264#define INT_24XX_GPTIMER6 42
265#define INT_24XX_GPTIMER7 43
266#define INT_24XX_GPTIMER8 44
267#define INT_24XX_GPTIMER9 45
268#define INT_24XX_GPTIMER10 46
269#define INT_24XX_GPTIMER11 47
270#define INT_24XX_GPTIMER12 48
271#define INT_24XX_SHA1MD5 51
272#define INT_24XX_MCBSP4_IRQ_TX 54
273#define INT_24XX_MCBSP4_IRQ_RX 55
274#define INT_24XX_I2C1_IRQ 56
275#define INT_24XX_I2C2_IRQ 57
276#define INT_24XX_HDQ_IRQ 58
277#define INT_24XX_MCBSP1_IRQ_TX 59
278#define INT_24XX_MCBSP1_IRQ_RX 60
279#define INT_24XX_MCBSP2_IRQ_TX 62
280#define INT_24XX_MCBSP2_IRQ_RX 63
281#define INT_24XX_SPI1_IRQ 65
282#define INT_24XX_SPI2_IRQ 66
283#define INT_24XX_UART1_IRQ 72
284#define INT_24XX_UART2_IRQ 73
285#define INT_24XX_UART3_IRQ 74
286#define INT_24XX_USB_IRQ_GEN 75
287#define INT_24XX_USB_IRQ_NISO 76
288#define INT_24XX_USB_IRQ_ISO 77
289#define INT_24XX_USB_IRQ_HGEN 78
290#define INT_24XX_USB_IRQ_HSOF 79
291#define INT_24XX_USB_IRQ_OTG 80
292#define INT_24XX_MCBSP5_IRQ_TX 81
293#define INT_24XX_MCBSP5_IRQ_RX 82
294#define INT_24XX_MMC_IRQ 83
295#define INT_24XX_MMC2_IRQ 86
296#define INT_24XX_MCBSP3_IRQ_TX 89
297#define INT_24XX_MCBSP3_IRQ_RX 90
298#define INT_24XX_SPI3_IRQ 91
299
300#define INT_243X_MCBSP2_IRQ 16
301#define INT_243X_MCBSP3_IRQ 17
302#define INT_243X_MCBSP4_IRQ 18
303#define INT_243X_MCBSP5_IRQ 19
304#define INT_243X_MCBSP1_IRQ 64
305#define INT_243X_HS_USB_MC 92
306#define INT_243X_HS_USB_DMA 93
307#define INT_243X_CARKIT_IRQ 94
308
309#define INT_34XX_BENCH_MPU_EMUL 3
310#define INT_34XX_ST_MCBSP2_IRQ 4
311#define INT_34XX_ST_MCBSP3_IRQ 5
312#define INT_34XX_SSM_ABORT_IRQ 6
313#define INT_34XX_SYS_NIRQ 7
314#define INT_34XX_D2D_FW_IRQ 8
315#define INT_34XX_PRCM_MPU_IRQ 11
316#define INT_34XX_MCBSP1_IRQ 16
317#define INT_34XX_MCBSP2_IRQ 17
318#define INT_34XX_MCBSP3_IRQ 22
319#define INT_34XX_MCBSP4_IRQ 23
320#define INT_34XX_CAM_IRQ 24
321#define INT_34XX_MCBSP5_IRQ 27
322#define INT_34XX_GPIO_BANK1 29
323#define INT_34XX_GPIO_BANK2 30
324#define INT_34XX_GPIO_BANK3 31
325#define INT_34XX_GPIO_BANK4 32
326#define INT_34XX_GPIO_BANK5 33
327#define INT_34XX_GPIO_BANK6 34
328#define INT_34XX_USIM_IRQ 35
329#define INT_34XX_WDT3_IRQ 36
330#define INT_34XX_SPI4_IRQ 48
331#define INT_34XX_SHA1MD52_IRQ 49
332#define INT_34XX_FPKA_READY_IRQ 50
333#define INT_34XX_SHA1MD51_IRQ 51
334#define INT_34XX_RNG_IRQ 52
335#define INT_34XX_I2C3_IRQ 61
336#define INT_34XX_FPKA_ERROR_IRQ 64
337#define INT_34XX_PBIAS_IRQ 75
338#define INT_34XX_OHCI_IRQ 76
339#define INT_34XX_EHCI_IRQ 77
340#define INT_34XX_TLL_IRQ 78
341#define INT_34XX_PARTHASH_IRQ 79
342#define INT_34XX_MMC3_IRQ 94
343#define INT_34XX_GPT12_IRQ 95
344
345#define INT_34XX_BENCH_MPU_EMUL 3
346
347
348#define IRQ_GIC_START 32
349#define INT_44XX_LOCALTIMER_IRQ 29
350#define INT_44XX_LOCALWDT_IRQ 30
351
352#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
353#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START)
354#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START)
355#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START)
356#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START)
357#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START)
358#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START)
359#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START)
360#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START)
361#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START)
362#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START)
363#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START)
364#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START)
365#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START)
366#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START)
367#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START)
368#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START)
369#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START)
370#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START)
371#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START)
372#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START)
373#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START)
374#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START)
375#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START)
376#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START)
377#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START)
378#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START)
379#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START)
380#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START)
381#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START)
382#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START)
383#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START)
384#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START)
385#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START)
386#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START)
387#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START)
388#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START)
389#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START)
390#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START)
391#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START)
392#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START)
393#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START)
394#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START)
395#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START)
396#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START)
397#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START)
398#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START)
399#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START)
400#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START)
401#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START)
402#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START)
403
404#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START)
405#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START)
406#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START)
407#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START)
408#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START)
409#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START)
410#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START)
411
412#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START)
413#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START)
414#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START)
415#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START)
416#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START)
417#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START)
418#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START)
419#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START)
420#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START)
421#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START)
422#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
423#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START)
424#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START)
425#define INT_44XX_MMC5_IRQ (59 + IRQ_GIC_START)
426#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START)
427#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
428#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START)
429#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START)
430#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START)
431#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START)
432#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START)
433#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START)
434#define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START)
435
436
437/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
438 * 16 MPUIO lines */
439#define OMAP_MAX_GPIO_LINES 192
440#define IH_GPIO_BASE (128 + IH2_BASE)
441#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
442#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
443
444/* External FPGA handles interrupts on Innovator boards */
445#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
446#ifdef CONFIG_MACH_OMAP_INNOVATOR
447#define OMAP_FPGA_NR_IRQS 24
448#else
449#define OMAP_FPGA_NR_IRQS 0
450#endif
451#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
452
453/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
454#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
455#ifdef CONFIG_TWL4030_CORE
456#define TWL4030_BASE_NR_IRQS 8
457#define TWL4030_PWR_NR_IRQS 8
458#else
459#define TWL4030_BASE_NR_IRQS 0
460#define TWL4030_PWR_NR_IRQS 0
461#endif
462#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
463#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
464#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
465
466/* External TWL4030 gpio interrupts are optional */
467#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
468#ifdef CONFIG_GPIO_TWL4030
469#define TWL4030_GPIO_NR_IRQS 18
470#else
471#define TWL4030_GPIO_NR_IRQS 0
472#endif
473#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
474
475/* Total number of interrupts depends on the enabled blocks above */
476#define NR_IRQS TWL4030_GPIO_IRQ_END
477
478#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
479
480#ifndef __ASSEMBLY__
481extern void omap_init_irq(void);
482extern int omap_irq_pending(void);
483#endif
484
485#include <mach/hardware.h>
486
487#endif