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-rw-r--r--arch/arm/plat-omap/include/plat/io.h174
1 files changed, 0 insertions, 174 deletions
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index e5e8e08f62f5..93261d9098f6 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -60,180 +60,6 @@
60#define IOMEM(x) ((void __force __iomem *)(x)) 60#define IOMEM(x) ((void __force __iomem *)(x))
61#endif 61#endif
62 62
63#define OMAP2_L3_IO_OFFSET 0x90000000
64#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
65
66
67#define OMAP2_L4_IO_OFFSET 0xb2000000
68#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
69
70#define OMAP4_L3_IO_OFFSET 0xb4000000
71#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
72
73#define AM33XX_L4_WK_IO_OFFSET 0xb5000000
74#define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
75
76#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
77#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
78
79#define OMAP4_GPMC_IO_OFFSET 0xa9000000
80#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
81
82#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
83#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
84
85/*
86 * ----------------------------------------------------------------------------
87 * Omap2 specific IO mapping
88 * ----------------------------------------------------------------------------
89 */
90
91/* We map both L3 and L4 on OMAP2 */
92#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
93#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
94#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
95#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
96#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
97#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
98
99#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
100#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
101#define L4_WK_243X_SIZE SZ_1M
102#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE
103#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
104 /* 0x6e000000 --> 0xfe000000 */
105#define OMAP243X_GPMC_SIZE SZ_1M
106#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
107 /* 0x6D000000 --> 0xfd000000 */
108#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
109#define OMAP243X_SDRC_SIZE SZ_1M
110#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
111 /* 0x6c000000 --> 0xfc000000 */
112#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
113#define OMAP243X_SMS_SIZE SZ_1M
114
115/* 2420 IVA */
116#define DSP_MEM_2420_PHYS OMAP2420_DSP_MEM_BASE
117 /* 0x58000000 --> 0xfc100000 */
118#define DSP_MEM_2420_VIRT 0xfc100000
119#define DSP_MEM_2420_SIZE 0x28000
120#define DSP_IPI_2420_PHYS OMAP2420_DSP_IPI_BASE
121 /* 0x59000000 --> 0xfc128000 */
122#define DSP_IPI_2420_VIRT 0xfc128000
123#define DSP_IPI_2420_SIZE SZ_4K
124#define DSP_MMU_2420_PHYS OMAP2420_DSP_MMU_BASE
125 /* 0x5a000000 --> 0xfc129000 */
126#define DSP_MMU_2420_VIRT 0xfc129000
127#define DSP_MMU_2420_SIZE SZ_4K
128
129/* 2430 IVA2.1 - currently unmapped */
130
131/*
132 * ----------------------------------------------------------------------------
133 * Omap3 specific IO mapping
134 * ----------------------------------------------------------------------------
135 */
136
137/* We map both L3 and L4 on OMAP3 */
138#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */
139#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
140#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
141
142#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */
143#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
144#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
145
146/*
147 * ----------------------------------------------------------------------------
148 * AM33XX specific IO mapping
149 * ----------------------------------------------------------------------------
150 */
151#define L4_WK_AM33XX_PHYS L4_WK_AM33XX_BASE
152#define L4_WK_AM33XX_VIRT (L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
153#define L4_WK_AM33XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
154
155/*
156 * Need to look at the Size 4M for L4.
157 * VPOM3430 was not working for Int controller
158 */
159
160#define L4_PER_34XX_PHYS L4_PER_34XX_BASE
161 /* 0x49000000 --> 0xfb000000 */
162#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
163#define L4_PER_34XX_SIZE SZ_1M
164
165#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE
166 /* 0x54000000 --> 0xfe800000 */
167#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
168#define L4_EMU_34XX_SIZE SZ_8M
169
170#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE
171 /* 0x6e000000 --> 0xfe000000 */
172#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
173#define OMAP34XX_GPMC_SIZE SZ_1M
174
175#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE
176 /* 0x6c000000 --> 0xfc000000 */
177#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
178#define OMAP343X_SMS_SIZE SZ_1M
179
180#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE
181 /* 0x6D000000 --> 0xfd000000 */
182#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
183#define OMAP343X_SDRC_SIZE SZ_1M
184
185/* 3430 IVA - currently unmapped */
186
187/*
188 * ----------------------------------------------------------------------------
189 * Omap4 specific IO mapping
190 * ----------------------------------------------------------------------------
191 */
192
193/* We map both L3 and L4 on OMAP4 */
194#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */
195#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
196#define L3_44XX_SIZE SZ_1M
197
198#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */
199#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
200#define L4_44XX_SIZE SZ_4M
201
202#define L4_PER_44XX_PHYS L4_PER_44XX_BASE
203 /* 0x48000000 --> 0xfa000000 */
204#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
205#define L4_PER_44XX_SIZE SZ_4M
206
207#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE
208 /* 0x49000000 --> 0xfb000000 */
209#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
210#define L4_ABE_44XX_SIZE SZ_1M
211
212#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
213 /* 0x54000000 --> 0xfe800000 */
214#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
215#define L4_EMU_44XX_SIZE SZ_8M
216
217#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
218 /* 0x50000000 --> 0xf9000000 */
219#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
220#define OMAP44XX_GPMC_SIZE SZ_1M
221
222
223#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE
224 /* 0x4c000000 --> 0xfd100000 */
225#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
226#define OMAP44XX_EMIF1_SIZE SZ_1M
227
228#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
229 /* 0x4d000000 --> 0xfd200000 */
230#define OMAP44XX_EMIF2_SIZE SZ_1M
231#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF1_SIZE)
232
233#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
234 /* 0x4e000000 --> 0xfd300000 */
235#define OMAP44XX_DMM_SIZE SZ_1M
236#define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE)
237/* 63/*
238 * ---------------------------------------------------------------------------- 64 * ----------------------------------------------------------------------------
239 * Omap specific register access 65 * Omap specific register access
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-03 00:52:47 -0500