diff options
Diffstat (limited to 'arch/arm/plat-omap/include/plat/control.h')
-rw-r--r-- | arch/arm/plat-omap/include/plat/control.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h index a56deee97676..131bf405c2f6 100644 --- a/arch/arm/plat-omap/include/plat/control.h +++ b/arch/arm/plat-omap/include/plat/control.h | |||
@@ -207,6 +207,9 @@ | |||
207 | /* 44xx control status register offset */ | 207 | /* 44xx control status register offset */ |
208 | #define OMAP44XX_CONTROL_STATUS 0x2c4 | 208 | #define OMAP44XX_CONTROL_STATUS 0x2c4 |
209 | 209 | ||
210 | /* 44xx-only CONTROL_GENERAL register offsets */ | ||
211 | #define OMAP44XX_CONTROL_MMC1 0x628 | ||
212 | #define OMAP44XX_CONTROL_PBIAS_LITE 0x600 | ||
210 | /* | 213 | /* |
211 | * REVISIT: This list of registers is not comprehensive - there are more | 214 | * REVISIT: This list of registers is not comprehensive - there are more |
212 | * that should be added. | 215 | * that should be added. |
@@ -252,6 +255,23 @@ | |||
252 | #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) | 255 | #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) |
253 | #define OMAP2_PBIASLITEVMODE0 (1 << 0) | 256 | #define OMAP2_PBIASLITEVMODE0 (1 << 0) |
254 | 257 | ||
258 | /* CONTROL_PBIAS_LITE bits for OMAP4 */ | ||
259 | #define OMAP4_MMC1_PWRDNZ (1 << 26) | ||
260 | #define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25) | ||
261 | #define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24) | ||
262 | #define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23) | ||
263 | #define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22) | ||
264 | #define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21) | ||
265 | #define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20) | ||
266 | |||
267 | #define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31) | ||
268 | #define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30) | ||
269 | #define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29) | ||
270 | #define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28) | ||
271 | #define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27) | ||
272 | #define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26) | ||
273 | #define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25) | ||
274 | |||
255 | /* CONTROL_PROG_IO1 bits */ | 275 | /* CONTROL_PROG_IO1 bits */ |
256 | #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) | 276 | #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) |
257 | 277 | ||