aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-omap/include/plat/control.h
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/plat-omap/include/plat/control.h')
-rw-r--r--arch/arm/plat-omap/include/plat/control.h230
1 files changed, 230 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
new file mode 100644
index 000000000000..805819f3a868
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -0,0 +1,230 @@
1/*
2 * arch/arm/plat-omap/include/mach/control.h
3 *
4 * OMAP2/3/4 System Control Module definitions
5 *
6 * Copyright (C) 2007-2009 Texas Instruments, Inc.
7 * Copyright (C) 2007-2008 Nokia Corporation
8 *
9 * Written by Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation.
14 */
15
16#ifndef __ASM_ARCH_CONTROL_H
17#define __ASM_ARCH_CONTROL_H
18
19#include <mach/io.h>
20
21#ifndef __ASSEMBLY__
22#define OMAP242X_CTRL_REGADDR(reg) \
23 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
24#define OMAP243X_CTRL_REGADDR(reg) \
25 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
26#define OMAP343X_CTRL_REGADDR(reg) \
27 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
28#else
29#define OMAP242X_CTRL_REGADDR(reg) \
30 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
31#define OMAP243X_CTRL_REGADDR(reg) \
32 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
33#define OMAP343X_CTRL_REGADDR(reg) \
34 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
35#endif /* __ASSEMBLY__ */
36
37/*
38 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
39 * OMAP24XX and OMAP34XX.
40 */
41
42/* Control submodule offsets */
43
44#define OMAP2_CONTROL_INTERFACE 0x000
45#define OMAP2_CONTROL_PADCONFS 0x030
46#define OMAP2_CONTROL_GENERAL 0x270
47#define OMAP343X_CONTROL_MEM_WKUP 0x600
48#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
49#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
50
51/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
52
53#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
54
55/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
56#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
57#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020)
58#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024)
59#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028)
60#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c)
61#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030)
62#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034)
63#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040)
64#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090)
65#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094)
66#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098)
67#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c)
68
69/* 242x-only CONTROL_GENERAL register offsets */
70#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */
71#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068)
72
73/* 243x-only CONTROL_GENERAL register offsets */
74/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
75#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078)
76#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c)
77#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
78#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
79#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198)
80#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230)
81
82/* 24xx-only CONTROL_GENERAL register offsets */
83#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000)
84#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008)
85#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044)
86#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048)
87#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c)
88#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050)
89#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060)
90#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064)
91#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c)
92#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070)
93#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074)
94#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
95#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
96#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088)
97#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
98#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0)
99#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4)
100#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8)
101#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac)
102#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0)
103#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4)
104#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0)
105#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4)
106#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8)
107#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc)
108#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0)
109#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4)
110#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8)
111#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc)
112#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0)
113#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4)
114
115/* 34xx-only CONTROL_GENERAL register offsets */
116#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000)
117#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008)
118#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c)
119#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068)
120#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c)
121#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070)
122#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074)
123#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078)
124#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080)
125#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
126#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0)
127#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8)
128#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac)
129#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0)
130#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4)
131#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8)
132#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc)
133#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0)
134#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4)
135#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8)
136#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc)
137#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0)
138#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4)
139#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8)
140#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec)
141#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0)
142#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
143#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
144#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
145#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
146#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
147#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02b0)
148#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4)
149
150/* 34xx D2D idle-related pins, handled by PM core */
151#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
152#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
153
154/*
155 * REVISIT: This list of registers is not comprehensive - there are more
156 * that should be added.
157 */
158
159/*
160 * Control module register bit defines - these should eventually go into
161 * their own regbits file. Some of these will be complicated, depending
162 * on the device type (general-purpose, emulator, test, secure, bad, other)
163 * and the security mode (secure, non-secure, don't care)
164 */
165/* CONTROL_DEVCONF0 bits */
166#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */
167#define OMAP24XX_USBSTANDBYCTRL (1 << 15)
168#define OMAP2_MCBSP2_CLKS_MASK (1 << 6)
169#define OMAP2_MCBSP1_CLKS_MASK (1 << 2)
170
171/* CONTROL_DEVCONF1 bits */
172#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31)
173#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */
174#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */
175#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */
176#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */
177
178/* CONTROL_STATUS bits */
179#define OMAP2_DEVICETYPE_MASK (0x7 << 8)
180#define OMAP2_SYSBOOT_5_MASK (1 << 5)
181#define OMAP2_SYSBOOT_4_MASK (1 << 4)
182#define OMAP2_SYSBOOT_3_MASK (1 << 3)
183#define OMAP2_SYSBOOT_2_MASK (1 << 2)
184#define OMAP2_SYSBOOT_1_MASK (1 << 1)
185#define OMAP2_SYSBOOT_0_MASK (1 << 0)
186
187/* CONTROL_PBIAS_LITE bits */
188#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15)
189#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11)
190#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10)
191#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9)
192#define OMAP343X_PBIASLITEVMODE1 (1 << 8)
193#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7)
194#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3)
195#define OMAP2_PBIASSPEEDCTRL0 (1 << 2)
196#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
197#define OMAP2_PBIASLITEVMODE0 (1 << 0)
198
199/* CONTROL_IVA2_BOOTMOD bits */
200#define OMAP3_IVA2_BOOTMOD_SHIFT 0
201#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
202#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
203
204/* CONTROL_PADCONF_X bits */
205#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
206#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
207
208#ifndef __ASSEMBLY__
209#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
210 defined(CONFIG_ARCH_OMAP4)
211extern void __iomem *omap_ctrl_base_get(void);
212extern u8 omap_ctrl_readb(u16 offset);
213extern u16 omap_ctrl_readw(u16 offset);
214extern u32 omap_ctrl_readl(u16 offset);
215extern void omap_ctrl_writeb(u8 val, u16 offset);
216extern void omap_ctrl_writew(u16 val, u16 offset);
217extern void omap_ctrl_writel(u32 val, u16 offset);
218#else
219#define omap_ctrl_base_get() 0
220#define omap_ctrl_readb(x) 0
221#define omap_ctrl_readw(x) 0
222#define omap_ctrl_readl(x) 0
223#define omap_ctrl_writeb(x, y) WARN_ON(1)
224#define omap_ctrl_writew(x, y) WARN_ON(1)
225#define omap_ctrl_writel(x, y) WARN_ON(1)
226#endif
227#endif /* __ASSEMBLY__ */
228
229#endif /* __ASM_ARCH_CONTROL_H */
230
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 08:33:35 -0500