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-rw-r--r--arch/arm/plat-omap/include/mach/clock.h10
-rw-r--r--arch/arm/plat-omap/include/mach/common.h3
-rw-r--r--arch/arm/plat-omap/include/mach/control.h20
-rw-r--r--arch/arm/plat-omap/include/mach/cpu.h21
-rw-r--r--arch/arm/plat-omap/include/mach/debug-macro.S2
-rw-r--r--arch/arm/plat-omap/include/mach/dma.h4
-rw-r--r--arch/arm/plat-omap/include/mach/entry-macro.S83
-rw-r--r--arch/arm/plat-omap/include/mach/gpmc-smc91x.h42
-rw-r--r--arch/arm/plat-omap/include/mach/hardware.h1
-rw-r--r--arch/arm/plat-omap/include/mach/hwa742.h4
-rw-r--r--arch/arm/plat-omap/include/mach/io.h37
-rw-r--r--arch/arm/plat-omap/include/mach/iommu.h168
-rw-r--r--arch/arm/plat-omap/include/mach/iommu2.h96
-rw-r--r--arch/arm/plat-omap/include/mach/iovmm.h94
-rw-r--r--arch/arm/plat-omap/include/mach/irqs.h92
-rw-r--r--arch/arm/plat-omap/include/mach/keypad.h4
-rw-r--r--arch/arm/plat-omap/include/mach/memory.h3
-rw-r--r--arch/arm/plat-omap/include/mach/omap24xx.h18
-rw-r--r--arch/arm/plat-omap/include/mach/omap34xx.h13
-rw-r--r--arch/arm/plat-omap/include/mach/omap44xx.h46
-rw-r--r--arch/arm/plat-omap/include/mach/onenand.h22
-rw-r--r--arch/arm/plat-omap/include/mach/pm.h345
-rw-r--r--arch/arm/plat-omap/include/mach/serial.h25
-rw-r--r--arch/arm/plat-omap/include/mach/smp.h51
-rw-r--r--arch/arm/plat-omap/include/mach/sram.h6
-rw-r--r--arch/arm/plat-omap/include/mach/usb.h6
-rw-r--r--arch/arm/plat-omap/include/mach/vmalloc.h2
27 files changed, 806 insertions, 412 deletions
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index 073a2c5569f0..f9f65e1ba3f1 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -22,7 +22,8 @@ struct clkops {
22 void (*disable)(struct clk *); 22 void (*disable)(struct clk *);
23}; 23};
24 24
25#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 25#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
26 defined(CONFIG_ARCH_OMAP4)
26 27
27struct clksel_rate { 28struct clksel_rate {
28 u32 val; 29 u32 val;
@@ -51,7 +52,7 @@ struct dpll_data {
51 u8 max_divider; 52 u8 max_divider;
52 u32 max_tolerance; 53 u32 max_tolerance;
53 u16 max_multiplier; 54 u16 max_multiplier;
54# if defined(CONFIG_ARCH_OMAP3) 55#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
55 u8 modes; 56 u8 modes;
56 void __iomem *autoidle_reg; 57 void __iomem *autoidle_reg;
57 void __iomem *idlest_reg; 58 void __iomem *idlest_reg;
@@ -83,7 +84,8 @@ struct clk {
83 void (*init)(struct clk *); 84 void (*init)(struct clk *);
84 __u8 enable_bit; 85 __u8 enable_bit;
85 __s8 usecount; 86 __s8 usecount;
86#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 87#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
88 defined(CONFIG_ARCH_OMAP4)
87 u8 fixed_div; 89 u8 fixed_div;
88 void __iomem *clksel_reg; 90 void __iomem *clksel_reg;
89 u32 clksel_mask; 91 u32 clksel_mask;
@@ -119,7 +121,7 @@ struct clk_functions {
119extern unsigned int mpurate; 121extern unsigned int mpurate;
120 122
121extern int clk_init(struct clk_functions *custom_clocks); 123extern int clk_init(struct clk_functions *custom_clocks);
122extern void clk_init_one(struct clk *clk); 124extern void clk_preinit(struct clk *clk);
123extern int clk_register(struct clk *clk); 125extern int clk_register(struct clk *clk);
124extern void clk_reparent(struct clk *child, struct clk *parent); 126extern void clk_reparent(struct clk *child, struct clk *parent);
125extern void clk_unregister(struct clk *clk); 127extern void clk_unregister(struct clk *clk);
diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/mach/common.h
index 0ecf36deb17b..fdeab421b4dc 100644
--- a/arch/arm/plat-omap/include/mach/common.h
+++ b/arch/arm/plat-omap/include/mach/common.h
@@ -33,8 +33,6 @@ struct sys_timer;
33 33
34extern void omap_map_common_io(void); 34extern void omap_map_common_io(void);
35extern struct sys_timer omap_timer; 35extern struct sys_timer omap_timer;
36extern void omap_serial_init(void);
37extern void omap_serial_enable_clocks(int enable);
38#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) 36#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
39extern int omap_register_i2c_bus(int bus_id, u32 clkrate, 37extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
40 struct i2c_board_info const *info, 38 struct i2c_board_info const *info,
@@ -62,6 +60,7 @@ struct omap_globals {
62void omap2_set_globals_242x(void); 60void omap2_set_globals_242x(void);
63void omap2_set_globals_243x(void); 61void omap2_set_globals_243x(void);
64void omap2_set_globals_343x(void); 62void omap2_set_globals_343x(void);
63void omap2_set_globals_443x(void);
65 64
66/* These get called from omap2_set_globals_xxxx(), do not call these */ 65/* These get called from omap2_set_globals_xxxx(), do not call these */
67void omap2_set_globals_tap(struct omap_globals *); 66void omap2_set_globals_tap(struct omap_globals *);
diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h
index 269147f3836f..8140dbccb7bc 100644
--- a/arch/arm/plat-omap/include/mach/control.h
+++ b/arch/arm/plat-omap/include/mach/control.h
@@ -1,9 +1,9 @@
1/* 1/*
2 * arch/arm/plat-omap/include/mach/control.h 2 * arch/arm/plat-omap/include/mach/control.h
3 * 3 *
4 * OMAP2/3 System Control Module definitions 4 * OMAP2/3/4 System Control Module definitions
5 * 5 *
6 * Copyright (C) 2007-2008 Texas Instruments, Inc. 6 * Copyright (C) 2007-2009 Texas Instruments, Inc.
7 * Copyright (C) 2007-2008 Nokia Corporation 7 * Copyright (C) 2007-2008 Nokia Corporation
8 * 8 *
9 * Written by Paul Walmsley 9 * Written by Paul Walmsley
@@ -144,6 +144,10 @@
144#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02b0) 144#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02b0)
145#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4) 145#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4)
146 146
147/* 34xx D2D idle-related pins, handled by PM core */
148#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
149#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
150
147/* 151/*
148 * REVISIT: This list of registers is not comprehensive - there are more 152 * REVISIT: This list of registers is not comprehensive - there are more
149 * that should be added. 153 * that should be added.
@@ -189,8 +193,18 @@
189#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) 193#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
190#define OMAP2_PBIASLITEVMODE0 (1 << 0) 194#define OMAP2_PBIASLITEVMODE0 (1 << 0)
191 195
196/* CONTROL_IVA2_BOOTMOD bits */
197#define OMAP3_IVA2_BOOTMOD_SHIFT 0
198#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
199#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0)
200
201/* CONTROL_PADCONF_X bits */
202#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15)
203#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14)
204
192#ifndef __ASSEMBLY__ 205#ifndef __ASSEMBLY__
193#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 206#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
207 defined(CONFIG_ARCH_OMAP4)
194extern void __iomem *omap_ctrl_base_get(void); 208extern void __iomem *omap_ctrl_base_get(void);
195extern u8 omap_ctrl_readb(u16 offset); 209extern u8 omap_ctrl_readb(u16 offset);
196extern u16 omap_ctrl_readw(u16 offset); 210extern u16 omap_ctrl_readw(u16 offset);
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h
index 98b144252364..fc60c4ebcc28 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/mach/cpu.h
@@ -5,8 +5,12 @@
5 * 5 *
6 * Copyright (C) 2004, 2008 Nokia Corporation 6 * Copyright (C) 2004, 2008 Nokia Corporation
7 * 7 *
8 * Copyright (C) 2009 Texas Instruments.
9 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com> 10 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 * 11 *
12 * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
13 *
10 * This program is free software; you can redistribute it and/or modify 14 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by 15 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or 16 * the Free Software Foundation; either version 2 of the License, or
@@ -155,6 +159,8 @@ IS_OMAP_SUBCLASS(343x, 0x343)
155#define cpu_is_omap243x() 0 159#define cpu_is_omap243x() 0
156#define cpu_is_omap34xx() 0 160#define cpu_is_omap34xx() 0
157#define cpu_is_omap343x() 0 161#define cpu_is_omap343x() 0
162#define cpu_is_omap44xx() 0
163#define cpu_is_omap443x() 0
158 164
159#if defined(MULTI_OMAP1) 165#if defined(MULTI_OMAP1)
160# if defined(CONFIG_ARCH_OMAP730) 166# if defined(CONFIG_ARCH_OMAP730)
@@ -348,12 +354,21 @@ IS_OMAP_TYPE(3430, 0x3430)
348# define cpu_is_omap3430() is_omap3430() 354# define cpu_is_omap3430() is_omap3430()
349#endif 355#endif
350 356
357# if defined(CONFIG_ARCH_OMAP4)
358# undef cpu_is_omap44xx
359# undef cpu_is_omap443x
360# define cpu_is_omap44xx() 1
361# define cpu_is_omap443x() 1
362# endif
363
351/* Macros to detect if we have OMAP1 or OMAP2 */ 364/* Macros to detect if we have OMAP1 or OMAP2 */
352#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \ 365#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
353 cpu_is_omap16xx()) 366 cpu_is_omap16xx())
354#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx()) 367#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
368 cpu_is_omap44xx())
355 369
356#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 370#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
371 defined(CONFIG_ARCH_OMAP4)
357 372
358/* Various silicon revisions for omap2 */ 373/* Various silicon revisions for omap2 */
359#define OMAP242X_CLASS 0x24200024 374#define OMAP242X_CLASS 0x24200024
@@ -370,6 +385,8 @@ IS_OMAP_TYPE(3430, 0x3430)
370#define OMAP3430_REV_ES3_0 0x34303034 385#define OMAP3430_REV_ES3_0 0x34303034
371#define OMAP3430_REV_ES3_1 0x34304034 386#define OMAP3430_REV_ES3_1 0x34304034
372 387
388#define OMAP443X_CLASS 0x44300034
389
373/* 390/*
374 * omap_chip bits 391 * omap_chip bits
375 * 392 *
diff --git a/arch/arm/plat-omap/include/mach/debug-macro.S b/arch/arm/plat-omap/include/mach/debug-macro.S
index 1b11f5c6a2d9..ac24050e3416 100644
--- a/arch/arm/plat-omap/include/mach/debug-macro.S
+++ b/arch/arm/plat-omap/include/mach/debug-macro.S
@@ -36,7 +36,7 @@
36 add \rx, \rx, #0x00004000 @ UART 3 36 add \rx, \rx, #0x00004000 @ UART 3
37#endif 37#endif
38 38
39#elif CONFIG_ARCH_OMAP3 39#elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
40 moveq \rx, #0x48000000 @ physical base address 40 moveq \rx, #0x48000000 @ physical base address
41 movne \rx, #0xd8000000 @ virtual base 41 movne \rx, #0xd8000000 @ virtual base
42 orr \rx, \rx, #0x0006a000 42 orr \rx, \rx, #0x0006a000
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h
index 54fe9665b182..8c1eae88737e 100644
--- a/arch/arm/plat-omap/include/mach/dma.h
+++ b/arch/arm/plat-omap/include/mach/dma.h
@@ -48,6 +48,7 @@
48/* Hardware registers for omap2 and omap3 */ 48/* Hardware registers for omap2 and omap3 */
49#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000) 49#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
50#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000) 50#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
51#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000)
51 52
52#define OMAP_DMA4_REVISION 0x00 53#define OMAP_DMA4_REVISION 0x00
53#define OMAP_DMA4_GCR 0x78 54#define OMAP_DMA4_GCR 0x78
@@ -144,6 +145,7 @@
144#define OMAP_DMA4_CSSA_U(n) 0 145#define OMAP_DMA4_CSSA_U(n) 0
145#define OMAP_DMA4_CDSA_L(n) 0 146#define OMAP_DMA4_CDSA_L(n) 0
146#define OMAP_DMA4_CDSA_U(n) 0 147#define OMAP_DMA4_CDSA_U(n) 0
148#define OMAP1_DMA_COLOR(n) 0
147 149
148/*----------------------------------------------------------------------------*/ 150/*----------------------------------------------------------------------------*/
149 151
@@ -531,7 +533,7 @@ extern int omap_get_dma_index(int lch, int *ei, int *fi);
531/* Chaining APIs */ 533/* Chaining APIs */
532#ifndef CONFIG_ARCH_OMAP1 534#ifndef CONFIG_ARCH_OMAP1
533extern int omap_request_dma_chain(int dev_id, const char *dev_name, 535extern int omap_request_dma_chain(int dev_id, const char *dev_name,
534 void (*callback) (int chain_id, u16 ch_status, 536 void (*callback) (int lch, u16 ch_status,
535 void *data), 537 void *data),
536 int *chain_id, int no_of_chans, 538 int *chain_id, int no_of_chans,
537 int chain_mode, 539 int chain_mode,
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S
index 2276f89671d8..56426ed45ef4 100644
--- a/arch/arm/plat-omap/include/mach/entry-macro.S
+++ b/arch/arm/plat-omap/include/mach/entry-macro.S
@@ -3,6 +3,9 @@
3 * 3 *
4 * Low-level IRQ helper macros for OMAP-based platforms 4 * Low-level IRQ helper macros for OMAP-based platforms
5 * 5 *
6 * Copyright (C) 2009 Texas Instruments
7 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
6 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
@@ -10,6 +13,7 @@
10#include <mach/hardware.h> 13#include <mach/hardware.h>
11#include <mach/io.h> 14#include <mach/io.h>
12#include <mach/irqs.h> 15#include <mach/irqs.h>
16#include <asm/hardware/gic.h>
13 17
14#if defined(CONFIG_ARCH_OMAP1) 18#if defined(CONFIG_ARCH_OMAP1)
15 19
@@ -56,15 +60,21 @@
56 .endm 60 .endm
57 61
58#endif 62#endif
59#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 63#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
64 defined(CONFIG_ARCH_OMAP4)
60 65
61#if defined(CONFIG_ARCH_OMAP24XX)
62#include <mach/omap24xx.h> 66#include <mach/omap24xx.h>
63#endif
64#if defined(CONFIG_ARCH_OMAP34XX)
65#include <mach/omap34xx.h> 67#include <mach/omap34xx.h>
66#endif
67 68
69/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
70#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)
71#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)
72#elif defined(CONFIG_ARCH_OMAP34XX)
73#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE)
74#endif
75#if defined(CONFIG_ARCH_OMAP4)
76#include <mach/omap44xx.h>
77#endif
68#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */ 78#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */
69#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ 79#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */
70 80
@@ -77,6 +87,7 @@
77 .macro arch_ret_to_user, tmp1, tmp2 87 .macro arch_ret_to_user, tmp1, tmp2
78 .endm 88 .endm
79 89
90#ifndef CONFIG_ARCH_OMAP4
80 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 91 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
81 ldr \base, =OMAP2_VA_IC_BASE 92 ldr \base, =OMAP2_VA_IC_BASE
82 ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ 93 ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
@@ -92,6 +103,68 @@
92 and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ 103 and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
93 104
94 .endm 105 .endm
106#else
107 /*
108 * The interrupt numbering scheme is defined in the
109 * interrupt controller spec. To wit:
110 *
111 * Interrupts 0-15 are IPI
112 * 16-28 are reserved
113 * 29-31 are local. We allow 30 to be used for the watchdog.
114 * 32-1020 are global
115 * 1021-1022 are reserved
116 * 1023 is "spurious" (no interrupt)
117 *
118 * For now, we ignore all local interrupts so only return an
119 * interrupt if it's between 30 and 1020. The test_for_ipi
120 * routine below will pick up on IPIs.
121 * A simple read from the controller will tell us the number
122 * of the highest priority enabled interrupt.
123 * We then just need to check whether it is in the
124 * valid range for an IRQ (30-1020 inclusive).
125 */
126 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
127 ldr \base, =OMAP44XX_VA_GIC_CPU_BASE
128 ldr \irqstat, [\base, #GIC_CPU_INTACK]
129
130 ldr \tmp, =1021
131
132 bic \irqnr, \irqstat, #0x1c00
133
134 cmp \irqnr, #29
135 cmpcc \irqnr, \irqnr
136 cmpne \irqnr, \tmp
137 cmpcs \irqnr, \irqnr
138 .endm
139
140 /* We assume that irqstat (the raw value of the IRQ acknowledge
141 * register) is preserved from the macro above.
142 * If there is an IPI, we immediately signal end of interrupt
143 * on the controller, since this requires the original irqstat
144 * value which we won't easily be able to recreate later.
145 */
146
147 .macro test_for_ipi, irqnr, irqstat, base, tmp
148 bic \irqnr, \irqstat, #0x1c00
149 cmp \irqnr, #16
150 it cc
151 strcc \irqstat, [\base, #GIC_CPU_EOI]
152 it cs
153 cmpcs \irqnr, \irqnr
154 .endm
155
156 /* As above, this assumes that irqstat and base are preserved */
157
158 .macro test_for_ltirq, irqnr, irqstat, base, tmp
159 bic \irqnr, \irqstat, #0x1c00
160 mov \tmp, #0
161 cmp \irqnr, #29
162 itt eq
163 moveq \tmp, #1
164 streq \irqstat, [\base, #GIC_CPU_EOI]
165 cmp \tmp, #0
166 .endm
167#endif
95 168
96 .macro irq_prio_table 169 .macro irq_prio_table
97 .endm 170 .endm
diff --git a/arch/arm/plat-omap/include/mach/gpmc-smc91x.h b/arch/arm/plat-omap/include/mach/gpmc-smc91x.h
new file mode 100644
index 000000000000..b64fbee4d567
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/gpmc-smc91x.h
@@ -0,0 +1,42 @@
1/*
2 * arch/arm/plat-omap/include/mach/gpmc-smc91x.h
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__
12
13#define GPMC_TIMINGS_SMC91C96 (1 << 4)
14#define GPMC_MUX_ADD_DATA (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */
15#define GPMC_READ_MON (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */
16#define GPMC_WRITE_MON (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */
17
18struct omap_smc91x_platform_data {
19 int cs;
20 int gpio_irq;
21 int gpio_pwrdwn;
22 int gpio_reset;
23 int wait_pin; /* Optional GPMC_CONFIG1_WAITPINSELECT */
24 u32 flags;
25 int (*retime)(void);
26};
27
28#if defined(CONFIG_SMC91X) || \
29 defined(CONFIG_SMC91X_MODULE)
30
31extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d);
32
33#else
34
35#define board_smc91x_data NULL
36
37static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d)
38{
39}
40
41#endif
42#endif
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h
index 3dc423ed3e80..26c1fbff08aa 100644
--- a/arch/arm/plat-omap/include/mach/hardware.h
+++ b/arch/arm/plat-omap/include/mach/hardware.h
@@ -285,5 +285,6 @@
285#include "omap16xx.h" 285#include "omap16xx.h"
286#include "omap24xx.h" 286#include "omap24xx.h"
287#include "omap34xx.h" 287#include "omap34xx.h"
288#include "omap44xx.h"
288 289
289#endif /* __ASM_ARCH_OMAP_HARDWARE_H */ 290#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/mach/hwa742.h b/arch/arm/plat-omap/include/mach/hwa742.h
index 577f492f2d3c..886248d32b49 100644
--- a/arch/arm/plat-omap/include/mach/hwa742.h
+++ b/arch/arm/plat-omap/include/mach/hwa742.h
@@ -2,10 +2,6 @@
2#define _HWA742_H 2#define _HWA742_H
3 3
4struct hwa742_platform_data { 4struct hwa742_platform_data {
5 void (*power_up)(struct device *dev);
6 void (*power_down)(struct device *dev);
7 unsigned long (*get_clock_rate)(struct device *dev);
8
9 unsigned te_connected:1; 5 unsigned te_connected:1;
10}; 6};
11 7
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index 0610d7e2b3d7..3b2814720569 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -6,6 +6,9 @@
6 * Copied from arch/arm/mach-sa1100/include/mach/io.h 6 * Copied from arch/arm/mach-sa1100/include/mach/io.h
7 * Copyright (C) 1997-1999 Russell King 7 * Copyright (C) 1997-1999 Russell King
8 * 8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
9 * This program is free software; you can redistribute it and/or modify it 12 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the 13 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your 14 * Free Software Foundation; either version 2 of the License, or (at your
@@ -157,6 +160,40 @@
157#define DSP_MMU_34XX_VIRT 0xe2000000 160#define DSP_MMU_34XX_VIRT 0xe2000000
158#define DSP_MMU_34XX_SIZE SZ_4K 161#define DSP_MMU_34XX_SIZE SZ_4K
159 162
163
164#elif defined(CONFIG_ARCH_OMAP4)
165/* We map both L3 and L4 on OMAP4 */
166#define L3_44XX_PHYS L3_44XX_BASE
167#define L3_44XX_VIRT 0xd4000000
168#define L3_44XX_SIZE SZ_1M
169
170#define L4_44XX_PHYS L4_44XX_BASE
171#define L4_44XX_VIRT 0xda000000
172#define L4_44XX_SIZE SZ_4M
173
174
175#define L4_WK_44XX_PHYS L4_WK_44XX_BASE
176#define L4_WK_44XX_VIRT 0xda300000
177#define L4_WK_44XX_SIZE SZ_1M
178
179#define L4_PER_44XX_PHYS L4_PER_44XX_BASE
180#define L4_PER_44XX_VIRT 0xd8000000
181#define L4_PER_44XX_SIZE SZ_4M
182
183#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
184#define L4_EMU_44XX_VIRT 0xe4000000
185#define L4_EMU_44XX_SIZE SZ_64M
186
187#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
188#define OMAP44XX_GPMC_VIRT 0xe0000000
189#define OMAP44XX_GPMC_SIZE SZ_1M
190
191
192#define IO_OFFSET 0x90000000
193#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
194#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
195#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
196
160#endif 197#endif
161 198
162#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) 199#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
diff --git a/arch/arm/plat-omap/include/mach/iommu.h b/arch/arm/plat-omap/include/mach/iommu.h
new file mode 100644
index 000000000000..769b00b4c34a
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/iommu.h
@@ -0,0 +1,168 @@
1/*
2 * omap iommu: main structures
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __MACH_IOMMU_H
14#define __MACH_IOMMU_H
15
16struct iotlb_entry {
17 u32 da;
18 u32 pa;
19 u32 pgsz, prsvd, valid;
20 union {
21 u16 ap;
22 struct {
23 u32 endian, elsz, mixed;
24 };
25 };
26};
27
28struct iommu {
29 const char *name;
30 struct module *owner;
31 struct clk *clk;
32 void __iomem *regbase;
33 struct device *dev;
34
35 unsigned int refcount;
36 struct mutex iommu_lock; /* global for this whole object */
37
38 /*
39 * We don't change iopgd for a situation like pgd for a task,
40 * but share it globally for each iommu.
41 */
42 u32 *iopgd;
43 spinlock_t page_table_lock; /* protect iopgd */
44
45 int nr_tlb_entries;
46
47 struct list_head mmap;
48 struct mutex mmap_lock; /* protect mmap */
49
50 int (*isr)(struct iommu *obj);
51
52 void *ctx; /* iommu context: registres saved area */
53};
54
55struct cr_regs {
56 union {
57 struct {
58 u16 cam_l;
59 u16 cam_h;
60 };
61 u32 cam;
62 };
63 union {
64 struct {
65 u16 ram_l;
66 u16 ram_h;
67 };
68 u32 ram;
69 };
70};
71
72struct iotlb_lock {
73 short base;
74 short vict;
75};
76
77/* architecture specific functions */
78struct iommu_functions {
79 unsigned long version;
80
81 int (*enable)(struct iommu *obj);
82 void (*disable)(struct iommu *obj);
83 u32 (*fault_isr)(struct iommu *obj, u32 *ra);
84
85 void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
86 void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr);
87
88 struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e);
89 int (*cr_valid)(struct cr_regs *cr);
90 u32 (*cr_to_virt)(struct cr_regs *cr);
91 void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
92 ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf);
93
94 u32 (*get_pte_attr)(struct iotlb_entry *e);
95
96 void (*save_ctx)(struct iommu *obj);
97 void (*restore_ctx)(struct iommu *obj);
98 ssize_t (*dump_ctx)(struct iommu *obj, char *buf);
99};
100
101struct iommu_platform_data {
102 const char *name;
103 const char *clk_name;
104 const int nr_tlb_entries;
105};
106
107#if defined(CONFIG_ARCH_OMAP1)
108#error "iommu for this processor not implemented yet"
109#else
110#include <mach/iommu2.h>
111#endif
112
113/*
114 * utilities for super page(16MB, 1MB, 64KB and 4KB)
115 */
116
117#define iopgsz_max(bytes) \
118 (((bytes) >= SZ_16M) ? SZ_16M : \
119 ((bytes) >= SZ_1M) ? SZ_1M : \
120 ((bytes) >= SZ_64K) ? SZ_64K : \
121 ((bytes) >= SZ_4K) ? SZ_4K : 0)
122
123#define bytes_to_iopgsz(bytes) \
124 (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
125 ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
126 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
127 ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
128
129#define iopgsz_to_bytes(iopgsz) \
130 (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
131 ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
132 ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
133 ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
134
135#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
136
137/*
138 * global functions
139 */
140extern u32 iommu_arch_version(void);
141
142extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
143extern u32 iotlb_cr_to_virt(struct cr_regs *cr);
144
145extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
146extern void flush_iotlb_page(struct iommu *obj, u32 da);
147extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
148extern void flush_iotlb_all(struct iommu *obj);
149
150extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
151extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
152
153extern struct iommu *iommu_get(const char *name);
154extern void iommu_put(struct iommu *obj);
155
156extern void iommu_save_ctx(struct iommu *obj);
157extern void iommu_restore_ctx(struct iommu *obj);
158
159extern int install_iommu_arch(const struct iommu_functions *ops);
160extern void uninstall_iommu_arch(const struct iommu_functions *ops);
161
162extern int foreach_iommu_device(void *data,
163 int (*fn)(struct device *, void *));
164
165extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf);
166extern size_t dump_tlb_entries(struct iommu *obj, char *buf);
167
168#endif /* __MACH_IOMMU_H */
diff --git a/arch/arm/plat-omap/include/mach/iommu2.h b/arch/arm/plat-omap/include/mach/iommu2.h
new file mode 100644
index 000000000000..10ad05f410e9
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/iommu2.h
@@ -0,0 +1,96 @@
1/*
2 * omap iommu: omap2 architecture specific definitions
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __MACH_IOMMU2_H
14#define __MACH_IOMMU2_H
15
16#include <linux/io.h>
17
18/*
19 * MMU Register offsets
20 */
21#define MMU_REVISION 0x00
22#define MMU_SYSCONFIG 0x10
23#define MMU_SYSSTATUS 0x14
24#define MMU_IRQSTATUS 0x18
25#define MMU_IRQENABLE 0x1c
26#define MMU_WALKING_ST 0x40
27#define MMU_CNTL 0x44
28#define MMU_FAULT_AD 0x48
29#define MMU_TTB 0x4c
30#define MMU_LOCK 0x50
31#define MMU_LD_TLB 0x54
32#define MMU_CAM 0x58
33#define MMU_RAM 0x5c
34#define MMU_GFLUSH 0x60
35#define MMU_FLUSH_ENTRY 0x64
36#define MMU_READ_CAM 0x68
37#define MMU_READ_RAM 0x6c
38#define MMU_EMU_FAULT_AD 0x70
39
40#define MMU_REG_SIZE 256
41
42/*
43 * MMU Register bit definitions
44 */
45#define MMU_LOCK_BASE_SHIFT 10
46#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
47#define MMU_LOCK_BASE(x) \
48 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
49
50#define MMU_LOCK_VICT_SHIFT 4
51#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
52#define MMU_LOCK_VICT(x) \
53 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
54
55#define MMU_CAM_VATAG_SHIFT 12
56#define MMU_CAM_VATAG_MASK \
57 ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
58#define MMU_CAM_P (1 << 3)
59#define MMU_CAM_V (1 << 2)
60#define MMU_CAM_PGSZ_MASK 3
61#define MMU_CAM_PGSZ_1M (0 << 0)
62#define MMU_CAM_PGSZ_64K (1 << 0)
63#define MMU_CAM_PGSZ_4K (2 << 0)
64#define MMU_CAM_PGSZ_16M (3 << 0)
65
66#define MMU_RAM_PADDR_SHIFT 12
67#define MMU_RAM_PADDR_MASK \
68 ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
69#define MMU_RAM_ENDIAN_SHIFT 9
70#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
71#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT)
72#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
73#define MMU_RAM_ELSZ_SHIFT 7
74#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
75#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
76#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
77#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
78#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
79#define MMU_RAM_MIXED_SHIFT 6
80#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
81#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
82
83/*
84 * register accessors
85 */
86static inline u32 iommu_read_reg(struct iommu *obj, size_t offs)
87{
88 return __raw_readl(obj->regbase + offs);
89}
90
91static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs)
92{
93 __raw_writel(val, obj->regbase + offs);
94}
95
96#endif /* __MACH_IOMMU2_H */
diff --git a/arch/arm/plat-omap/include/mach/iovmm.h b/arch/arm/plat-omap/include/mach/iovmm.h
new file mode 100644
index 000000000000..bdc7ce5d7a4a
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/iovmm.h
@@ -0,0 +1,94 @@
1/*
2 * omap iommu: simple virtual address space management
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __IOMMU_MMAP_H
14#define __IOMMU_MMAP_H
15
16struct iovm_struct {
17 struct iommu *iommu; /* iommu object which this belongs to */
18 u32 da_start; /* area definition */
19 u32 da_end;
20 u32 flags; /* IOVMF_: see below */
21 struct list_head list; /* linked in ascending order */
22 const struct sg_table *sgt; /* keep 'page' <-> 'da' mapping */
23 void *va; /* mpu side mapped address */
24};
25
26/*
27 * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma)
28 *
29 * lower 16 bit is used for h/w and upper 16 bit is for s/w.
30 */
31#define IOVMF_SW_SHIFT 16
32#define IOVMF_HW_SIZE (1 << IOVMF_SW_SHIFT)
33#define IOVMF_HW_MASK (IOVMF_HW_SIZE - 1)
34#define IOVMF_SW_MASK (~IOVMF_HW_MASK)UL
35
36/*
37 * iovma: h/w flags derived from cam and ram attribute
38 */
39#define IOVMF_CAM_MASK (~((1 << 10) - 1))
40#define IOVMF_RAM_MASK (~IOVMF_CAM_MASK)
41
42#define IOVMF_PGSZ_MASK (3 << 0)
43#define IOVMF_PGSZ_1M MMU_CAM_PGSZ_1M
44#define IOVMF_PGSZ_64K MMU_CAM_PGSZ_64K
45#define IOVMF_PGSZ_4K MMU_CAM_PGSZ_4K
46#define IOVMF_PGSZ_16M MMU_CAM_PGSZ_16M
47
48#define IOVMF_ENDIAN_MASK (1 << 9)
49#define IOVMF_ENDIAN_BIG MMU_RAM_ENDIAN_BIG
50#define IOVMF_ENDIAN_LITTLE MMU_RAM_ENDIAN_LITTLE
51
52#define IOVMF_ELSZ_MASK (3 << 7)
53#define IOVMF_ELSZ_8 MMU_RAM_ELSZ_8
54#define IOVMF_ELSZ_16 MMU_RAM_ELSZ_16
55#define IOVMF_ELSZ_32 MMU_RAM_ELSZ_32
56#define IOVMF_ELSZ_NONE MMU_RAM_ELSZ_NONE
57
58#define IOVMF_MIXED_MASK (1 << 6)
59#define IOVMF_MIXED MMU_RAM_MIXED
60
61/*
62 * iovma: s/w flags, used for mapping and umapping internally.
63 */
64#define IOVMF_MMIO (1 << IOVMF_SW_SHIFT)
65#define IOVMF_ALLOC (2 << IOVMF_SW_SHIFT)
66#define IOVMF_ALLOC_MASK (3 << IOVMF_SW_SHIFT)
67
68/* "superpages" is supported just with physically linear pages */
69#define IOVMF_DISCONT (1 << (2 + IOVMF_SW_SHIFT))
70#define IOVMF_LINEAR (2 << (2 + IOVMF_SW_SHIFT))
71#define IOVMF_LINEAR_MASK (3 << (2 + IOVMF_SW_SHIFT))
72
73#define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT))
74#define IOVMF_DA_ANON (2 << (4 + IOVMF_SW_SHIFT))
75#define IOVMF_DA_MASK (3 << (4 + IOVMF_SW_SHIFT))
76
77
78extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da);
79extern u32 iommu_vmap(struct iommu *obj, u32 da,
80 const struct sg_table *sgt, u32 flags);
81extern struct sg_table *iommu_vunmap(struct iommu *obj, u32 da);
82extern u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes,
83 u32 flags);
84extern void iommu_vfree(struct iommu *obj, const u32 da);
85extern u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
86 u32 flags);
87extern void iommu_kunmap(struct iommu *obj, u32 da);
88extern u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes,
89 u32 flags);
90extern void iommu_kfree(struct iommu *obj, u32 da);
91
92extern void *da_to_va(struct iommu *obj, u32 da);
93
94#endif /* __IOMMU_MMAP_H */
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
index 7f57ee66f364..fb7cb7723990 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -4,6 +4,9 @@
4 * Copyright (C) Greg Lonnon 2001 4 * Copyright (C) Greg Lonnon 2001
5 * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> 5 * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
6 * 6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
7 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 11 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or 12 * the Free Software Foundation; either version 2 of the License, or
@@ -422,6 +425,94 @@
422 425
423#define INT_34XX_BENCH_MPU_EMUL 3 426#define INT_34XX_BENCH_MPU_EMUL 3
424 427
428
429#define IRQ_GIC_START 32
430#define INT_44XX_LOCALTIMER_IRQ 29
431#define INT_44XX_LOCALWDT_IRQ 30
432
433#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
434#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START)
435#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START)
436#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START)
437#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START)
438#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START)
439#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START)
440#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START)
441#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START)
442#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START)
443#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START)
444#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START)
445#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START)
446#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START)
447#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START)
448#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START)
449#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START)
450#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START)
451#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START)
452#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START)
453#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START)
454#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START)
455#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START)
456#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START)
457#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START)
458#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START)
459#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START)
460#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START)
461#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START)
462#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START)
463#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START)
464#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START)
465#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START)
466#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START)
467#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START)
468#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START)
469#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START)
470#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START)
471#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START)
472#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START)
473#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START)
474#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START)
475#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START)
476#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START)
477#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START)
478#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START)
479#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START)
480#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START)
481#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START)
482#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START)
483#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START)
484
485#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START)
486#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START)
487#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START)
488#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START)
489#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START)
490#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START)
491#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START)
492
493#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START)
494#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START)
495#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START)
496#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START)
497#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START)
498#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START)
499#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START)
500#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START)
501#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START)
502#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START)
503#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
504#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START)
505#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START)
506#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START)
507#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
508#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START)
509#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START)
510#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START)
511#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START)
512#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START)
513#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START)
514
515
425/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and 516/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
426 * 16 MPUIO lines */ 517 * 16 MPUIO lines */
427#define OMAP_MAX_GPIO_LINES 192 518#define OMAP_MAX_GPIO_LINES 192
@@ -467,6 +558,7 @@
467 558
468#ifndef __ASSEMBLY__ 559#ifndef __ASSEMBLY__
469extern void omap_init_irq(void); 560extern void omap_init_irq(void);
561extern int omap_irq_pending(void);
470#endif 562#endif
471 563
472#include <mach/hardware.h> 564#include <mach/hardware.h>
diff --git a/arch/arm/plat-omap/include/mach/keypad.h b/arch/arm/plat-omap/include/mach/keypad.h
index 232923aaf61d..45ea3ae3c995 100644
--- a/arch/arm/plat-omap/include/mach/keypad.h
+++ b/arch/arm/plat-omap/include/mach/keypad.h
@@ -33,7 +33,11 @@ struct omap_kp_platform_data {
33#define GROUP_3 (3 << 16) 33#define GROUP_3 (3 << 16)
34#define GROUP_MASK GROUP_3 34#define GROUP_MASK GROUP_3
35 35
36#define KEY_PERSISTENT 0x00800000
37#define KEYNUM_MASK 0x00EFFFFF
36#define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val)) 38#define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val))
39#define PERSISTENT_KEY(col, row) (((col) << 28) | ((row) << 24) | \
40 KEY_PERSISTENT)
37 41
38#endif 42#endif
39 43
diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/mach/memory.h
index 99ed564d9277..9ad41dc484c1 100644
--- a/arch/arm/plat-omap/include/mach/memory.h
+++ b/arch/arm/plat-omap/include/mach/memory.h
@@ -38,7 +38,8 @@
38 */ 38 */
39#if defined(CONFIG_ARCH_OMAP1) 39#if defined(CONFIG_ARCH_OMAP1)
40#define PHYS_OFFSET UL(0x10000000) 40#define PHYS_OFFSET UL(0x10000000)
41#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 41#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
42 defined(CONFIG_ARCH_OMAP4)
42#define PHYS_OFFSET UL(0x80000000) 43#define PHYS_OFFSET UL(0x80000000)
43#endif 44#endif
44 45
diff --git a/arch/arm/plat-omap/include/mach/omap24xx.h b/arch/arm/plat-omap/include/mach/omap24xx.h
index 24335d4932f5..696edfc145a6 100644
--- a/arch/arm/plat-omap/include/mach/omap24xx.h
+++ b/arch/arm/plat-omap/include/mach/omap24xx.h
@@ -85,23 +85,5 @@
85#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000) 85#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000)
86#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000) 86#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000)
87 87
88#if defined(CONFIG_ARCH_OMAP2420)
89
90#define OMAP2_32KSYNCT_BASE OMAP2420_32KSYNCT_BASE
91#define OMAP2_PRCM_BASE OMAP2420_PRCM_BASE
92#define OMAP2_CM_BASE OMAP2420_CM_BASE
93#define OMAP2_PRM_BASE OMAP2420_PRM_BASE
94#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)
95
96#elif defined(CONFIG_ARCH_OMAP2430)
97
98#define OMAP2_32KSYNCT_BASE OMAP2430_32KSYNCT_BASE
99#define OMAP2_PRCM_BASE OMAP2430_PRCM_BASE
100#define OMAP2_CM_BASE OMAP2430_CM_BASE
101#define OMAP2_PRM_BASE OMAP2430_PRM_BASE
102#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)
103
104#endif
105
106#endif /* __ASM_ARCH_OMAP24XX_H */ 88#endif /* __ASM_ARCH_OMAP24XX_H */
107 89
diff --git a/arch/arm/plat-omap/include/mach/omap34xx.h b/arch/arm/plat-omap/include/mach/omap34xx.h
index ab640151d3ec..f8d186a73712 100644
--- a/arch/arm/plat-omap/include/mach/omap34xx.h
+++ b/arch/arm/plat-omap/include/mach/omap34xx.h
@@ -31,13 +31,9 @@
31 31
32#define L4_34XX_BASE 0x48000000 32#define L4_34XX_BASE 0x48000000
33#define L4_WK_34XX_BASE 0x48300000 33#define L4_WK_34XX_BASE 0x48300000
34#define L4_WK_OMAP_BASE L4_WK_34XX_BASE
35#define L4_PER_34XX_BASE 0x49000000 34#define L4_PER_34XX_BASE 0x49000000
36#define L4_PER_OMAP_BASE L4_PER_34XX_BASE
37#define L4_EMU_34XX_BASE 0x54000000 35#define L4_EMU_34XX_BASE 0x54000000
38#define L4_EMU_BASE L4_EMU_34XX_BASE
39#define L3_34XX_BASE 0x68000000 36#define L3_34XX_BASE 0x68000000
40#define L3_OMAP_BASE L3_34XX_BASE
41 37
42#define OMAP3430_32KSYNCT_BASE 0x48320000 38#define OMAP3430_32KSYNCT_BASE 0x48320000
43#define OMAP3430_CM_BASE 0x48004800 39#define OMAP3430_CM_BASE 0x48004800
@@ -83,15 +79,6 @@
83 79
84#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000) 80#define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000)
85 81
86#if defined(CONFIG_ARCH_OMAP3430)
87
88#define OMAP2_32KSYNCT_BASE OMAP3430_32KSYNCT_BASE
89#define OMAP2_CM_BASE OMAP3430_CM_BASE
90#define OMAP2_PRM_BASE OMAP3430_PRM_BASE
91#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE)
92
93#endif
94
95#define OMAP34XX_DSP_BASE 0x58000000 82#define OMAP34XX_DSP_BASE 0x58000000
96#define OMAP34XX_DSP_MEM_BASE (OMAP34XX_DSP_BASE + 0x0) 83#define OMAP34XX_DSP_MEM_BASE (OMAP34XX_DSP_BASE + 0x0)
97#define OMAP34XX_DSP_IPI_BASE (OMAP34XX_DSP_BASE + 0x1000000) 84#define OMAP34XX_DSP_IPI_BASE (OMAP34XX_DSP_BASE + 0x1000000)
diff --git a/arch/arm/plat-omap/include/mach/omap44xx.h b/arch/arm/plat-omap/include/mach/omap44xx.h
new file mode 100644
index 000000000000..15dec7f1c7c0
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omap44xx.h
@@ -0,0 +1,46 @@
1/*:
2 * Address mappings and base address for OMAP4 interconnects
3 * and peripherals.
4 *
5 * Copyright (C) 2009 Texas Instruments
6 *
7 * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef __ASM_ARCH_OMAP44XX_H
14#define __ASM_ARCH_OMAP44XX_H
15
16/*
17 * Please place only base defines here and put the rest in device
18 * specific headers.
19 */
20#define L4_44XX_BASE 0x4a000000
21#define L4_WK_44XX_BASE 0x4a300000
22#define L4_PER_44XX_BASE 0x48000000
23#define L4_EMU_44XX_BASE 0x54000000
24#define L3_44XX_BASE 0x44000000
25#define OMAP4430_32KSYNCT_BASE 0x4a304000
26#define OMAP4430_CM_BASE 0x4a004000
27#define OMAP4430_PRM_BASE 0x48306000
28#define OMAP44XX_GPMC_BASE 0x50000000
29#define OMAP443X_SCM_BASE 0x4a002000
30#define OMAP443X_CTRL_BASE OMAP443X_SCM_BASE
31#define OMAP44XX_IC_BASE 0x48200000
32#define OMAP44XX_IVA_INTC_BASE 0x40000000
33#define IRQ_SIR_IRQ 0x0040
34#define OMAP44XX_GIC_DIST_BASE 0x48241000
35#define OMAP44XX_GIC_CPU_BASE 0x48240100
36#define OMAP44XX_VA_GIC_CPU_BASE IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
37#define OMAP44XX_SCU_BASE 0x48240000
38#define OMAP44XX_VA_SCU_BASE IO_ADDRESS(OMAP44XX_SCU_BASE)
39#define OMAP44XX_LOCAL_TWD_BASE 0x48240600
40#define OMAP44XX_VA_LOCAL_TWD_BASE IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE)
41#define OMAP44XX_LOCAL_TWD_SIZE 0x00000100
42#define OMAP44XX_WKUPGEN_BASE 0x48281000
43#define OMAP44XX_VA_WKUPGEN_BASE IO_ADDRESS(OMAP44XX_WKUPGEN_BASE)
44
45#endif /* __ASM_ARCH_OMAP44XX_H */
46
diff --git a/arch/arm/plat-omap/include/mach/onenand.h b/arch/arm/plat-omap/include/mach/onenand.h
index 4649d302c263..72f433d7d827 100644
--- a/arch/arm/plat-omap/include/mach/onenand.h
+++ b/arch/arm/plat-omap/include/mach/onenand.h
@@ -9,8 +9,12 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h> 13#include <linux/mtd/partitions.h>
13 14
15#define ONENAND_SYNC_READ (1 << 0)
16#define ONENAND_SYNC_READWRITE (1 << 1)
17
14struct omap_onenand_platform_data { 18struct omap_onenand_platform_data {
15 int cs; 19 int cs;
16 int gpio_irq; 20 int gpio_irq;
@@ -18,8 +22,22 @@ struct omap_onenand_platform_data {
18 int nr_parts; 22 int nr_parts;
19 int (*onenand_setup)(void __iomem *, int freq); 23 int (*onenand_setup)(void __iomem *, int freq);
20 int dma_channel; 24 int dma_channel;
25 u8 flags;
21}; 26};
22 27
23int omap2_onenand_rephase(void);
24
25#define ONENAND_MAX_PARTITIONS 8 28#define ONENAND_MAX_PARTITIONS 8
29
30#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
31 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
32
33extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
34
35#else
36
37#define board_onenand_data NULL
38
39static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
40{
41}
42
43#endif
diff --git a/arch/arm/plat-omap/include/mach/pm.h b/arch/arm/plat-omap/include/mach/pm.h
deleted file mode 100644
index ce6ee7927537..000000000000
--- a/arch/arm/plat-omap/include/mach/pm.h
+++ /dev/null
@@ -1,345 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/pm.h
3 *
4 * Header file for OMAP Power Management Routines
5 *
6 * Author: MontaVista Software, Inc.
7 * support@mvista.com
8 *
9 * Copyright 2002 MontaVista Software Inc.
10 *
11 * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 */
33
34#ifndef __ASM_ARCH_OMAP_PM_H
35#define __ASM_ARCH_OMAP_PM_H
36
37/*
38 * ----------------------------------------------------------------------------
39 * Register and offset definitions to be used in PM assembler code
40 * ----------------------------------------------------------------------------
41 */
42#define CLKGEN_REG_ASM_BASE IO_ADDRESS(0xfffece00)
43#define ARM_IDLECT1_ASM_OFFSET 0x04
44#define ARM_IDLECT2_ASM_OFFSET 0x08
45
46#define TCMIF_ASM_BASE IO_ADDRESS(0xfffecc00)
47#define EMIFS_CONFIG_ASM_OFFSET 0x0c
48#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20
49
50/*
51 * ----------------------------------------------------------------------------
52 * Power management bitmasks
53 * ----------------------------------------------------------------------------
54 */
55#define IDLE_WAIT_CYCLES 0x00000fff
56#define PERIPHERAL_ENABLE 0x2
57
58#define SELF_REFRESH_MODE 0x0c000001
59#define IDLE_EMIFS_REQUEST 0xc
60#define MODEM_32K_EN 0x1
61#define PER_EN 0x1
62
63#define CPU_SUSPEND_SIZE 200
64#define ULPD_LOW_PWR_EN 0x0001
65#define ULPD_DEEP_SLEEP_TRANSITION_EN 0x0010
66#define ULPD_SETUP_ANALOG_CELL_3_VAL 0
67#define ULPD_POWER_CTRL_REG_VAL 0x0219
68
69#define DSP_IDLE_DELAY 10
70#define DSP_IDLE 0x0040
71#define DSP_RST 0x0004
72#define DSP_ENABLE 0x0002
73#define SUFFICIENT_DSP_RESET_TIME 1000
74#define DEFAULT_MPUI_CONFIG 0x05cf
75#define ENABLE_XORCLK 0x2
76#define DSP_CLOCK_ENABLE 0x2000
77#define DSP_IDLE_MODE 0x2
78#define TC_IDLE_REQUEST (0x0000000c)
79
80#define IRQ_LEVEL2 (1<<0)
81#define IRQ_KEYBOARD (1<<1)
82#define IRQ_UART2 (1<<15)
83
84#define PDE_BIT 0x08
85#define PWD_EN_BIT 0x04
86#define EN_PERCK_BIT 0x04
87
88#define OMAP1510_DEEP_SLEEP_REQUEST 0x0ec7
89#define OMAP1510_BIG_SLEEP_REQUEST 0x0cc5
90#define OMAP1510_IDLE_LOOP_REQUEST 0x0c00
91#define OMAP1510_IDLE_CLOCK_DOMAINS 0x2
92
93/* Both big sleep and deep sleep use same values. Difference is in ULPD. */
94#define OMAP1610_IDLECT1_SLEEP_VAL 0x13c7
95#define OMAP1610_IDLECT2_SLEEP_VAL 0x09c7
96#define OMAP1610_IDLECT3_VAL 0x3f
97#define OMAP1610_IDLECT3_SLEEP_ORMASK 0x2c
98#define OMAP1610_IDLECT3 0xfffece24
99#define OMAP1610_IDLE_LOOP_REQUEST 0x0400
100
101#define OMAP730_IDLECT1_SLEEP_VAL 0x16c7
102#define OMAP730_IDLECT2_SLEEP_VAL 0x09c7
103#define OMAP730_IDLECT3_VAL 0x3f
104#define OMAP730_IDLECT3 0xfffece24
105#define OMAP730_IDLE_LOOP_REQUEST 0x0C00
106
107#if !defined(CONFIG_ARCH_OMAP730) && \
108 !defined(CONFIG_ARCH_OMAP15XX) && \
109 !defined(CONFIG_ARCH_OMAP16XX) && \
110 !defined(CONFIG_ARCH_OMAP24XX)
111#warning "Power management for this processor not implemented yet"
112#endif
113
114#ifndef __ASSEMBLER__
115
116#include <linux/clk.h>
117
118extern void prevent_idle_sleep(void);
119extern void allow_idle_sleep(void);
120
121extern void omap_pm_idle(void);
122extern void omap_pm_suspend(void);
123extern void omap730_cpu_suspend(unsigned short, unsigned short);
124extern void omap1510_cpu_suspend(unsigned short, unsigned short);
125extern void omap1610_cpu_suspend(unsigned short, unsigned short);
126extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
127 void __iomem *sdrc_power);
128extern void omap730_idle_loop_suspend(void);
129extern void omap1510_idle_loop_suspend(void);
130extern void omap1610_idle_loop_suspend(void);
131extern void omap24xx_idle_loop_suspend(void);
132
133extern unsigned int omap730_cpu_suspend_sz;
134extern unsigned int omap1510_cpu_suspend_sz;
135extern unsigned int omap1610_cpu_suspend_sz;
136extern unsigned int omap24xx_cpu_suspend_sz;
137extern unsigned int omap730_idle_loop_suspend_sz;
138extern unsigned int omap1510_idle_loop_suspend_sz;
139extern unsigned int omap1610_idle_loop_suspend_sz;
140extern unsigned int omap24xx_idle_loop_suspend_sz;
141
142#ifdef CONFIG_OMAP_SERIAL_WAKE
143extern void omap_serial_wake_trigger(int enable);
144#else
145#define omap_serial_wakeup_init() {}
146#define omap_serial_wake_trigger(x) {}
147#endif /* CONFIG_OMAP_SERIAL_WAKE */
148
149#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
150#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
151#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
152
153#define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x)
154#define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x))
155#define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x]
156
157#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
158#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
159#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
160
161#define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x)
162#define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x))
163#define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]
164
165#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
166#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
167#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
168
169#define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
170#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
171#define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
172
173#define OMAP24XX_SAVE(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] = x
174#define OMAP24XX_RESTORE(x) x = omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
175#define OMAP24XX_SHOW(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
176
177/*
178 * List of global OMAP registers to preserve.
179 * More ones like CP and general purpose register values are preserved
180 * with the stack pointer in sleep.S.
181 */
182
183enum arm_save_state {
184 ARM_SLEEP_SAVE_START = 0,
185 /*
186 * MPU control registers 32 bits
187 */
188 ARM_SLEEP_SAVE_ARM_CKCTL,
189 ARM_SLEEP_SAVE_ARM_IDLECT1,
190 ARM_SLEEP_SAVE_ARM_IDLECT2,
191 ARM_SLEEP_SAVE_ARM_IDLECT3,
192 ARM_SLEEP_SAVE_ARM_EWUPCT,
193 ARM_SLEEP_SAVE_ARM_RSTCT1,
194 ARM_SLEEP_SAVE_ARM_RSTCT2,
195 ARM_SLEEP_SAVE_ARM_SYSST,
196 ARM_SLEEP_SAVE_SIZE
197};
198
199enum dsp_save_state {
200 DSP_SLEEP_SAVE_START = 0,
201 /*
202 * DSP registers 16 bits
203 */
204 DSP_SLEEP_SAVE_DSP_IDLECT2,
205 DSP_SLEEP_SAVE_SIZE
206};
207
208enum ulpd_save_state {
209 ULPD_SLEEP_SAVE_START = 0,
210 /*
211 * ULPD registers 16 bits
212 */
213 ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
214 ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
215 ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
216 ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
217 ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
218 ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
219 ULPD_SLEEP_SAVE_SIZE
220};
221
222enum mpui1510_save_state {
223 MPUI1510_SLEEP_SAVE_START = 0,
224 /*
225 * MPUI registers 32 bits
226 */
227 MPUI1510_SLEEP_SAVE_MPUI_CTRL,
228 MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
229 MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
230 MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
231 MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
232 MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
233 MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
234 MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
235#if defined(CONFIG_ARCH_OMAP15XX)
236 MPUI1510_SLEEP_SAVE_SIZE
237#else
238 MPUI1510_SLEEP_SAVE_SIZE = 0
239#endif
240};
241
242enum mpui730_save_state {
243 MPUI730_SLEEP_SAVE_START = 0,
244 /*
245 * MPUI registers 32 bits
246 */
247 MPUI730_SLEEP_SAVE_MPUI_CTRL,
248 MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
249 MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
250 MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS,
251 MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
252 MPUI730_SLEEP_SAVE_EMIFS_CONFIG,
253 MPUI730_SLEEP_SAVE_OMAP_IH1_MIR,
254 MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR,
255 MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR,
256#if defined(CONFIG_ARCH_OMAP730)
257 MPUI730_SLEEP_SAVE_SIZE
258#else
259 MPUI730_SLEEP_SAVE_SIZE = 0
260#endif
261};
262
263enum mpui1610_save_state {
264 MPUI1610_SLEEP_SAVE_START = 0,
265 /*
266 * MPUI registers 32 bits
267 */
268 MPUI1610_SLEEP_SAVE_MPUI_CTRL,
269 MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
270 MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
271 MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
272 MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
273 MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
274 MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
275 MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
276 MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
277 MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
278 MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
279#if defined(CONFIG_ARCH_OMAP16XX)
280 MPUI1610_SLEEP_SAVE_SIZE
281#else
282 MPUI1610_SLEEP_SAVE_SIZE = 0
283#endif
284};
285
286enum omap24xx_save_state {
287 OMAP24XX_SLEEP_SAVE_START = 0,
288 OMAP24XX_SLEEP_SAVE_INTC_MIR0,
289 OMAP24XX_SLEEP_SAVE_INTC_MIR1,
290 OMAP24XX_SLEEP_SAVE_INTC_MIR2,
291
292 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MPU,
293 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_CORE,
294 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_GFX,
295 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_DSP,
296 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MDM,
297
298 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MPU,
299 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_CORE,
300 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_GFX,
301 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_DSP,
302 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MDM,
303
304 OMAP24XX_SLEEP_SAVE_CM_IDLEST1_CORE,
305 OMAP24XX_SLEEP_SAVE_CM_IDLEST2_CORE,
306 OMAP24XX_SLEEP_SAVE_CM_IDLEST3_CORE,
307 OMAP24XX_SLEEP_SAVE_CM_IDLEST4_CORE,
308 OMAP24XX_SLEEP_SAVE_CM_IDLEST_GFX,
309 OMAP24XX_SLEEP_SAVE_CM_IDLEST_WKUP,
310 OMAP24XX_SLEEP_SAVE_CM_IDLEST_CKGEN,
311 OMAP24XX_SLEEP_SAVE_CM_IDLEST_DSP,
312 OMAP24XX_SLEEP_SAVE_CM_IDLEST_MDM,
313
314 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE1_CORE,
315 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE2_CORE,
316 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE3_CORE,
317 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE4_CORE,
318 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_WKUP,
319 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_PLL,
320 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_DSP,
321 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_MDM,
322
323 OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE,
324 OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE,
325 OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE,
326 OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE,
327 OMAP24XX_SLEEP_SAVE_CM_ICLKEN3_CORE,
328 OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE,
329 OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1,
330 OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1,
331 OMAP24XX_SLEEP_SAVE_GPIO3_IRQENABLE1,
332 OMAP24XX_SLEEP_SAVE_GPIO4_IRQENABLE1,
333 OMAP24XX_SLEEP_SAVE_GPIO3_OE,
334 OMAP24XX_SLEEP_SAVE_GPIO4_OE,
335 OMAP24XX_SLEEP_SAVE_GPIO3_RISINGDETECT,
336 OMAP24XX_SLEEP_SAVE_GPIO3_FALLINGDETECT,
337 OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SPI1_NCS2,
338 OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_MCBSP1_DX,
339 OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SSI1_FLAG_TX,
340 OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQW0,
341 OMAP24XX_SLEEP_SAVE_SIZE
342};
343
344#endif /* ASSEMBLER */
345#endif /* __ASM_ARCH_OMAP_PM_H */
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h
index 8a676a04be48..13abd02d1527 100644
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ b/arch/arm/plat-omap/include/mach/serial.h
@@ -1,5 +1,8 @@
1/* 1/*
2 * arch/arm/plat-omap/include/mach/serial.h 2 * arch/arm/plat-omap/include/mach/serial.h
3 *
4 * Copyright (C) 2009 Texas Instruments
5 * Addded OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
3 * 6 *
4 * This program is distributed in the hope that it will be useful, 7 * This program is distributed in the hope that it will be useful,
5 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -15,19 +18,28 @@
15#define OMAP_UART1_BASE 0xfffb0000 18#define OMAP_UART1_BASE 0xfffb0000
16#define OMAP_UART2_BASE 0xfffb0800 19#define OMAP_UART2_BASE 0xfffb0800
17#define OMAP_UART3_BASE 0xfffb9800 20#define OMAP_UART3_BASE 0xfffb9800
21#define OMAP_MAX_NR_PORTS 3
18#elif defined(CONFIG_ARCH_OMAP2) 22#elif defined(CONFIG_ARCH_OMAP2)
19/* OMAP2 serial ports */ 23/* OMAP2 serial ports */
20#define OMAP_UART1_BASE 0x4806a000 24#define OMAP_UART1_BASE 0x4806a000
21#define OMAP_UART2_BASE 0x4806c000 25#define OMAP_UART2_BASE 0x4806c000
22#define OMAP_UART3_BASE 0x4806e000 26#define OMAP_UART3_BASE 0x4806e000
27#define OMAP_MAX_NR_PORTS 3
23#elif defined(CONFIG_ARCH_OMAP3) 28#elif defined(CONFIG_ARCH_OMAP3)
24/* OMAP3 serial ports */ 29/* OMAP3 serial ports */
25#define OMAP_UART1_BASE 0x4806a000 30#define OMAP_UART1_BASE 0x4806a000
26#define OMAP_UART2_BASE 0x4806c000 31#define OMAP_UART2_BASE 0x4806c000
27#define OMAP_UART3_BASE 0x49020000 32#define OMAP_UART3_BASE 0x49020000
33#define OMAP_MAX_NR_PORTS 3
34#elif defined(CONFIG_ARCH_OMAP4)
35/* OMAP4 serial ports */
36#define OMAP_UART1_BASE 0x4806a000
37#define OMAP_UART2_BASE 0x4806c000
38#define OMAP_UART3_BASE 0x48020000
39#define OMAP_UART4_BASE 0x4806e000
40#define OMAP_MAX_NR_PORTS 4
28#endif 41#endif
29 42
30#define OMAP_MAX_NR_PORTS 3
31#define OMAP1510_BASE_BAUD (12000000/16) 43#define OMAP1510_BASE_BAUD (12000000/16)
32#define OMAP16XX_BASE_BAUD (48000000/16) 44#define OMAP16XX_BASE_BAUD (48000000/16)
33#define OMAP24XX_BASE_BAUD (48000000/16) 45#define OMAP24XX_BASE_BAUD (48000000/16)
@@ -40,4 +52,13 @@
40 __ret; \ 52 __ret; \
41 }) 53 })
42 54
55#ifndef __ASSEMBLER__
56extern void omap_serial_init(void);
57extern int omap_uart_can_sleep(void);
58extern void omap_uart_check_wakeup(void);
59extern void omap_uart_prepare_suspend(void);
60extern void omap_uart_prepare_idle(int num);
61extern void omap_uart_resume_idle(int num);
62#endif
63
43#endif 64#endif
diff --git a/arch/arm/plat-omap/include/mach/smp.h b/arch/arm/plat-omap/include/mach/smp.h
new file mode 100644
index 000000000000..dcaa8fde7063
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/smp.h
@@ -0,0 +1,51 @@
1/*
2 * OMAP4 machine specific smp.h
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc.
5 *
6 * Author:
7 * Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * Interface functions needed for the SMP. This file is based on arm
10 * realview smp platform.
11 * Copyright (c) 2003 ARM Limited.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#ifndef OMAP_ARCH_SMP_H
18#define OMAP_ARCH_SMP_H
19
20#include <asm/hardware/gic.h>
21
22/*
23 * set_event() is used to wake up secondary core from wfe using sev. ROM
24 * code puts the second core into wfe(standby).
25 *
26 */
27#define set_event() __asm__ __volatile__ ("sev" : : : "memory")
28
29/* Needed for secondary core boot */
30extern void omap_secondary_startup(void);
31
32/*
33 * We use Soft IRQ1 as the IPI
34 */
35static inline void smp_cross_call(const struct cpumask *mask)
36{
37 gic_raise_softirq(mask, 1);
38}
39
40/*
41 * Read MPIDR: Multiprocessor affinity register
42 */
43#define hard_smp_processor_id() \
44 ({ \
45 unsigned int cpunum; \
46 __asm__("mrc p15, 0, %0, c0, c0, 5" \
47 : "=r" (cpunum)); \
48 cpunum &= 0x0F; \
49 })
50
51#endif
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
index ab35d622dcf5..dca7c16ae903 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -23,7 +23,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
23 23
24extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, 24extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
25 u32 sdrc_actim_ctrla, 25 u32 sdrc_actim_ctrla,
26 u32 sdrc_actim_ctrlb, u32 m2); 26 u32 sdrc_actim_ctrlb, u32 m2,
27 u32 unlock_dll);
27 28
28/* Do not use these */ 29/* Do not use these */
29extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); 30extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@@ -60,7 +61,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
60 61
61extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, 62extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
62 u32 sdrc_actim_ctrla, 63 u32 sdrc_actim_ctrla,
63 u32 sdrc_actim_ctrlb, u32 m2); 64 u32 sdrc_actim_ctrlb, u32 m2,
65 u32 unlock_dll);
64extern unsigned long omap3_sram_configure_core_dpll_sz; 66extern unsigned long omap3_sram_configure_core_dpll_sz;
65 67
66#endif 68#endif
diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/mach/usb.h
index 69f0ceed500b..f337e1761e2c 100644
--- a/arch/arm/plat-omap/include/mach/usb.h
+++ b/arch/arm/plat-omap/include/mach/usb.h
@@ -27,13 +27,7 @@
27#define UDC_BASE OMAP2_UDC_BASE 27#define UDC_BASE OMAP2_UDC_BASE
28#define OMAP_OHCI_BASE OMAP2_OHCI_BASE 28#define OMAP_OHCI_BASE OMAP2_OHCI_BASE
29 29
30#ifdef CONFIG_USB_MUSB_SOC
31extern void usb_musb_init(void); 30extern void usb_musb_init(void);
32#else
33static inline void usb_musb_init(void)
34{
35}
36#endif
37 31
38#endif 32#endif
39 33
diff --git a/arch/arm/plat-omap/include/mach/vmalloc.h b/arch/arm/plat-omap/include/mach/vmalloc.h
index dc104cd96197..b97dfafeebda 100644
--- a/arch/arm/plat-omap/include/mach/vmalloc.h
+++ b/arch/arm/plat-omap/include/mach/vmalloc.h
@@ -17,5 +17,5 @@
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20#define VMALLOC_END (PAGE_OFFSET + 0x10000000) 20#define VMALLOC_END (PAGE_OFFSET + 0x18000000)
21 21
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 08:25:21 -0500