4 files changed, 14 insertions, 127 deletions

diff --git a/arch/arm/plat-omap/include/mach/aic23.h b/arch/arm/plat-omap/include/mach/aic23.h
deleted file mode 100644
index 5ccedac77526..000000000000
--- a/arch/arm/plat-omap/include/mach/aic23.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/aic23.h
- *
- * Hardware definitions for TI TLV320AIC23 audio codec
- *
- * Copyright (C) 2002 RidgeRun, Inc.
- * Author: Steve Johnson
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_AIC23_H
-#define __ASM_ARCH_AIC23_H
-
-// Codec TLV320AIC23
-#define LEFT_LINE_VOLUME_ADDR           0x00
-#define RIGHT_LINE_VOLUME_ADDR          0x01
-#define LEFT_CHANNEL_VOLUME_ADDR        0x02
-#define RIGHT_CHANNEL_VOLUME_ADDR       0x03
-#define ANALOG_AUDIO_CONTROL_ADDR       0x04
-#define DIGITAL_AUDIO_CONTROL_ADDR      0x05
-#define POWER_DOWN_CONTROL_ADDR         0x06
-#define DIGITAL_AUDIO_FORMAT_ADDR       0x07
-#define SAMPLE_RATE_CONTROL_ADDR        0x08
-#define DIGITAL_INTERFACE_ACT_ADDR      0x09
-#define RESET_CONTROL_ADDR              0x0F
-
-// Left (right) line input volume control register
-#define LRS_ENABLED                     0x0100
-#define LIM_MUTED                       0x0080
-#define LIV_DEFAULT                     0x0017
-#define LIV_MAX                         0x001f
-#define LIV_MIN                         0x0000
-
-// Left (right) channel headphone volume control register
-#define LZC_ON                          0x0080
-#define LHV_DEFAULT                     0x0079
-#define LHV_MAX                         0x007f
-#define LHV_MIN                         0x0000
-
-// Analog audio path control register
-#define STA_REG(x)                      ((x)<<6)
-#define STE_ENABLED                     0x0020
-#define DAC_SELECTED                    0x0010
-#define BYPASS_ON                       0x0008
-#define INSEL_MIC                       0x0004
-#define MICM_MUTED                      0x0002
-#define MICB_20DB                       0x0001
-
-// Digital audio path control register
-#define DACM_MUTE                       0x0008
-#define DEEMP_32K                       0x0002
-#define DEEMP_44K                       0x0004
-#define DEEMP_48K                       0x0006
-#define ADCHP_ON                        0x0001
-
-// Power control down register
-#define DEVICE_POWER_OFF                0x0080
-#define CLK_OFF                         0x0040
-#define OSC_OFF                         0x0020
-#define OUT_OFF                         0x0010
-#define DAC_OFF                         0x0008
-#define ADC_OFF                         0x0004
-#define MIC_OFF                         0x0002
-#define LINE_OFF                        0x0001
-
-// Digital audio interface register
-#define MS_MASTER                       0x0040
-#define LRSWAP_ON                       0x0020
-#define LRP_ON                          0x0010
-#define IWL_16                          0x0000
-#define IWL_20                          0x0004
-#define IWL_24                          0x0008
-#define IWL_32                          0x000C
-#define FOR_I2S                         0x0002
-#define FOR_DSP                         0x0003
-
-// Sample rate control register
-#define CLKOUT_HALF                     0x0080
-#define CLKIN_HALF                      0x0040
-#define BOSR_384fs                      0x0002 // BOSR_272fs when in USB mode
-#define USB_CLK_ON                      0x0001
-#define SR_MASK                         0xf
-#define CLKOUT_SHIFT                    7
-#define CLKIN_SHIFT                     6
-#define SR_SHIFT                        2
-#define BOSR_SHIFT                      1
-
-// Digital interface register
-#define ACT_ON                          0x0001
-
-#define TLV320AIC23ID1                  (0x1a)  // cs low
-#define TLV320AIC23ID2                  (0x1b)  // cs high
-
-void aic23_power_up(void);
-void aic23_power_down(void);
-
-#endif /* __ASM_ARCH_AIC23_H */
diff --git a/arch/arm/plat-omap/include/mach/board-h3.h b/arch/arm/plat-omap/include/mach/board-h3.h
index 14909dc7858a..1888326da7ea 100644
--- a/arch/arm/plat-omap/include/mach/board-h3.h
+++ b/arch/arm/plat-omap/include/mach/board-h3.h
@@ -30,7 +30,9 @@
 /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
 #define OMAP1710_ETHR_START             0x04000300
 
+#define H3_TPS_GPIO_BASE                (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */)
+#       define H3_TPS_GPIO_MMC_PWR_EN   (H3_TPS_GPIO_BASE + 4)
+
 extern void h3_mmc_init(void);
-extern void h3_mmc_slot_cover_handler(void *arg, int state);
 
 #endif /*  __ASM_ARCH_OMAP_H3_H */
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h
index 04e68e88f134..8d9dfe314387 100644
--- a/arch/arm/plat-omap/include/mach/gpio.h
+++ b/arch/arm/plat-omap/include/mach/gpio.h
@@ -87,16 +87,6 @@ extern void omap_set_gpio_debounce_time(int gpio, int enable);
 #include <linux/errno.h>
 #include <asm-generic/gpio.h>
 
-static inline int omap_request_gpio(int gpio)
-{
-        return gpio_request(gpio, "FIXME");
-}
-
-static inline void omap_free_gpio(int gpio)
-{
-        gpio_free(gpio);
-}
-
 static inline int gpio_get_value(unsigned gpio)
 {
         return __gpio_get_value(gpio);
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
index 6a0d1a0a24a7..eef873db3d48 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -87,6 +87,10 @@
 #define OMAP_MCBSP_REG_XCERG    0x3A
 #define OMAP_MCBSP_REG_XCERH    0x3C
 
+/* Dummy defines, these are not available on omap1 */
+#define OMAP_MCBSP_REG_XCCR     0x00
+#define OMAP_MCBSP_REG_RCCR     0x00
+
 #define AUDIO_MCBSP_DATAWRITE   (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
 #define AUDIO_MCBSP_DATAREAD    (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
 
@@ -231,11 +235,16 @@
 #define XPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
 
 /*********************** McBSP XCCR bit definitions *************************/
+#define EXTCLKGATE              0x8000
+#define PPCONNECT               0x4000
+#define DXENDLY(value)          ((value)<<12)   /* Bits 12:13 */
+#define XFULL_CYCLE             0x0800
 #define DILB                    0x0020
 #define XDMAEN                  0x0008
 #define XDISABLE                0x0001
 
 /********************** McBSP RCCR bit definitions *************************/
+#define RFULL_CYCLE             0x0800
 #define RDMAEN                  0x0008
 #define RDISABLE                0x0001
 
@@ -267,6 +276,8 @@ struct omap_mcbsp_reg_cfg {
         u16 rcerh;
         u16 xcerg;
         u16 xcerh;
+        u16 xccr;
+        u16 rccr;
 };
 
 typedef enum {