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-rw-r--r--arch/arm/plat-omap/include/mach/sdrc.h15
1 files changed, 12 insertions, 3 deletions
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
index 0be18e4ff182..1c09c78a48f2 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -21,19 +21,28 @@
21/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */ 21/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
22 22
23#define SDRC_SYSCONFIG 0x010 23#define SDRC_SYSCONFIG 0x010
24#define SDRC_CS_CFG 0x040
25#define SDRC_SHARING 0x044
26#define SDRC_ERR_TYPE 0x04C
24#define SDRC_DLLA_CTRL 0x060 27#define SDRC_DLLA_CTRL 0x060
25#define SDRC_DLLA_STATUS 0x064 28#define SDRC_DLLA_STATUS 0x064
26#define SDRC_DLLB_CTRL 0x068 29#define SDRC_DLLB_CTRL 0x068
27#define SDRC_DLLB_STATUS 0x06C 30#define SDRC_DLLB_STATUS 0x06C
28#define SDRC_POWER 0x070 31#define SDRC_POWER 0x070
32#define SDRC_MCFG_0 0x080
29#define SDRC_MR_0 0x084 33#define SDRC_MR_0 0x084
34#define SDRC_EMR2_0 0x08c
30#define SDRC_ACTIM_CTRL_A_0 0x09c 35#define SDRC_ACTIM_CTRL_A_0 0x09c
31#define SDRC_ACTIM_CTRL_B_0 0x0a0 36#define SDRC_ACTIM_CTRL_B_0 0x0a0
32#define SDRC_RFR_CTRL_0 0x0a4 37#define SDRC_RFR_CTRL_0 0x0a4
38#define SDRC_MANUAL_0 0x0a8
39#define SDRC_MCFG_1 0x0B0
33#define SDRC_MR_1 0x0B4 40#define SDRC_MR_1 0x0B4
41#define SDRC_EMR2_1 0x0BC
34#define SDRC_ACTIM_CTRL_A_1 0x0C4 42#define SDRC_ACTIM_CTRL_A_1 0x0C4
35#define SDRC_ACTIM_CTRL_B_1 0x0C8 43#define SDRC_ACTIM_CTRL_B_1 0x0C8
36#define SDRC_RFR_CTRL_1 0x0D4 44#define SDRC_RFR_CTRL_1 0x0D4
45#define SDRC_MANUAL_1 0x0D8
37 46
38/* 47/*
39 * These values represent the number of memory clock cycles between 48 * These values represent the number of memory clock cycles between
@@ -71,11 +80,11 @@
71 */ 80 */
72 81
73#define OMAP242X_SMS_REGADDR(reg) \ 82#define OMAP242X_SMS_REGADDR(reg) \
74 (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg) 83 (void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
75#define OMAP243X_SMS_REGADDR(reg) \ 84#define OMAP243X_SMS_REGADDR(reg) \
76 (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg) 85 (void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
77#define OMAP343X_SMS_REGADDR(reg) \ 86#define OMAP343X_SMS_REGADDR(reg) \
78 (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg) 87 (void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
79 88
80/* SMS register offsets - read/write with sms_{read,write}_reg() */ 89/* SMS register offsets - read/write with sms_{read,write}_reg() */
81 90