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Diffstat (limited to 'arch/arm/plat-omap/gpio.c')
-rw-r--r--arch/arm/plat-omap/gpio.c115
1 files changed, 67 insertions, 48 deletions
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 176c86e5531d..693839c89ad0 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -31,7 +31,7 @@
31/* 31/*
32 * OMAP1510 GPIO registers 32 * OMAP1510 GPIO registers
33 */ 33 */
34#define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000) 34#define OMAP1510_GPIO_BASE OMAP1_IO_ADDRESS(0xfffce000)
35#define OMAP1510_GPIO_DATA_INPUT 0x00 35#define OMAP1510_GPIO_DATA_INPUT 0x00
36#define OMAP1510_GPIO_DATA_OUTPUT 0x04 36#define OMAP1510_GPIO_DATA_OUTPUT 0x04
37#define OMAP1510_GPIO_DIR_CONTROL 0x08 37#define OMAP1510_GPIO_DIR_CONTROL 0x08
@@ -45,10 +45,10 @@
45/* 45/*
46 * OMAP1610 specific GPIO registers 46 * OMAP1610 specific GPIO registers
47 */ 47 */
48#define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400) 48#define OMAP1610_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbe400)
49#define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00) 49#define OMAP1610_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbec00)
50#define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400) 50#define OMAP1610_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbb400)
51#define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00) 51#define OMAP1610_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbbc00)
52#define OMAP1610_GPIO_REVISION 0x0000 52#define OMAP1610_GPIO_REVISION 0x0000
53#define OMAP1610_GPIO_SYSCONFIG 0x0010 53#define OMAP1610_GPIO_SYSCONFIG 0x0010
54#define OMAP1610_GPIO_SYSSTATUS 0x0014 54#define OMAP1610_GPIO_SYSSTATUS 0x0014
@@ -70,12 +70,12 @@
70/* 70/*
71 * OMAP730 specific GPIO registers 71 * OMAP730 specific GPIO registers
72 */ 72 */
73#define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000) 73#define OMAP730_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
74#define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800) 74#define OMAP730_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
75#define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000) 75#define OMAP730_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
76#define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800) 76#define OMAP730_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
77#define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000) 77#define OMAP730_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
78#define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800) 78#define OMAP730_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
79#define OMAP730_GPIO_DATA_INPUT 0x00 79#define OMAP730_GPIO_DATA_INPUT 0x00
80#define OMAP730_GPIO_DATA_OUTPUT 0x04 80#define OMAP730_GPIO_DATA_OUTPUT 0x04
81#define OMAP730_GPIO_DIR_CONTROL 0x08 81#define OMAP730_GPIO_DIR_CONTROL 0x08
@@ -86,12 +86,12 @@
86/* 86/*
87 * OMAP850 specific GPIO registers 87 * OMAP850 specific GPIO registers
88 */ 88 */
89#define OMAP850_GPIO1_BASE IO_ADDRESS(0xfffbc000) 89#define OMAP850_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
90#define OMAP850_GPIO2_BASE IO_ADDRESS(0xfffbc800) 90#define OMAP850_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
91#define OMAP850_GPIO3_BASE IO_ADDRESS(0xfffbd000) 91#define OMAP850_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
92#define OMAP850_GPIO4_BASE IO_ADDRESS(0xfffbd800) 92#define OMAP850_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
93#define OMAP850_GPIO5_BASE IO_ADDRESS(0xfffbe000) 93#define OMAP850_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
94#define OMAP850_GPIO6_BASE IO_ADDRESS(0xfffbe800) 94#define OMAP850_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
95#define OMAP850_GPIO_DATA_INPUT 0x00 95#define OMAP850_GPIO_DATA_INPUT 0x00
96#define OMAP850_GPIO_DATA_OUTPUT 0x04 96#define OMAP850_GPIO_DATA_OUTPUT 0x04
97#define OMAP850_GPIO_DIR_CONTROL 0x08 97#define OMAP850_GPIO_DIR_CONTROL 0x08
@@ -99,19 +99,21 @@
99#define OMAP850_GPIO_INT_MASK 0x10 99#define OMAP850_GPIO_INT_MASK 0x10
100#define OMAP850_GPIO_INT_STATUS 0x14 100#define OMAP850_GPIO_INT_STATUS 0x14
101 101
102#define OMAP1_MPUIO_VBASE OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE)
103
102/* 104/*
103 * omap24xx specific GPIO registers 105 * omap24xx specific GPIO registers
104 */ 106 */
105#define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000) 107#define OMAP242X_GPIO1_BASE OMAP2_IO_ADDRESS(0x48018000)
106#define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000) 108#define OMAP242X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4801a000)
107#define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000) 109#define OMAP242X_GPIO3_BASE OMAP2_IO_ADDRESS(0x4801c000)
108#define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000) 110#define OMAP242X_GPIO4_BASE OMAP2_IO_ADDRESS(0x4801e000)
109 111
110#define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000) 112#define OMAP243X_GPIO1_BASE OMAP2_IO_ADDRESS(0x4900C000)
111#define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000) 113#define OMAP243X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4900E000)
112#define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000) 114#define OMAP243X_GPIO3_BASE OMAP2_IO_ADDRESS(0x49010000)
113#define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000) 115#define OMAP243X_GPIO4_BASE OMAP2_IO_ADDRESS(0x49012000)
114#define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000) 116#define OMAP243X_GPIO5_BASE OMAP2_IO_ADDRESS(0x480B6000)
115 117
116#define OMAP24XX_GPIO_REVISION 0x0000 118#define OMAP24XX_GPIO_REVISION 0x0000
117#define OMAP24XX_GPIO_SYSCONFIG 0x0010 119#define OMAP24XX_GPIO_SYSCONFIG 0x0010
@@ -168,24 +170,22 @@
168 * omap34xx specific GPIO registers 170 * omap34xx specific GPIO registers
169 */ 171 */
170 172
171#define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000) 173#define OMAP34XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x48310000)
172#define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000) 174#define OMAP34XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x49050000)
173#define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000) 175#define OMAP34XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x49052000)
174#define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000) 176#define OMAP34XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x49054000)
175#define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000) 177#define OMAP34XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x49056000)
176#define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000) 178#define OMAP34XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x49058000)
177 179
178/* 180/*
179 * OMAP44XX specific GPIO registers 181 * OMAP44XX specific GPIO registers
180 */ 182 */
181#define OMAP44XX_GPIO1_BASE IO_ADDRESS(0x4a310000) 183#define OMAP44XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x4a310000)
182#define OMAP44XX_GPIO2_BASE IO_ADDRESS(0x48055000) 184#define OMAP44XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x48055000)
183#define OMAP44XX_GPIO3_BASE IO_ADDRESS(0x48057000) 185#define OMAP44XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x48057000)
184#define OMAP44XX_GPIO4_BASE IO_ADDRESS(0x48059000) 186#define OMAP44XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x48059000)
185#define OMAP44XX_GPIO5_BASE IO_ADDRESS(0x4805B000) 187#define OMAP44XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x4805B000)
186#define OMAP44XX_GPIO6_BASE IO_ADDRESS(0x4805D000) 188#define OMAP44XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x4805D000)
187
188#define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
189 189
190struct gpio_bank { 190struct gpio_bank {
191 void __iomem *base; 191 void __iomem *base;
@@ -221,7 +221,7 @@ struct gpio_bank {
221 221
222#ifdef CONFIG_ARCH_OMAP16XX 222#ifdef CONFIG_ARCH_OMAP16XX
223static struct gpio_bank gpio_bank_1610[5] = { 223static struct gpio_bank gpio_bank_1610[5] = {
224 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, 224 { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
225 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, 225 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
226 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, 226 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
227 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, 227 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
@@ -231,14 +231,14 @@ static struct gpio_bank gpio_bank_1610[5] = {
231 231
232#ifdef CONFIG_ARCH_OMAP15XX 232#ifdef CONFIG_ARCH_OMAP15XX
233static struct gpio_bank gpio_bank_1510[2] = { 233static struct gpio_bank gpio_bank_1510[2] = {
234 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 234 { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
235 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } 235 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
236}; 236};
237#endif 237#endif
238 238
239#ifdef CONFIG_ARCH_OMAP730 239#ifdef CONFIG_ARCH_OMAP730
240static struct gpio_bank gpio_bank_730[7] = { 240static struct gpio_bank gpio_bank_730[7] = {
241 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 241 { OMAP1_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
242 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, 242 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
243 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, 243 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
244 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, 244 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
@@ -250,7 +250,7 @@ static struct gpio_bank gpio_bank_730[7] = {
250 250
251#ifdef CONFIG_ARCH_OMAP850 251#ifdef CONFIG_ARCH_OMAP850
252static struct gpio_bank gpio_bank_850[7] = { 252static struct gpio_bank gpio_bank_850[7] = {
253 { OMAP_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 253 { OMAP1_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
254 { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 }, 254 { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 },
255 { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 }, 255 { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 },
256 { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 }, 256 { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 },
@@ -2032,7 +2032,7 @@ void omap2_gpio_resume_after_retention(void)
2032 return; 2032 return;
2033 for (i = 0; i < gpio_bank_count; i++) { 2033 for (i = 0; i < gpio_bank_count; i++) {
2034 struct gpio_bank *bank = &gpio_bank[i]; 2034 struct gpio_bank *bank = &gpio_bank[i];
2035 u32 l; 2035 u32 l, gen, gen0, gen1;
2036 2036
2037 if (!(bank->enabled_non_wakeup_gpios)) 2037 if (!(bank->enabled_non_wakeup_gpios))
2038 continue; 2038 continue;
@@ -2056,13 +2056,32 @@ void omap2_gpio_resume_after_retention(void)
2056 * this silicon bug. */ 2056 * this silicon bug. */
2057 l ^= bank->saved_datain; 2057 l ^= bank->saved_datain;
2058 l &= bank->non_wakeup_gpios; 2058 l &= bank->non_wakeup_gpios;
2059 if (l) { 2059
2060 /*
2061 * No need to generate IRQs for the rising edge for gpio IRQs
2062 * configured with falling edge only; and vice versa.
2063 */
2064 gen0 = l & bank->saved_fallingdetect;
2065 gen0 &= bank->saved_datain;
2066
2067 gen1 = l & bank->saved_risingdetect;
2068 gen1 &= ~(bank->saved_datain);
2069
2070 /* FIXME: Consider GPIO IRQs with level detections properly! */
2071 gen = l & (~(bank->saved_fallingdetect) &
2072 ~(bank->saved_risingdetect));
2073 /* Consider all GPIO IRQs needed to be updated */
2074 gen |= gen0 | gen1;
2075
2076 if (gen) {
2060 u32 old0, old1; 2077 u32 old0, old1;
2061#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 2078#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2062 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); 2079 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2063 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); 2080 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2064 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0); 2081 __raw_writel(old0 | gen, bank->base +
2065 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1); 2082 OMAP24XX_GPIO_LEVELDETECT0);
2083 __raw_writel(old1 | gen, bank->base +
2084 OMAP24XX_GPIO_LEVELDETECT1);
2066 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); 2085 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2067 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); 2086 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2068#endif 2087#endif