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-rw-r--r--arch/arm/plat-omap/gpio.c549
1 files changed, 301 insertions, 248 deletions
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 7c345b757df1..055160e0620e 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -31,7 +31,7 @@
31/* 31/*
32 * OMAP1510 GPIO registers 32 * OMAP1510 GPIO registers
33 */ 33 */
34#define OMAP1510_GPIO_BASE OMAP1_IO_ADDRESS(0xfffce000) 34#define OMAP1510_GPIO_BASE 0xfffce000
35#define OMAP1510_GPIO_DATA_INPUT 0x00 35#define OMAP1510_GPIO_DATA_INPUT 0x00
36#define OMAP1510_GPIO_DATA_OUTPUT 0x04 36#define OMAP1510_GPIO_DATA_OUTPUT 0x04
37#define OMAP1510_GPIO_DIR_CONTROL 0x08 37#define OMAP1510_GPIO_DIR_CONTROL 0x08
@@ -45,10 +45,10 @@
45/* 45/*
46 * OMAP1610 specific GPIO registers 46 * OMAP1610 specific GPIO registers
47 */ 47 */
48#define OMAP1610_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbe400) 48#define OMAP1610_GPIO1_BASE 0xfffbe400
49#define OMAP1610_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbec00) 49#define OMAP1610_GPIO2_BASE 0xfffbec00
50#define OMAP1610_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbb400) 50#define OMAP1610_GPIO3_BASE 0xfffbb400
51#define OMAP1610_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbbc00) 51#define OMAP1610_GPIO4_BASE 0xfffbbc00
52#define OMAP1610_GPIO_REVISION 0x0000 52#define OMAP1610_GPIO_REVISION 0x0000
53#define OMAP1610_GPIO_SYSCONFIG 0x0010 53#define OMAP1610_GPIO_SYSCONFIG 0x0010
54#define OMAP1610_GPIO_SYSSTATUS 0x0014 54#define OMAP1610_GPIO_SYSSTATUS 0x0014
@@ -68,52 +68,36 @@
68#define OMAP1610_GPIO_SET_DATAOUT 0x00f0 68#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69 69
70/* 70/*
71 * OMAP730 specific GPIO registers 71 * OMAP7XX specific GPIO registers
72 */ 72 */
73#define OMAP730_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000) 73#define OMAP7XX_GPIO1_BASE 0xfffbc000
74#define OMAP730_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800) 74#define OMAP7XX_GPIO2_BASE 0xfffbc800
75#define OMAP730_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000) 75#define OMAP7XX_GPIO3_BASE 0xfffbd000
76#define OMAP730_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800) 76#define OMAP7XX_GPIO4_BASE 0xfffbd800
77#define OMAP730_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000) 77#define OMAP7XX_GPIO5_BASE 0xfffbe000
78#define OMAP730_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800) 78#define OMAP7XX_GPIO6_BASE 0xfffbe800
79#define OMAP730_GPIO_DATA_INPUT 0x00 79#define OMAP7XX_GPIO_DATA_INPUT 0x00
80#define OMAP730_GPIO_DATA_OUTPUT 0x04 80#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
81#define OMAP730_GPIO_DIR_CONTROL 0x08 81#define OMAP7XX_GPIO_DIR_CONTROL 0x08
82#define OMAP730_GPIO_INT_CONTROL 0x0c 82#define OMAP7XX_GPIO_INT_CONTROL 0x0c
83#define OMAP730_GPIO_INT_MASK 0x10 83#define OMAP7XX_GPIO_INT_MASK 0x10
84#define OMAP730_GPIO_INT_STATUS 0x14 84#define OMAP7XX_GPIO_INT_STATUS 0x14
85 85
86/* 86#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
87 * OMAP850 specific GPIO registers
88 */
89#define OMAP850_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
90#define OMAP850_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
91#define OMAP850_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
92#define OMAP850_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
93#define OMAP850_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
94#define OMAP850_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
95#define OMAP850_GPIO_DATA_INPUT 0x00
96#define OMAP850_GPIO_DATA_OUTPUT 0x04
97#define OMAP850_GPIO_DIR_CONTROL 0x08
98#define OMAP850_GPIO_INT_CONTROL 0x0c
99#define OMAP850_GPIO_INT_MASK 0x10
100#define OMAP850_GPIO_INT_STATUS 0x14
101
102#define OMAP1_MPUIO_VBASE OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE)
103 87
104/* 88/*
105 * omap24xx specific GPIO registers 89 * omap24xx specific GPIO registers
106 */ 90 */
107#define OMAP242X_GPIO1_BASE OMAP2_IO_ADDRESS(0x48018000) 91#define OMAP242X_GPIO1_BASE 0x48018000
108#define OMAP242X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4801a000) 92#define OMAP242X_GPIO2_BASE 0x4801a000
109#define OMAP242X_GPIO3_BASE OMAP2_IO_ADDRESS(0x4801c000) 93#define OMAP242X_GPIO3_BASE 0x4801c000
110#define OMAP242X_GPIO4_BASE OMAP2_IO_ADDRESS(0x4801e000) 94#define OMAP242X_GPIO4_BASE 0x4801e000
111 95
112#define OMAP243X_GPIO1_BASE OMAP2_IO_ADDRESS(0x4900C000) 96#define OMAP243X_GPIO1_BASE 0x4900C000
113#define OMAP243X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4900E000) 97#define OMAP243X_GPIO2_BASE 0x4900E000
114#define OMAP243X_GPIO3_BASE OMAP2_IO_ADDRESS(0x49010000) 98#define OMAP243X_GPIO3_BASE 0x49010000
115#define OMAP243X_GPIO4_BASE OMAP2_IO_ADDRESS(0x49012000) 99#define OMAP243X_GPIO4_BASE 0x49012000
116#define OMAP243X_GPIO5_BASE OMAP2_IO_ADDRESS(0x480B6000) 100#define OMAP243X_GPIO5_BASE 0x480B6000
117 101
118#define OMAP24XX_GPIO_REVISION 0x0000 102#define OMAP24XX_GPIO_REVISION 0x0000
119#define OMAP24XX_GPIO_SYSCONFIG 0x0010 103#define OMAP24XX_GPIO_SYSCONFIG 0x0010
@@ -170,24 +154,25 @@
170 * omap34xx specific GPIO registers 154 * omap34xx specific GPIO registers
171 */ 155 */
172 156
173#define OMAP34XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x48310000) 157#define OMAP34XX_GPIO1_BASE 0x48310000
174#define OMAP34XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x49050000) 158#define OMAP34XX_GPIO2_BASE 0x49050000
175#define OMAP34XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x49052000) 159#define OMAP34XX_GPIO3_BASE 0x49052000
176#define OMAP34XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x49054000) 160#define OMAP34XX_GPIO4_BASE 0x49054000
177#define OMAP34XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x49056000) 161#define OMAP34XX_GPIO5_BASE 0x49056000
178#define OMAP34XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x49058000) 162#define OMAP34XX_GPIO6_BASE 0x49058000
179 163
180/* 164/*
181 * OMAP44XX specific GPIO registers 165 * OMAP44XX specific GPIO registers
182 */ 166 */
183#define OMAP44XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x4a310000) 167#define OMAP44XX_GPIO1_BASE 0x4a310000
184#define OMAP44XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x48055000) 168#define OMAP44XX_GPIO2_BASE 0x48055000
185#define OMAP44XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x48057000) 169#define OMAP44XX_GPIO3_BASE 0x48057000
186#define OMAP44XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x48059000) 170#define OMAP44XX_GPIO4_BASE 0x48059000
187#define OMAP44XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x4805B000) 171#define OMAP44XX_GPIO5_BASE 0x4805B000
188#define OMAP44XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x4805D000) 172#define OMAP44XX_GPIO6_BASE 0x4805D000
189 173
190struct gpio_bank { 174struct gpio_bank {
175 unsigned long pbase;
191 void __iomem *base; 176 void __iomem *base;
192 u16 irq; 177 u16 irq;
193 u16 virtual_irq_start; 178 u16 virtual_irq_start;
@@ -210,101 +195,134 @@ struct gpio_bank {
210 spinlock_t lock; 195 spinlock_t lock;
211 struct gpio_chip chip; 196 struct gpio_chip chip;
212 struct clk *dbck; 197 struct clk *dbck;
198 u32 mod_usage;
213}; 199};
214 200
215#define METHOD_MPUIO 0 201#define METHOD_MPUIO 0
216#define METHOD_GPIO_1510 1 202#define METHOD_GPIO_1510 1
217#define METHOD_GPIO_1610 2 203#define METHOD_GPIO_1610 2
218#define METHOD_GPIO_730 3 204#define METHOD_GPIO_7XX 3
219#define METHOD_GPIO_850 4
220#define METHOD_GPIO_24XX 5 205#define METHOD_GPIO_24XX 5
221 206
222#ifdef CONFIG_ARCH_OMAP16XX 207#ifdef CONFIG_ARCH_OMAP16XX
223static struct gpio_bank gpio_bank_1610[5] = { 208static struct gpio_bank gpio_bank_1610[5] = {
224 { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, 209 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
225 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, 210 METHOD_MPUIO },
226 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, 211 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
227 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, 212 METHOD_GPIO_1610 },
228 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 }, 213 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
214 METHOD_GPIO_1610 },
215 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
216 METHOD_GPIO_1610 },
217 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
218 METHOD_GPIO_1610 },
229}; 219};
230#endif 220#endif
231 221
232#ifdef CONFIG_ARCH_OMAP15XX 222#ifdef CONFIG_ARCH_OMAP15XX
233static struct gpio_bank gpio_bank_1510[2] = { 223static struct gpio_bank gpio_bank_1510[2] = {
234 { OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 224 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
235 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } 225 METHOD_MPUIO },
236}; 226 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
237#endif 227 METHOD_GPIO_1510 }
238
239#ifdef CONFIG_ARCH_OMAP730
240static struct gpio_bank gpio_bank_730[7] = {
241 { OMAP1_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
242 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
243 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
244 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
245 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
246 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
247 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
248}; 228};
249#endif 229#endif
250 230
251#ifdef CONFIG_ARCH_OMAP850 231#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
252static struct gpio_bank gpio_bank_850[7] = { 232static struct gpio_bank gpio_bank_7xx[7] = {
253 { OMAP1_MPUIO_VBASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 233 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
254 { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 }, 234 METHOD_MPUIO },
255 { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 }, 235 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
256 { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 }, 236 METHOD_GPIO_7XX },
257 { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 }, 237 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
258 { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 }, 238 METHOD_GPIO_7XX },
259 { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 }, 239 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
240 METHOD_GPIO_7XX },
241 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
242 METHOD_GPIO_7XX },
243 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
244 METHOD_GPIO_7XX },
245 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
246 METHOD_GPIO_7XX },
260}; 247};
261#endif 248#endif
262 249
263
264#ifdef CONFIG_ARCH_OMAP24XX 250#ifdef CONFIG_ARCH_OMAP24XX
265 251
266static struct gpio_bank gpio_bank_242x[4] = { 252static struct gpio_bank gpio_bank_242x[4] = {
267 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, 253 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
268 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, 254 METHOD_GPIO_24XX },
269 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, 255 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
270 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, 256 METHOD_GPIO_24XX },
257 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
258 METHOD_GPIO_24XX },
259 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
260 METHOD_GPIO_24XX },
271}; 261};
272 262
273static struct gpio_bank gpio_bank_243x[5] = { 263static struct gpio_bank gpio_bank_243x[5] = {
274 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, 264 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
275 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, 265 METHOD_GPIO_24XX },
276 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, 266 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
277 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, 267 METHOD_GPIO_24XX },
278 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, 268 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
269 METHOD_GPIO_24XX },
270 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
271 METHOD_GPIO_24XX },
272 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
273 METHOD_GPIO_24XX },
279}; 274};
280 275
281#endif 276#endif
282 277
283#ifdef CONFIG_ARCH_OMAP34XX 278#ifdef CONFIG_ARCH_OMAP34XX
284static struct gpio_bank gpio_bank_34xx[6] = { 279static struct gpio_bank gpio_bank_34xx[6] = {
285 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, 280 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
286 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, 281 METHOD_GPIO_24XX },
287 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, 282 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
288 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, 283 METHOD_GPIO_24XX },
289 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, 284 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
290 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX }, 285 METHOD_GPIO_24XX },
286 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
287 METHOD_GPIO_24XX },
288 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
289 METHOD_GPIO_24XX },
290 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
291 METHOD_GPIO_24XX },
291}; 292};
292 293
294struct omap3_gpio_regs {
295 u32 sysconfig;
296 u32 irqenable1;
297 u32 irqenable2;
298 u32 wake_en;
299 u32 ctrl;
300 u32 oe;
301 u32 leveldetect0;
302 u32 leveldetect1;
303 u32 risingdetect;
304 u32 fallingdetect;
305 u32 dataout;
306 u32 setwkuena;
307 u32 setdataout;
308};
309
310static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
293#endif 311#endif
294 312
295#ifdef CONFIG_ARCH_OMAP4 313#ifdef CONFIG_ARCH_OMAP4
296static struct gpio_bank gpio_bank_44xx[6] = { 314static struct gpio_bank gpio_bank_44xx[6] = {
297 { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, \ 315 { OMAP44XX_GPIO1_BASE, NULL, INT_44XX_GPIO_BANK1, IH_GPIO_BASE,
298 METHOD_GPIO_24XX }, 316 METHOD_GPIO_24XX },
299 { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, \ 317 { OMAP44XX_GPIO2_BASE, NULL, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32,
300 METHOD_GPIO_24XX }, 318 METHOD_GPIO_24XX },
301 { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, \ 319 { OMAP44XX_GPIO3_BASE, NULL, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64,
302 METHOD_GPIO_24XX }, 320 METHOD_GPIO_24XX },
303 { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, \ 321 { OMAP44XX_GPIO4_BASE, NULL, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96,
304 METHOD_GPIO_24XX }, 322 METHOD_GPIO_24XX },
305 { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \ 323 { OMAP44XX_GPIO5_BASE, NULL, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128,
306 METHOD_GPIO_24XX }, 324 METHOD_GPIO_24XX },
307 { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \ 325 { OMAP44XX_GPIO6_BASE, NULL, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160,
308 METHOD_GPIO_24XX }, 326 METHOD_GPIO_24XX },
309}; 327};
310 328
@@ -402,14 +420,9 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
402 reg += OMAP1610_GPIO_DIRECTION; 420 reg += OMAP1610_GPIO_DIRECTION;
403 break; 421 break;
404#endif 422#endif
405#ifdef CONFIG_ARCH_OMAP730 423#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
406 case METHOD_GPIO_730: 424 case METHOD_GPIO_7XX:
407 reg += OMAP730_GPIO_DIR_CONTROL; 425 reg += OMAP7XX_GPIO_DIR_CONTROL;
408 break;
409#endif
410#ifdef CONFIG_ARCH_OMAP850
411 case METHOD_GPIO_850:
412 reg += OMAP850_GPIO_DIR_CONTROL;
413 break; 426 break;
414#endif 427#endif
415#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 428#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
@@ -469,19 +482,9 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
469 l = 1 << gpio; 482 l = 1 << gpio;
470 break; 483 break;
471#endif 484#endif
472#ifdef CONFIG_ARCH_OMAP730 485#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
473 case METHOD_GPIO_730: 486 case METHOD_GPIO_7XX:
474 reg += OMAP730_GPIO_DATA_OUTPUT; 487 reg += OMAP7XX_GPIO_DATA_OUTPUT;
475 l = __raw_readl(reg);
476 if (enable)
477 l |= 1 << gpio;
478 else
479 l &= ~(1 << gpio);
480 break;
481#endif
482#ifdef CONFIG_ARCH_OMAP850
483 case METHOD_GPIO_850:
484 reg += OMAP850_GPIO_DATA_OUTPUT;
485 l = __raw_readl(reg); 488 l = __raw_readl(reg);
486 if (enable) 489 if (enable)
487 l |= 1 << gpio; 490 l |= 1 << gpio;
@@ -537,14 +540,9 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
537 reg += OMAP1610_GPIO_DATAIN; 540 reg += OMAP1610_GPIO_DATAIN;
538 break; 541 break;
539#endif 542#endif
540#ifdef CONFIG_ARCH_OMAP730 543#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
541 case METHOD_GPIO_730: 544 case METHOD_GPIO_7XX:
542 reg += OMAP730_GPIO_DATA_INPUT; 545 reg += OMAP7XX_GPIO_DATA_INPUT;
543 break;
544#endif
545#ifdef CONFIG_ARCH_OMAP850
546 case METHOD_GPIO_850:
547 reg += OMAP850_GPIO_DATA_INPUT;
548 break; 546 break;
549#endif 547#endif
550#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 548#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
@@ -588,14 +586,9 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
588 reg += OMAP1610_GPIO_DATAOUT; 586 reg += OMAP1610_GPIO_DATAOUT;
589 break; 587 break;
590#endif 588#endif
591#ifdef CONFIG_ARCH_OMAP730 589#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
592 case METHOD_GPIO_730: 590 case METHOD_GPIO_7XX:
593 reg += OMAP730_GPIO_DATA_OUTPUT; 591 reg += OMAP7XX_GPIO_DATA_OUTPUT;
594 break;
595#endif
596#ifdef CONFIG_ARCH_OMAP850
597 case METHOD_GPIO_850:
598 reg += OMAP850_GPIO_DATA_OUTPUT;
599 break; 592 break;
600#endif 593#endif
601#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 594#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
@@ -636,6 +629,10 @@ void omap_set_gpio_debounce(int gpio, int enable)
636#else 629#else
637 reg += OMAP24XX_GPIO_DEBOUNCE_EN; 630 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
638#endif 631#endif
632 if (!(bank->mod_usage & l)) {
633 printk(KERN_ERR "GPIO %d not requested\n", gpio);
634 return;
635 }
639 636
640 spin_lock_irqsave(&bank->lock, flags); 637 spin_lock_irqsave(&bank->lock, flags);
641 val = __raw_readl(reg); 638 val = __raw_readl(reg);
@@ -671,6 +668,11 @@ void omap_set_gpio_debounce_time(int gpio, int enc_time)
671 bank = get_gpio_bank(gpio); 668 bank = get_gpio_bank(gpio);
672 reg = bank->base; 669 reg = bank->base;
673 670
671 if (!bank->mod_usage) {
672 printk(KERN_ERR "GPIO not requested\n");
673 return;
674 }
675
674 enc_time &= 0xff; 676 enc_time &= 0xff;
675#ifdef CONFIG_ARCH_OMAP4 677#ifdef CONFIG_ARCH_OMAP4
676 reg += OMAP4_GPIO_DEBOUNCINGTIME; 678 reg += OMAP4_GPIO_DEBOUNCINGTIME;
@@ -797,21 +799,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
797 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); 799 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
798 break; 800 break;
799#endif 801#endif
800#ifdef CONFIG_ARCH_OMAP730 802#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
801 case METHOD_GPIO_730: 803 case METHOD_GPIO_7XX:
802 reg += OMAP730_GPIO_INT_CONTROL; 804 reg += OMAP7XX_GPIO_INT_CONTROL;
803 l = __raw_readl(reg);
804 if (trigger & IRQ_TYPE_EDGE_RISING)
805 l |= 1 << gpio;
806 else if (trigger & IRQ_TYPE_EDGE_FALLING)
807 l &= ~(1 << gpio);
808 else
809 goto bad;
810 break;
811#endif
812#ifdef CONFIG_ARCH_OMAP850
813 case METHOD_GPIO_850:
814 reg += OMAP850_GPIO_INT_CONTROL;
815 l = __raw_readl(reg); 805 l = __raw_readl(reg);
816 if (trigger & IRQ_TYPE_EDGE_RISING) 806 if (trigger & IRQ_TYPE_EDGE_RISING)
817 l |= 1 << gpio; 807 l |= 1 << gpio;
@@ -897,14 +887,9 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
897 reg += OMAP1610_GPIO_IRQSTATUS1; 887 reg += OMAP1610_GPIO_IRQSTATUS1;
898 break; 888 break;
899#endif 889#endif
900#ifdef CONFIG_ARCH_OMAP730 890#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
901 case METHOD_GPIO_730: 891 case METHOD_GPIO_7XX:
902 reg += OMAP730_GPIO_INT_STATUS; 892 reg += OMAP7XX_GPIO_INT_STATUS;
903 break;
904#endif
905#ifdef CONFIG_ARCH_OMAP850
906 case METHOD_GPIO_850:
907 reg += OMAP850_GPIO_INT_STATUS;
908 break; 893 break;
909#endif 894#endif
910#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 895#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
@@ -971,16 +956,9 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
971 mask = 0xffff; 956 mask = 0xffff;
972 break; 957 break;
973#endif 958#endif
974#ifdef CONFIG_ARCH_OMAP730 959#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
975 case METHOD_GPIO_730: 960 case METHOD_GPIO_7XX:
976 reg += OMAP730_GPIO_INT_MASK; 961 reg += OMAP7XX_GPIO_INT_MASK;
977 mask = 0xffffffff;
978 inv = 1;
979 break;
980#endif
981#ifdef CONFIG_ARCH_OMAP850
982 case METHOD_GPIO_850:
983 reg += OMAP850_GPIO_INT_MASK;
984 mask = 0xffffffff; 962 mask = 0xffffffff;
985 inv = 1; 963 inv = 1;
986 break; 964 break;
@@ -1044,19 +1022,9 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
1044 l = gpio_mask; 1022 l = gpio_mask;
1045 break; 1023 break;
1046#endif 1024#endif
1047#ifdef CONFIG_ARCH_OMAP730 1025#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1048 case METHOD_GPIO_730: 1026 case METHOD_GPIO_7XX:
1049 reg += OMAP730_GPIO_INT_MASK; 1027 reg += OMAP7XX_GPIO_INT_MASK;
1050 l = __raw_readl(reg);
1051 if (enable)
1052 l &= ~(gpio_mask);
1053 else
1054 l |= gpio_mask;
1055 break;
1056#endif
1057#ifdef CONFIG_ARCH_OMAP850
1058 case METHOD_GPIO_850:
1059 reg += OMAP850_GPIO_INT_MASK;
1060 l = __raw_readl(reg); 1028 l = __raw_readl(reg);
1061 if (enable) 1029 if (enable)
1062 l &= ~(gpio_mask); 1030 l &= ~(gpio_mask);
@@ -1186,6 +1154,16 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1186 __raw_writel(__raw_readl(reg) | (1 << offset), reg); 1154 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1187 } 1155 }
1188#endif 1156#endif
1157 if (!cpu_class_is_omap1()) {
1158 if (!bank->mod_usage) {
1159 u32 ctrl;
1160 ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1161 ctrl &= 0xFFFFFFFE;
1162 /* Module is enabled, clocks are not gated */
1163 __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
1164 }
1165 bank->mod_usage |= 1 << offset;
1166 }
1189 spin_unlock_irqrestore(&bank->lock, flags); 1167 spin_unlock_irqrestore(&bank->lock, flags);
1190 1168
1191 return 0; 1169 return 0;
@@ -1212,6 +1190,16 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1212 __raw_writel(1 << offset, reg); 1190 __raw_writel(1 << offset, reg);
1213 } 1191 }
1214#endif 1192#endif
1193 if (!cpu_class_is_omap1()) {
1194 bank->mod_usage &= ~(1 << offset);
1195 if (!bank->mod_usage) {
1196 u32 ctrl;
1197 ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1198 /* Module is disabled, clocks are gated */
1199 ctrl |= 1;
1200 __raw_writel(ctrl, bank->base + OMAP24XX_GPIO_CTRL);
1201 }
1202 }
1215 _reset_gpio(bank, bank->chip.base + offset); 1203 _reset_gpio(bank, bank->chip.base + offset);
1216 spin_unlock_irqrestore(&bank->lock, flags); 1204 spin_unlock_irqrestore(&bank->lock, flags);
1217} 1205}
@@ -1249,13 +1237,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1249 if (bank->method == METHOD_GPIO_1610) 1237 if (bank->method == METHOD_GPIO_1610)
1250 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; 1238 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1251#endif 1239#endif
1252#ifdef CONFIG_ARCH_OMAP730 1240#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1253 if (bank->method == METHOD_GPIO_730) 1241 if (bank->method == METHOD_GPIO_7XX)
1254 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; 1242 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1255#endif
1256#ifdef CONFIG_ARCH_OMAP850
1257 if (bank->method == METHOD_GPIO_850)
1258 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
1259#endif 1243#endif
1260#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1244#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1261 if (bank->method == METHOD_GPIO_24XX) 1245 if (bank->method == METHOD_GPIO_24XX)
@@ -1524,11 +1508,8 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
1524 case METHOD_GPIO_1610: 1508 case METHOD_GPIO_1610:
1525 reg += OMAP1610_GPIO_DIRECTION; 1509 reg += OMAP1610_GPIO_DIRECTION;
1526 break; 1510 break;
1527 case METHOD_GPIO_730: 1511 case METHOD_GPIO_7XX:
1528 reg += OMAP730_GPIO_DIR_CONTROL; 1512 reg += OMAP7XX_GPIO_DIR_CONTROL;
1529 break;
1530 case METHOD_GPIO_850:
1531 reg += OMAP850_GPIO_DIR_CONTROL;
1532 break; 1513 break;
1533 case METHOD_GPIO_24XX: 1514 case METHOD_GPIO_24XX:
1534 reg += OMAP24XX_GPIO_OE; 1515 reg += OMAP24XX_GPIO_OE;
@@ -1607,6 +1588,23 @@ static struct clk * gpio5_fck;
1607static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; 1588static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1608#endif 1589#endif
1609 1590
1591static void __init omap_gpio_show_rev(void)
1592{
1593 u32 rev;
1594
1595 if (cpu_is_omap16xx())
1596 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1597 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1598 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1599 else if (cpu_is_omap44xx())
1600 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1601 else
1602 return;
1603
1604 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1605 (rev >> 4) & 0x0f, rev & 0x0f);
1606}
1607
1610/* This lock class tells lockdep that GPIO irqs are in a different 1608/* This lock class tells lockdep that GPIO irqs are in a different
1611 * category than their parents, so it won't report false recursion. 1609 * category than their parents, so it won't report false recursion.
1612 */ 1610 */
@@ -1617,6 +1615,7 @@ static int __init _omap_gpio_init(void)
1617 int i; 1615 int i;
1618 int gpio = 0; 1616 int gpio = 0;
1619 struct gpio_bank *bank; 1617 struct gpio_bank *bank;
1618 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
1620 char clk_name[11]; 1619 char clk_name[11];
1621 1620
1622 initialized = 1; 1621 initialized = 1;
@@ -1679,77 +1678,45 @@ static int __init _omap_gpio_init(void)
1679 1678
1680#ifdef CONFIG_ARCH_OMAP15XX 1679#ifdef CONFIG_ARCH_OMAP15XX
1681 if (cpu_is_omap15xx()) { 1680 if (cpu_is_omap15xx()) {
1682 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1683 gpio_bank_count = 2; 1681 gpio_bank_count = 2;
1684 gpio_bank = gpio_bank_1510; 1682 gpio_bank = gpio_bank_1510;
1683 bank_size = SZ_2K;
1685 } 1684 }
1686#endif 1685#endif
1687#if defined(CONFIG_ARCH_OMAP16XX) 1686#if defined(CONFIG_ARCH_OMAP16XX)
1688 if (cpu_is_omap16xx()) { 1687 if (cpu_is_omap16xx()) {
1689 u32 rev;
1690
1691 gpio_bank_count = 5; 1688 gpio_bank_count = 5;
1692 gpio_bank = gpio_bank_1610; 1689 gpio_bank = gpio_bank_1610;
1693 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); 1690 bank_size = SZ_2K;
1694 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1695 (rev >> 4) & 0x0f, rev & 0x0f);
1696 } 1691 }
1697#endif 1692#endif
1698#ifdef CONFIG_ARCH_OMAP730 1693#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1699 if (cpu_is_omap730()) { 1694 if (cpu_is_omap7xx()) {
1700 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1701 gpio_bank_count = 7;
1702 gpio_bank = gpio_bank_730;
1703 }
1704#endif
1705#ifdef CONFIG_ARCH_OMAP850
1706 if (cpu_is_omap850()) {
1707 printk(KERN_INFO "OMAP850 GPIO hardware\n");
1708 gpio_bank_count = 7; 1695 gpio_bank_count = 7;
1709 gpio_bank = gpio_bank_850; 1696 gpio_bank = gpio_bank_7xx;
1697 bank_size = SZ_2K;
1710 } 1698 }
1711#endif 1699#endif
1712
1713#ifdef CONFIG_ARCH_OMAP24XX 1700#ifdef CONFIG_ARCH_OMAP24XX
1714 if (cpu_is_omap242x()) { 1701 if (cpu_is_omap242x()) {
1715 int rev;
1716
1717 gpio_bank_count = 4; 1702 gpio_bank_count = 4;
1718 gpio_bank = gpio_bank_242x; 1703 gpio_bank = gpio_bank_242x;
1719 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1720 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1721 (rev >> 4) & 0x0f, rev & 0x0f);
1722 } 1704 }
1723 if (cpu_is_omap243x()) { 1705 if (cpu_is_omap243x()) {
1724 int rev;
1725
1726 gpio_bank_count = 5; 1706 gpio_bank_count = 5;
1727 gpio_bank = gpio_bank_243x; 1707 gpio_bank = gpio_bank_243x;
1728 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1729 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1730 (rev >> 4) & 0x0f, rev & 0x0f);
1731 } 1708 }
1732#endif 1709#endif
1733#ifdef CONFIG_ARCH_OMAP34XX 1710#ifdef CONFIG_ARCH_OMAP34XX
1734 if (cpu_is_omap34xx()) { 1711 if (cpu_is_omap34xx()) {
1735 int rev;
1736
1737 gpio_bank_count = OMAP34XX_NR_GPIOS; 1712 gpio_bank_count = OMAP34XX_NR_GPIOS;
1738 gpio_bank = gpio_bank_34xx; 1713 gpio_bank = gpio_bank_34xx;
1739 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1740 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1741 (rev >> 4) & 0x0f, rev & 0x0f);
1742 } 1714 }
1743#endif 1715#endif
1744#ifdef CONFIG_ARCH_OMAP4 1716#ifdef CONFIG_ARCH_OMAP4
1745 if (cpu_is_omap44xx()) { 1717 if (cpu_is_omap44xx()) {
1746 int rev;
1747
1748 gpio_bank_count = OMAP34XX_NR_GPIOS; 1718 gpio_bank_count = OMAP34XX_NR_GPIOS;
1749 gpio_bank = gpio_bank_44xx; 1719 gpio_bank = gpio_bank_44xx;
1750 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1751 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
1752 (rev >> 4) & 0x0f, rev & 0x0f);
1753 } 1720 }
1754#endif 1721#endif
1755 for (i = 0; i < gpio_bank_count; i++) { 1722 for (i = 0; i < gpio_bank_count; i++) {
@@ -1757,6 +1724,14 @@ static int __init _omap_gpio_init(void)
1757 1724
1758 bank = &gpio_bank[i]; 1725 bank = &gpio_bank[i];
1759 spin_lock_init(&bank->lock); 1726 spin_lock_init(&bank->lock);
1727
1728 /* Static mapping, never released */
1729 bank->base = ioremap(bank->pbase, bank_size);
1730 if (!bank->base) {
1731 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
1732 continue;
1733 }
1734
1760 if (bank_is_mpuio(bank)) 1735 if (bank_is_mpuio(bank))
1761 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT); 1736 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1762 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { 1737 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
@@ -1768,11 +1743,11 @@ static int __init _omap_gpio_init(void)
1768 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); 1743 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1769 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); 1744 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1770 } 1745 }
1771 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) { 1746 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1772 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); 1747 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1773 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); 1748 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
1774 1749
1775 gpio_count = 32; /* 730 has 32-bit GPIOs */ 1750 gpio_count = 32; /* 7xx has 32-bit GPIOs */
1776 } 1751 }
1777 1752
1778#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1753#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
@@ -1804,6 +1779,8 @@ static int __init _omap_gpio_init(void)
1804 gpio_count = 32; 1779 gpio_count = 32;
1805 } 1780 }
1806#endif 1781#endif
1782
1783 bank->mod_usage = 0;
1807 /* REVISIT eventually switch from OMAP-specific gpio structs 1784 /* REVISIT eventually switch from OMAP-specific gpio structs
1808 * over to the generic ones 1785 * over to the generic ones
1809 */ 1786 */
@@ -1862,6 +1839,8 @@ static int __init _omap_gpio_init(void)
1862 if (cpu_is_omap34xx()) 1839 if (cpu_is_omap34xx())
1863 omap_writel(1 << 0, 0x48306814); 1840 omap_writel(1 << 0, 0x48306814);
1864 1841
1842 omap_gpio_show_rev();
1843
1865 return 0; 1844 return 0;
1866} 1845}
1867 1846
@@ -2106,6 +2085,81 @@ void omap2_gpio_resume_after_retention(void)
2106 2085
2107#endif 2086#endif
2108 2087
2088#ifdef CONFIG_ARCH_OMAP34XX
2089/* save the registers of bank 2-6 */
2090void omap_gpio_save_context(void)
2091{
2092 int i;
2093
2094 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2095 for (i = 1; i < gpio_bank_count; i++) {
2096 struct gpio_bank *bank = &gpio_bank[i];
2097 gpio_context[i].sysconfig =
2098 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
2099 gpio_context[i].irqenable1 =
2100 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2101 gpio_context[i].irqenable2 =
2102 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2103 gpio_context[i].wake_en =
2104 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2105 gpio_context[i].ctrl =
2106 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2107 gpio_context[i].oe =
2108 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2109 gpio_context[i].leveldetect0 =
2110 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2111 gpio_context[i].leveldetect1 =
2112 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2113 gpio_context[i].risingdetect =
2114 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2115 gpio_context[i].fallingdetect =
2116 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2117 gpio_context[i].dataout =
2118 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2119 gpio_context[i].setwkuena =
2120 __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA);
2121 gpio_context[i].setdataout =
2122 __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT);
2123 }
2124}
2125
2126/* restore the required registers of bank 2-6 */
2127void omap_gpio_restore_context(void)
2128{
2129 int i;
2130
2131 for (i = 1; i < gpio_bank_count; i++) {
2132 struct gpio_bank *bank = &gpio_bank[i];
2133 __raw_writel(gpio_context[i].sysconfig,
2134 bank->base + OMAP24XX_GPIO_SYSCONFIG);
2135 __raw_writel(gpio_context[i].irqenable1,
2136 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2137 __raw_writel(gpio_context[i].irqenable2,
2138 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2139 __raw_writel(gpio_context[i].wake_en,
2140 bank->base + OMAP24XX_GPIO_WAKE_EN);
2141 __raw_writel(gpio_context[i].ctrl,
2142 bank->base + OMAP24XX_GPIO_CTRL);
2143 __raw_writel(gpio_context[i].oe,
2144 bank->base + OMAP24XX_GPIO_OE);
2145 __raw_writel(gpio_context[i].leveldetect0,
2146 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2147 __raw_writel(gpio_context[i].leveldetect1,
2148 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2149 __raw_writel(gpio_context[i].risingdetect,
2150 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2151 __raw_writel(gpio_context[i].fallingdetect,
2152 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2153 __raw_writel(gpio_context[i].dataout,
2154 bank->base + OMAP24XX_GPIO_DATAOUT);
2155 __raw_writel(gpio_context[i].setwkuena,
2156 bank->base + OMAP24XX_GPIO_SETWKUENA);
2157 __raw_writel(gpio_context[i].setdataout,
2158 bank->base + OMAP24XX_GPIO_SETDATAOUT);
2159 }
2160}
2161#endif
2162
2109/* 2163/*
2110 * This may get called early from board specific init 2164 * This may get called early from board specific init
2111 * for boards that have interrupts routed via FPGA. 2165 * for boards that have interrupts routed via FPGA.
@@ -2160,8 +2214,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
2160 2214
2161 if (bank_is_mpuio(bank)) 2215 if (bank_is_mpuio(bank))
2162 gpio = OMAP_MPUIO(0); 2216 gpio = OMAP_MPUIO(0);
2163 else if (cpu_class_is_omap2() || cpu_is_omap730() || 2217 else if (cpu_class_is_omap2() || cpu_is_omap7xx())
2164 cpu_is_omap850())
2165 bankwidth = 32; 2218 bankwidth = 32;
2166 2219
2167 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { 2220 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 23:57:42 -0500