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Diffstat (limited to 'arch/arm/plat-omap/gpio.c')
-rw-r--r--arch/arm/plat-omap/gpio.c31
1 files changed, 11 insertions, 20 deletions
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 971d18636942..d2adcdda23cf 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -755,18 +755,12 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
755 bank = irq_data_get_irq_chip_data(d); 755 bank = irq_data_get_irq_chip_data(d);
756 spin_lock_irqsave(&bank->lock, flags); 756 spin_lock_irqsave(&bank->lock, flags);
757 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); 757 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
758 if (retval == 0) {
759 struct irq_desc *desc = irq_to_desc(d->irq);
760
761 desc->status &= ~IRQ_TYPE_SENSE_MASK;
762 desc->status |= type;
763 }
764 spin_unlock_irqrestore(&bank->lock, flags); 758 spin_unlock_irqrestore(&bank->lock, flags);
765 759
766 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 760 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
767 __set_irq_handler_unlocked(d->irq, handle_level_irq); 761 __irq_set_handler_locked(d->irq, handle_level_irq);
768 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 762 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
769 __set_irq_handler_unlocked(d->irq, handle_edge_irq); 763 __irq_set_handler_locked(d->irq, handle_edge_irq);
770 764
771 return retval; 765 return retval;
772} 766}
@@ -1146,7 +1140,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1146 1140
1147 desc->irq_data.chip->irq_ack(&desc->irq_data); 1141 desc->irq_data.chip->irq_ack(&desc->irq_data);
1148 1142
1149 bank = get_irq_data(irq); 1143 bank = irq_get_handler_data(irq);
1150#ifdef CONFIG_ARCH_OMAP1 1144#ifdef CONFIG_ARCH_OMAP1
1151 if (bank->method == METHOD_MPUIO) 1145 if (bank->method == METHOD_MPUIO)
1152 isr_reg = bank->base + 1146 isr_reg = bank->base +
@@ -1270,8 +1264,7 @@ static void gpio_unmask_irq(struct irq_data *d)
1270 unsigned int gpio = d->irq - IH_GPIO_BASE; 1264 unsigned int gpio = d->irq - IH_GPIO_BASE;
1271 struct gpio_bank *bank = irq_data_get_irq_chip_data(d); 1265 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1272 unsigned int irq_mask = 1 << get_gpio_index(gpio); 1266 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1273 struct irq_desc *desc = irq_to_desc(d->irq); 1267 u32 trigger = irqd_get_trigger_type(d);
1274 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1275 1268
1276 if (trigger) 1269 if (trigger)
1277 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); 1270 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
@@ -1672,19 +1665,17 @@ static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1672 1665
1673 for (j = bank->virtual_irq_start; 1666 for (j = bank->virtual_irq_start;
1674 j < bank->virtual_irq_start + bank_width; j++) { 1667 j < bank->virtual_irq_start + bank_width; j++) {
1675 struct irq_desc *d = irq_to_desc(j); 1668 irq_set_lockdep_class(j, &gpio_lock_class);
1676 1669 irq_set_chip_data(j, bank);
1677 lockdep_set_class(&d->lock, &gpio_lock_class);
1678 set_irq_chip_data(j, bank);
1679 if (bank_is_mpuio(bank)) 1670 if (bank_is_mpuio(bank))
1680 set_irq_chip(j, &mpuio_irq_chip); 1671 irq_set_chip(j, &mpuio_irq_chip);
1681 else 1672 else
1682 set_irq_chip(j, &gpio_irq_chip); 1673 irq_set_chip(j, &gpio_irq_chip);
1683 set_irq_handler(j, handle_simple_irq); 1674 irq_set_handler(j, handle_simple_irq);
1684 set_irq_flags(j, IRQF_VALID); 1675 set_irq_flags(j, IRQF_VALID);
1685 } 1676 }
1686 set_irq_chained_handler(bank->irq, gpio_irq_handler); 1677 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1687 set_irq_data(bank->irq, bank); 1678 irq_set_handler_data(bank->irq, bank);
1688} 1679}
1689 1680
1690static int __devinit omap_gpio_probe(struct platform_device *pdev) 1681static int __devinit omap_gpio_probe(struct platform_device *pdev)