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Diffstat (limited to 'arch/arm/plat-omap/gpio.c')
-rw-r--r--arch/arm/plat-omap/gpio.c234
1 files changed, 118 insertions, 116 deletions
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index e0e2fa725269..48bccf2001eb 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -190,14 +190,12 @@ struct gpio_bank {
190 u32 suspend_wakeup; 190 u32 suspend_wakeup;
191 u32 saved_wakeup; 191 u32 saved_wakeup;
192#endif 192#endif
193#ifdef CONFIG_ARCH_OMAP2PLUS
194 u32 non_wakeup_gpios; 193 u32 non_wakeup_gpios;
195 u32 enabled_non_wakeup_gpios; 194 u32 enabled_non_wakeup_gpios;
196 195
197 u32 saved_datain; 196 u32 saved_datain;
198 u32 saved_fallingdetect; 197 u32 saved_fallingdetect;
199 u32 saved_risingdetect; 198 u32 saved_risingdetect;
200#endif
201 u32 level_mask; 199 u32 level_mask;
202 u32 toggle_mask; 200 u32 toggle_mask;
203 spinlock_t lock; 201 spinlock_t lock;
@@ -1718,10 +1716,125 @@ static void __init omap_gpio_show_rev(void)
1718 */ 1716 */
1719static struct lock_class_key gpio_lock_class; 1717static struct lock_class_key gpio_lock_class;
1720 1718
1719static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1720{
1721 if (cpu_class_is_omap2()) {
1722 if (cpu_is_omap44xx()) {
1723 __raw_writel(0xffffffff, bank->base +
1724 OMAP4_GPIO_IRQSTATUSCLR0);
1725 __raw_writel(0x00000000, bank->base +
1726 OMAP4_GPIO_DEBOUNCENABLE);
1727 /* Initialize interface clk ungated, module enabled */
1728 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1729 } else if (cpu_is_omap34xx()) {
1730 __raw_writel(0x00000000, bank->base +
1731 OMAP24XX_GPIO_IRQENABLE1);
1732 __raw_writel(0xffffffff, bank->base +
1733 OMAP24XX_GPIO_IRQSTATUS1);
1734 __raw_writel(0x00000000, bank->base +
1735 OMAP24XX_GPIO_DEBOUNCE_EN);
1736
1737 /* Initialize interface clk ungated, module enabled */
1738 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1739 } else if (cpu_is_omap24xx()) {
1740 static const u32 non_wakeup_gpios[] = {
1741 0xe203ffc0, 0x08700040
1742 };
1743 if (id < ARRAY_SIZE(non_wakeup_gpios))
1744 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1745 }
1746 } else if (cpu_class_is_omap1()) {
1747 if (bank_is_mpuio(bank))
1748 __raw_writew(0xffff, bank->base
1749 + OMAP_MPUIO_GPIO_MASKIT);
1750 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1751 __raw_writew(0xffff, bank->base
1752 + OMAP1510_GPIO_INT_MASK);
1753 __raw_writew(0x0000, bank->base
1754 + OMAP1510_GPIO_INT_STATUS);
1755 }
1756 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1757 __raw_writew(0x0000, bank->base
1758 + OMAP1610_GPIO_IRQENABLE1);
1759 __raw_writew(0xffff, bank->base
1760 + OMAP1610_GPIO_IRQSTATUS1);
1761 __raw_writew(0x0014, bank->base
1762 + OMAP1610_GPIO_SYSCONFIG);
1763
1764 /*
1765 * Enable system clock for GPIO module.
1766 * The CAM_CLK_CTRL *is* really the right place.
1767 */
1768 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1769 ULPD_CAM_CLK_CTRL);
1770 }
1771 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1772 __raw_writel(0xffffffff, bank->base
1773 + OMAP7XX_GPIO_INT_MASK);
1774 __raw_writel(0x00000000, bank->base
1775 + OMAP7XX_GPIO_INT_STATUS);
1776 }
1777 }
1778}
1779
1780static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1781{
1782 int j, bank_width = 16;
1783 static int gpio;
1784
1785 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX)
1786 bank_width = 32; /* 7xx has 32-bit GPIOs */
1787
1788 if ((bank->method == METHOD_GPIO_24XX) ||
1789 (bank->method == METHOD_GPIO_44XX))
1790 bank_width = 32;
1791
1792 bank->mod_usage = 0;
1793 /*
1794 * REVISIT eventually switch from OMAP-specific gpio structs
1795 * over to the generic ones
1796 */
1797 bank->chip.request = omap_gpio_request;
1798 bank->chip.free = omap_gpio_free;
1799 bank->chip.direction_input = gpio_input;
1800 bank->chip.get = gpio_get;
1801 bank->chip.direction_output = gpio_output;
1802 bank->chip.set_debounce = gpio_debounce;
1803 bank->chip.set = gpio_set;
1804 bank->chip.to_irq = gpio_2irq;
1805 if (bank_is_mpuio(bank)) {
1806 bank->chip.label = "mpuio";
1807#ifdef CONFIG_ARCH_OMAP16XX
1808 bank->chip.dev = &omap_mpuio_device.dev;
1809#endif
1810 bank->chip.base = OMAP_MPUIO(0);
1811 } else {
1812 bank->chip.label = "gpio";
1813 bank->chip.base = gpio;
1814 gpio += bank_width;
1815 }
1816 bank->chip.ngpio = bank_width;
1817
1818 gpiochip_add(&bank->chip);
1819
1820 for (j = bank->virtual_irq_start;
1821 j < bank->virtual_irq_start + bank_width; j++) {
1822 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1823 set_irq_chip_data(j, bank);
1824 if (bank_is_mpuio(bank))
1825 set_irq_chip(j, &mpuio_irq_chip);
1826 else
1827 set_irq_chip(j, &gpio_irq_chip);
1828 set_irq_handler(j, handle_simple_irq);
1829 set_irq_flags(j, IRQF_VALID);
1830 }
1831 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1832 set_irq_data(bank->irq, bank);
1833}
1834
1721static int __init _omap_gpio_init(void) 1835static int __init _omap_gpio_init(void)
1722{ 1836{
1723 int i; 1837 int i;
1724 int gpio = 0;
1725 struct gpio_bank *bank; 1838 struct gpio_bank *bank;
1726 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ 1839 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
1727 char clk_name[11]; 1840 char clk_name[11];
@@ -1828,7 +1941,6 @@ static int __init _omap_gpio_init(void)
1828 } 1941 }
1829#endif 1942#endif
1830 for (i = 0; i < gpio_bank_count; i++) { 1943 for (i = 0; i < gpio_bank_count; i++) {
1831 int j, gpio_count = 16;
1832 1944
1833 bank = &gpio_bank[i]; 1945 bank = &gpio_bank[i];
1834 spin_lock_init(&bank->lock); 1946 spin_lock_init(&bank->lock);
@@ -1840,107 +1952,8 @@ static int __init _omap_gpio_init(void)
1840 continue; 1952 continue;
1841 } 1953 }
1842 1954
1843 if (bank_is_mpuio(bank)) 1955 omap_gpio_mod_init(bank, i);
1844 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT); 1956 omap_gpio_chip_init(bank);
1845 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1846 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1847 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1848 }
1849 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1850 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1851 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1852 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1853 }
1854 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1855 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1856 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
1857
1858 gpio_count = 32; /* 7xx has 32-bit GPIOs */
1859 }
1860
1861#ifdef CONFIG_ARCH_OMAP2PLUS
1862 if ((bank->method == METHOD_GPIO_24XX) ||
1863 (bank->method == METHOD_GPIO_44XX)) {
1864 static const u32 non_wakeup_gpios[] = {
1865 0xe203ffc0, 0x08700040
1866 };
1867
1868 if (cpu_is_omap44xx()) {
1869 __raw_writel(0xffffffff, bank->base +
1870 OMAP4_GPIO_IRQSTATUSCLR0);
1871 __raw_writew(0x0015, bank->base +
1872 OMAP4_GPIO_SYSCONFIG);
1873 __raw_writel(0x00000000, bank->base +
1874 OMAP4_GPIO_DEBOUNCENABLE);
1875 /*
1876 * Initialize interface clock ungated,
1877 * module enabled
1878 */
1879 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1880 } else {
1881 __raw_writel(0x00000000, bank->base +
1882 OMAP24XX_GPIO_IRQENABLE1);
1883 __raw_writel(0xffffffff, bank->base +
1884 OMAP24XX_GPIO_IRQSTATUS1);
1885 __raw_writew(0x0015, bank->base +
1886 OMAP24XX_GPIO_SYSCONFIG);
1887 __raw_writel(0x00000000, bank->base +
1888 OMAP24XX_GPIO_DEBOUNCE_EN);
1889
1890 /*
1891 * Initialize interface clock ungated,
1892 * module enabled
1893 */
1894 __raw_writel(0, bank->base +
1895 OMAP24XX_GPIO_CTRL);
1896 }
1897 if (cpu_is_omap24xx() &&
1898 i < ARRAY_SIZE(non_wakeup_gpios))
1899 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1900 gpio_count = 32;
1901 }
1902#endif
1903
1904 bank->mod_usage = 0;
1905 /* REVISIT eventually switch from OMAP-specific gpio structs
1906 * over to the generic ones
1907 */
1908 bank->chip.request = omap_gpio_request;
1909 bank->chip.free = omap_gpio_free;
1910 bank->chip.direction_input = gpio_input;
1911 bank->chip.get = gpio_get;
1912 bank->chip.direction_output = gpio_output;
1913 bank->chip.set_debounce = gpio_debounce;
1914 bank->chip.set = gpio_set;
1915 bank->chip.to_irq = gpio_2irq;
1916 if (bank_is_mpuio(bank)) {
1917 bank->chip.label = "mpuio";
1918#ifdef CONFIG_ARCH_OMAP16XX
1919 bank->chip.dev = &omap_mpuio_device.dev;
1920#endif
1921 bank->chip.base = OMAP_MPUIO(0);
1922 } else {
1923 bank->chip.label = "gpio";
1924 bank->chip.base = gpio;
1925 gpio += gpio_count;
1926 }
1927 bank->chip.ngpio = gpio_count;
1928
1929 gpiochip_add(&bank->chip);
1930
1931 for (j = bank->virtual_irq_start;
1932 j < bank->virtual_irq_start + gpio_count; j++) {
1933 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1934 set_irq_chip_data(j, bank);
1935 if (bank_is_mpuio(bank))
1936 set_irq_chip(j, &mpuio_irq_chip);
1937 else
1938 set_irq_chip(j, &gpio_irq_chip);
1939 set_irq_handler(j, handle_simple_irq);
1940 set_irq_flags(j, IRQF_VALID);
1941 }
1942 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1943 set_irq_data(bank->irq, bank);
1944 1957
1945 if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 1958 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1946 sprintf(clk_name, "gpio%d_dbck", i + 1); 1959 sprintf(clk_name, "gpio%d_dbck", i + 1);
@@ -1950,17 +1963,6 @@ static int __init _omap_gpio_init(void)
1950 } 1963 }
1951 } 1964 }
1952 1965
1953 /* Enable system clock for GPIO module.
1954 * The CAM_CLK_CTRL *is* really the right place. */
1955 if (cpu_is_omap16xx())
1956 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1957
1958 /* Enable autoidle for the OCP interface */
1959 if (cpu_is_omap24xx())
1960 omap_writel(1 << 0, 0x48019010);
1961 if (cpu_is_omap34xx())
1962 omap_writel(1 << 0, 0x48306814);
1963
1964 omap_gpio_show_rev(); 1966 omap_gpio_show_rev();
1965 1967
1966 return 0; 1968 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 09:09:03 -0500