1 files changed, 419 insertions, 105 deletions

diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 1c85b4e536c2..55059a24ad41 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -3,7 +3,7 @@
  *
  * Support functions for OMAP GPIO
  *
- * Copyright (C) 2003 Nokia Corporation
+ * Copyright (C) 2003-2005 Nokia Corporation
  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -17,8 +17,11 @@
 #include <linux/sched.h>
 #include <linux/interrupt.h>
 #include <linux/ptrace.h>
+#include <linux/sysdev.h>
+#include <linux/err.h>
 
 #include <asm/hardware.h>
+#include <asm/hardware/clock.h>
 #include <asm/irq.h>
 #include <asm/arch/irqs.h>
 #include <asm/arch/gpio.h>
@@ -29,7 +32,7 @@
 /*
  * OMAP1510 GPIO registers
  */
-#define OMAP1510_GPIO_BASE              0xfffce000
+#define OMAP1510_GPIO_BASE              (void __iomem *)0xfffce000
 #define OMAP1510_GPIO_DATA_INPUT        0x00
 #define OMAP1510_GPIO_DATA_OUTPUT       0x04
 #define OMAP1510_GPIO_DIR_CONTROL       0x08
@@ -43,34 +46,37 @@
 /*
  * OMAP1610 specific GPIO registers
  */
-#define OMAP1610_GPIO1_BASE             0xfffbe400
-#define OMAP1610_GPIO2_BASE             0xfffbec00
-#define OMAP1610_GPIO3_BASE             0xfffbb400
-#define OMAP1610_GPIO4_BASE             0xfffbbc00
+#define OMAP1610_GPIO1_BASE             (void __iomem *)0xfffbe400
+#define OMAP1610_GPIO2_BASE             (void __iomem *)0xfffbec00
+#define OMAP1610_GPIO3_BASE             (void __iomem *)0xfffbb400
+#define OMAP1610_GPIO4_BASE             (void __iomem *)0xfffbbc00
 #define OMAP1610_GPIO_REVISION          0x0000
 #define OMAP1610_GPIO_SYSCONFIG         0x0010
 #define OMAP1610_GPIO_SYSSTATUS         0x0014
 #define OMAP1610_GPIO_IRQSTATUS1        0x0018
 #define OMAP1610_GPIO_IRQENABLE1        0x001c
+#define OMAP1610_GPIO_WAKEUPENABLE      0x0028
 #define OMAP1610_GPIO_DATAIN            0x002c
 #define OMAP1610_GPIO_DATAOUT           0x0030
 #define OMAP1610_GPIO_DIRECTION         0x0034
 #define OMAP1610_GPIO_EDGE_CTRL1        0x0038
 #define OMAP1610_GPIO_EDGE_CTRL2        0x003c
 #define OMAP1610_GPIO_CLEAR_IRQENABLE1  0x009c
+#define OMAP1610_GPIO_CLEAR_WAKEUPENA   0x00a8
 #define OMAP1610_GPIO_CLEAR_DATAOUT     0x00b0
 #define OMAP1610_GPIO_SET_IRQENABLE1    0x00dc
+#define OMAP1610_GPIO_SET_WAKEUPENA     0x00e8
 #define OMAP1610_GPIO_SET_DATAOUT       0x00f0
 
 /*
  * OMAP730 specific GPIO registers
  */
-#define OMAP730_GPIO1_BASE              0xfffbc000
-#define OMAP730_GPIO2_BASE              0xfffbc800
-#define OMAP730_GPIO3_BASE              0xfffbd000
-#define OMAP730_GPIO4_BASE              0xfffbd800
-#define OMAP730_GPIO5_BASE              0xfffbe000
-#define OMAP730_GPIO6_BASE              0xfffbe800
+#define OMAP730_GPIO1_BASE              (void __iomem *)0xfffbc000
+#define OMAP730_GPIO2_BASE              (void __iomem *)0xfffbc800
+#define OMAP730_GPIO3_BASE              (void __iomem *)0xfffbd000
+#define OMAP730_GPIO4_BASE              (void __iomem *)0xfffbd800
+#define OMAP730_GPIO5_BASE              (void __iomem *)0xfffbe000
+#define OMAP730_GPIO6_BASE              (void __iomem *)0xfffbe800
 #define OMAP730_GPIO_DATA_INPUT         0x00
 #define OMAP730_GPIO_DATA_OUTPUT        0x04
 #define OMAP730_GPIO_DIR_CONTROL        0x08
@@ -78,14 +84,43 @@
 #define OMAP730_GPIO_INT_MASK           0x10
 #define OMAP730_GPIO_INT_STATUS         0x14
 
+/*
+ * omap24xx specific GPIO registers
+ */
+#define OMAP24XX_GPIO1_BASE             (void __iomem *)0x48018000
+#define OMAP24XX_GPIO2_BASE             (void __iomem *)0x4801a000
+#define OMAP24XX_GPIO3_BASE             (void __iomem *)0x4801c000
+#define OMAP24XX_GPIO4_BASE             (void __iomem *)0x4801e000
+#define OMAP24XX_GPIO_REVISION          0x0000
+#define OMAP24XX_GPIO_SYSCONFIG         0x0010
+#define OMAP24XX_GPIO_SYSSTATUS         0x0014
+#define OMAP24XX_GPIO_IRQSTATUS1        0x0018
+#define OMAP24XX_GPIO_IRQENABLE1        0x001c
+#define OMAP24XX_GPIO_CTRL              0x0030
+#define OMAP24XX_GPIO_OE                0x0034
+#define OMAP24XX_GPIO_DATAIN            0x0038
+#define OMAP24XX_GPIO_DATAOUT           0x003c
+#define OMAP24XX_GPIO_LEVELDETECT0      0x0040
+#define OMAP24XX_GPIO_LEVELDETECT1      0x0044
+#define OMAP24XX_GPIO_RISINGDETECT      0x0048
+#define OMAP24XX_GPIO_FALLINGDETECT     0x004c
+#define OMAP24XX_GPIO_CLEARIRQENABLE1   0x0060
+#define OMAP24XX_GPIO_SETIRQENABLE1     0x0064
+#define OMAP24XX_GPIO_CLEARWKUENA       0x0080
+#define OMAP24XX_GPIO_SETWKUENA         0x0084
+#define OMAP24XX_GPIO_CLEARDATAOUT      0x0090
+#define OMAP24XX_GPIO_SETDATAOUT        0x0094
+
 #define OMAP_MPUIO_MASK         (~OMAP_MAX_GPIO_LINES & 0xff)
 
 struct gpio_bank {
-        u32 base;
+        void __iomem *base;
         u16 irq;
         u16 virtual_irq_start;
-        u8 method;
+        int method;
         u32 reserved_map;
+        u32 suspend_wakeup;
+        u32 saved_wakeup;
         spinlock_t lock;
 };
 
@@ -93,8 +128,9 @@ struct gpio_bank {
 #define METHOD_GPIO_1510        1
 #define METHOD_GPIO_1610        2
 #define METHOD_GPIO_730         3
+#define METHOD_GPIO_24XX        4
 
-#if defined(CONFIG_ARCH_OMAP16XX)
+#ifdef CONFIG_ARCH_OMAP16XX
 static struct gpio_bank gpio_bank_1610[5] = {
         { OMAP_MPUIO_BASE,     INT_MPUIO,           IH_MPUIO_BASE,     METHOD_MPUIO},
         { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1,      IH_GPIO_BASE,      METHOD_GPIO_1610 },
@@ -123,6 +159,15 @@ static struct gpio_bank gpio_bank_730[7] = {
 };
 #endif
 
+#ifdef CONFIG_ARCH_OMAP24XX
+static struct gpio_bank gpio_bank_24xx[4] = {
+        { OMAP24XX_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,       METHOD_GPIO_24XX },
+        { OMAP24XX_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,  METHOD_GPIO_24XX },
+        { OMAP24XX_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,  METHOD_GPIO_24XX },
+        { OMAP24XX_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,  METHOD_GPIO_24XX },
+};
+#endif
+
 static struct gpio_bank *gpio_bank;
 static int gpio_bank_count;
 
@@ -149,14 +194,23 @@ static inline struct gpio_bank *get_gpio_bank(int gpio)
                 return &gpio_bank[1 + (gpio >> 5)];
         }
 #endif
+#ifdef CONFIG_ARCH_OMAP24XX
+        if (cpu_is_omap24xx())
+                return &gpio_bank[gpio >> 5];
+#endif
 }
 
 static inline int get_gpio_index(int gpio)
 {
+#ifdef CONFIG_ARCH_OMAP730
         if (cpu_is_omap730())
                 return gpio & 0x1f;
-        else
-                return gpio & 0x0f;
+#endif
+#ifdef CONFIG_ARCH_OMAP24XX
+        if (cpu_is_omap24xx())
+                return gpio & 0x1f;
+#endif
+        return gpio & 0x0f;
 }
 
 static inline int gpio_valid(int gpio)
@@ -180,6 +234,10 @@ static inline int gpio_valid(int gpio)
         if (cpu_is_omap730() && gpio < 192)
                 return 0;
 #endif
+#ifdef CONFIG_ARCH_OMAP24XX
+        if (cpu_is_omap24xx() && gpio < 128)
+                return 0;
+#endif
         return -1;
 }
 
@@ -195,7 +253,7 @@ static int check_gpio(int gpio)
 
 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
 {
-        u32 reg = bank->base;
+        void __iomem *reg = bank->base;
         u32 l;
 
         switch (bank->method) {
@@ -211,6 +269,9 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
         case METHOD_GPIO_730:
                 reg += OMAP730_GPIO_DIR_CONTROL;
                 break;
+        case METHOD_GPIO_24XX:
+                reg += OMAP24XX_GPIO_OE;
+                break;
         }
         l = __raw_readl(reg);
         if (is_input)
@@ -234,7 +295,7 @@ void omap_set_gpio_direction(int gpio, int is_input)
 
 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
 {
-        u32 reg = bank->base;
+        void __iomem *reg = bank->base;
         u32 l = 0;
 
         switch (bank->method) {
@@ -269,6 +330,13 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
                 else
                         l &= ~(1 << gpio);
                 break;
+        case METHOD_GPIO_24XX:
+                if (enable)
+                        reg += OMAP24XX_GPIO_SETDATAOUT;
+                else
+                        reg += OMAP24XX_GPIO_CLEARDATAOUT;
+                l = 1 << gpio;
+                break;
         default:
                 BUG();
                 return;
@@ -291,7 +359,7 @@ void omap_set_gpio_dataout(int gpio, int enable)
 int omap_get_gpio_datain(int gpio)
 {
         struct gpio_bank *bank;
-        u32 reg;
+        void __iomem *reg;
 
         if (check_gpio(gpio) < 0)
                 return -1;
@@ -310,109 +378,132 @@ int omap_get_gpio_datain(int gpio)
         case METHOD_GPIO_730:
                 reg += OMAP730_GPIO_DATA_INPUT;
                 break;
+        case METHOD_GPIO_24XX:
+                reg += OMAP24XX_GPIO_DATAIN;
+                break;
         default:
                 BUG();
                 return -1;
         }
-        return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
+        return (__raw_readl(reg)
+                        & (1 << get_gpio_index(gpio))) != 0;
 }
 
-static void _set_gpio_edge_ctrl(struct gpio_bank *bank, int gpio, int edge)
+#define MOD_REG_BIT(reg, bit_mask, set) \
+do {    \
+        int l = __raw_readl(base + reg); \
+        if (set) l |= bit_mask; \
+        else l &= ~bit_mask; \
+        __raw_writel(l, base + reg); \
+} while(0)
+
+static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int trigger)
 {
-        u32 reg = bank->base;
-        u32 l;
+        u32 gpio_bit = 1 << gpio;
+
+        MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
+                trigger & IRQT_LOW);
+        MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
+                trigger & IRQT_HIGH);
+        MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
+                trigger & IRQT_RISING);
+        MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
+                trigger & IRQT_FALLING);
+        /* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level
+         * triggering requested. */
+}
+
+static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
+{
+        void __iomem *reg = bank->base;
+        u32 l = 0;
 
         switch (bank->method) {
         case METHOD_MPUIO:
                 reg += OMAP_MPUIO_GPIO_INT_EDGE;
                 l = __raw_readl(reg);
-                if (edge == OMAP_GPIO_RISING_EDGE)
+                if (trigger == IRQT_RISING)
                         l |= 1 << gpio;
-                else
+                else if (trigger == IRQT_FALLING)
                         l &= ~(1 << gpio);
-                __raw_writel(l, reg);
+                else
+                        goto bad;
                 break;
         case METHOD_GPIO_1510:
                 reg += OMAP1510_GPIO_INT_CONTROL;
                 l = __raw_readl(reg);
-                if (edge == OMAP_GPIO_RISING_EDGE)
+                if (trigger == IRQT_RISING)
                         l |= 1 << gpio;
-                else
+                else if (trigger == IRQT_FALLING)
                         l &= ~(1 << gpio);
-                __raw_writel(l, reg);
+                else
+                        goto bad;
                 break;
         case METHOD_GPIO_1610:
-                edge &= 0x03;
                 if (gpio & 0x08)
                         reg += OMAP1610_GPIO_EDGE_CTRL2;
                 else
                         reg += OMAP1610_GPIO_EDGE_CTRL1;
                 gpio &= 0x07;
+                /* We allow only edge triggering, i.e. two lowest bits */
+                if (trigger & ~IRQT_BOTHEDGE)
+                        BUG();
+                /* NOTE: knows __IRQT_{FAL,RIS}EDGE match OMAP hardware */
+                trigger &= 0x03;
                 l = __raw_readl(reg);
                 l &= ~(3 << (gpio << 1));
-                l |= edge << (gpio << 1);
-                __raw_writel(l, reg);
+                l |= trigger << (gpio << 1);
                 break;
         case METHOD_GPIO_730:
                 reg += OMAP730_GPIO_INT_CONTROL;
                 l = __raw_readl(reg);
-                if (edge == OMAP_GPIO_RISING_EDGE)
+                if (trigger == IRQT_RISING)
                         l |= 1 << gpio;
-                else
+                else if (trigger == IRQT_FALLING)
                         l &= ~(1 << gpio);
-                __raw_writel(l, reg);
+                else
+                        goto bad;
+                break;
+        case METHOD_GPIO_24XX:
+                set_24xx_gpio_triggering(reg, gpio, trigger);
                 break;
         default:
                 BUG();
-                return;
+                goto bad;
         }
+        __raw_writel(l, reg);
+        return 0;
+bad:
+        return -EINVAL;
 }
 
-void omap_set_gpio_edge_ctrl(int gpio, int edge)
+static int gpio_irq_type(unsigned irq, unsigned type)
 {
         struct gpio_bank *bank;
+        unsigned gpio;
+        int retval;
+
+        if (irq > IH_MPUIO_BASE)
+                gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
+        else
+                gpio = irq - IH_GPIO_BASE;
 
         if (check_gpio(gpio) < 0)
-                return;
+                return -EINVAL;
+
+        if (type & (__IRQT_LOWLVL|__IRQT_HIGHLVL|IRQT_PROBE))
+                return -EINVAL;
+
         bank = get_gpio_bank(gpio);
         spin_lock(&bank->lock);
-        _set_gpio_edge_ctrl(bank, get_gpio_index(gpio), edge);
+        retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
         spin_unlock(&bank->lock);
-}
-
-
-static int _get_gpio_edge_ctrl(struct gpio_bank *bank, int gpio)
-{
-        u32 reg = bank->base, l;
-
-        switch (bank->method) {
-        case METHOD_MPUIO:
-                l = __raw_readl(reg + OMAP_MPUIO_GPIO_INT_EDGE);
-                return (l & (1 << gpio)) ?
-                        OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
-        case METHOD_GPIO_1510:
-                l = __raw_readl(reg + OMAP1510_GPIO_INT_CONTROL);
-                return (l & (1 << gpio)) ?
-                        OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
-        case METHOD_GPIO_1610:
-                if (gpio & 0x08)
-                        reg += OMAP1610_GPIO_EDGE_CTRL2;
-                else
-                        reg += OMAP1610_GPIO_EDGE_CTRL1;
-                return (__raw_readl(reg) >> ((gpio & 0x07) << 1)) & 0x03;
-        case METHOD_GPIO_730:
-                l = __raw_readl(reg + OMAP730_GPIO_INT_CONTROL);
-                return (l & (1 << gpio)) ?
-                        OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
-        default:
-                BUG();
-                return -1;
-        }
+        return retval;
 }
 
 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 {
-        u32 reg = bank->base;
+        void __iomem *reg = bank->base;
 
         switch (bank->method) {
         case METHOD_MPUIO:
@@ -428,6 +519,9 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
         case METHOD_GPIO_730:
                 reg += OMAP730_GPIO_INT_STATUS;
                 break;
+        case METHOD_GPIO_24XX:
+                reg += OMAP24XX_GPIO_IRQSTATUS1;
+                break;
         default:
                 BUG();
                 return;
@@ -442,7 +536,7 @@ static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
 
 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
 {
-        u32 reg = bank->base;
+        void __iomem *reg = bank->base;
         u32 l;
 
         switch (bank->method) {
@@ -477,6 +571,13 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
                 else
                         l |= gpio_mask;
                 break;
+        case METHOD_GPIO_24XX:
+                if (enable)
+                        reg += OMAP24XX_GPIO_SETIRQENABLE1;
+                else
+                        reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
+                l = gpio_mask;
+                break;
         default:
                 BUG();
                 return;
@@ -489,6 +590,50 @@ static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int ena
         _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
 }
 
+/*
+ * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
+ * 1510 does not seem to have a wake-up register. If JTAG is connected
+ * to the target, system will wake up always on GPIO events. While
+ * system is running all registered GPIO interrupts need to have wake-up
+ * enabled. When system is suspended, only selected GPIO interrupts need
+ * to have wake-up enabled.
+ */
+static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
+{
+        switch (bank->method) {
+        case METHOD_GPIO_1610:
+        case METHOD_GPIO_24XX:
+                spin_lock(&bank->lock);
+                if (enable)
+                        bank->suspend_wakeup |= (1 << gpio);
+                else
+                        bank->suspend_wakeup &= ~(1 << gpio);
+                spin_unlock(&bank->lock);
+                return 0;
+        default:
+                printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
+                       bank->method);
+                return -EINVAL;
+        }
+}
+
+/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
+static int gpio_wake_enable(unsigned int irq, unsigned int enable)
+{
+        unsigned int gpio = irq - IH_GPIO_BASE;
+        struct gpio_bank *bank;
+        int retval;
+
+        if (check_gpio(gpio) < 0)
+                return -ENODEV;
+        bank = get_gpio_bank(gpio);
+        spin_lock(&bank->lock);
+        retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
+        spin_unlock(&bank->lock);
+
+        return retval;
+}
+
 int omap_request_gpio(int gpio)
 {
         struct gpio_bank *bank;
@@ -505,15 +650,33 @@ int omap_request_gpio(int gpio)
                 return -1;
         }
         bank->reserved_map |= (1 << get_gpio_index(gpio));
+
+        /* Set trigger to none. You need to enable the trigger after request_irq */
+        _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
+
 #ifdef CONFIG_ARCH_OMAP1510
         if (bank->method == METHOD_GPIO_1510) {
-                u32 reg;
+                void __iomem *reg;
 
-                /* Claim the pin for the ARM */
+                /* Claim the pin for MPU */
                 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
                 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
         }
 #endif
+#ifdef CONFIG_ARCH_OMAP16XX
+        if (bank->method == METHOD_GPIO_1610) {
+                /* Enable wake-up during idle for dynamic tick */
+                void __iomem *reg = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
+                __raw_writel(1 << get_gpio_index(gpio), reg);
+        }
+#endif
+#ifdef CONFIG_ARCH_OMAP24XX
+        if (bank->method == METHOD_GPIO_24XX) {
+                /* Enable wake-up during idle for dynamic tick */
+                void __iomem *reg = bank->base + OMAP24XX_GPIO_SETWKUENA;
+                __raw_writel(1 << get_gpio_index(gpio), reg);
+        }
+#endif
         spin_unlock(&bank->lock);
 
         return 0;
@@ -533,6 +696,20 @@ void omap_free_gpio(int gpio)
                 spin_unlock(&bank->lock);
                 return;
         }
+#ifdef CONFIG_ARCH_OMAP16XX
+        if (bank->method == METHOD_GPIO_1610) {
+                /* Disable wake-up during idle for dynamic tick */
+                void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
+                __raw_writel(1 << get_gpio_index(gpio), reg);
+        }
+#endif
+#ifdef CONFIG_ARCH_OMAP24XX
+        if (bank->method == METHOD_GPIO_24XX) {
+                /* Disable wake-up during idle for dynamic tick */
+                void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
+                __raw_writel(1 << get_gpio_index(gpio), reg);
+        }
+#endif
         bank->reserved_map &= ~(1 << get_gpio_index(gpio));
         _set_gpio_direction(bank, get_gpio_index(gpio), 1);
         _set_gpio_irqenable(bank, gpio, 0);
@@ -552,7 +729,7 @@ void omap_free_gpio(int gpio)
 static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
                              struct pt_regs *regs)
 {
-        u32 isr_reg = 0;
+        void __iomem *isr_reg = NULL;
         u32 isr;
         unsigned int gpio_irq;
         struct gpio_bank *bank;
@@ -574,24 +751,30 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
         if (bank->method == METHOD_GPIO_730)
                 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
 #endif
+#ifdef CONFIG_ARCH_OMAP24XX
+        if (bank->method == METHOD_GPIO_24XX)
+                isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
+#endif
 
-        isr = __raw_readl(isr_reg);
-        _enable_gpio_irqbank(bank, isr, 0);
-        _clear_gpio_irqbank(bank, isr);
-        _enable_gpio_irqbank(bank, isr, 1);
-        desc->chip->unmask(irq);
-
-        if (unlikely(!isr))
-                return;
-
-        gpio_irq = bank->virtual_irq_start;
-        for (; isr != 0; isr >>= 1, gpio_irq++) {
-                struct irqdesc *d;
-                if (!(isr & 1))
-                        continue;
-                d = irq_desc + gpio_irq;
-                d->handle(gpio_irq, d, regs);
-        }
+        while(1) {
+                isr = __raw_readl(isr_reg);
+                _enable_gpio_irqbank(bank, isr, 0);
+                _clear_gpio_irqbank(bank, isr);
+                _enable_gpio_irqbank(bank, isr, 1);
+                desc->chip->unmask(irq);
+
+                if (!isr)
+                        break;
+
+                gpio_irq = bank->virtual_irq_start;
+                for (; isr != 0; isr >>= 1, gpio_irq++) {
+                        struct irqdesc *d;
+                        if (!(isr & 1))
+                                continue;
+                        d = irq_desc + gpio_irq;
+                        desc_handle_irq(gpio_irq, d, regs);
+                }
+        }
 }
 
 static void gpio_ack_irq(unsigned int irq)
@@ -613,14 +796,10 @@ static void gpio_mask_irq(unsigned int irq)
 static void gpio_unmask_irq(unsigned int irq)
 {
         unsigned int gpio = irq - IH_GPIO_BASE;
+        unsigned int gpio_idx = get_gpio_index(gpio);
         struct gpio_bank *bank = get_gpio_bank(gpio);
 
-        if (_get_gpio_edge_ctrl(bank, get_gpio_index(gpio)) == OMAP_GPIO_NO_EDGE) {
-                printk(KERN_ERR "OMAP GPIO %d: trying to enable GPIO IRQ while no edge is set\n",
-                       gpio);
-                _set_gpio_edge_ctrl(bank, get_gpio_index(gpio), OMAP_GPIO_RISING_EDGE);
-        }
-        _set_gpio_irqenable(bank, gpio, 1);
+        _set_gpio_irqenable(bank, gpio_idx, 1);
 }
 
 static void mpuio_ack_irq(unsigned int irq)
@@ -645,9 +824,11 @@ static void mpuio_unmask_irq(unsigned int irq)
 }
 
 static struct irqchip gpio_irq_chip = {
-        .ack    = gpio_ack_irq,
-        .mask   = gpio_mask_irq,
-        .unmask = gpio_unmask_irq,
+        .ack            = gpio_ack_irq,
+        .mask           = gpio_mask_irq,
+        .unmask         = gpio_unmask_irq,
+        .set_type       = gpio_irq_type,
+        .set_wake       = gpio_wake_enable,
 };
 
 static struct irqchip mpuio_irq_chip = {
@@ -657,6 +838,7 @@ static struct irqchip mpuio_irq_chip = {
 };
 
 static int initialized = 0;
+static struct clk * gpio_ck = NULL;
 
 static int __init _omap_gpio_init(void)
 {
@@ -665,6 +847,14 @@ static int __init _omap_gpio_init(void)
 
         initialized = 1;
 
+        if (cpu_is_omap1510()) {
+                gpio_ck = clk_get(NULL, "arm_gpio_ck");
+                if (IS_ERR(gpio_ck))
+                        printk("Could not get arm_gpio_ck\n");
+                else
+                        clk_use(gpio_ck);
+        }
+
 #ifdef CONFIG_ARCH_OMAP1510
         if (cpu_is_omap1510()) {
                 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
@@ -674,7 +864,7 @@ static int __init _omap_gpio_init(void)
 #endif
 #if defined(CONFIG_ARCH_OMAP16XX)
         if (cpu_is_omap16xx()) {
-                int rev;
+                u32 rev;
 
                 gpio_bank_count = 5;
                 gpio_bank = gpio_bank_1610;
@@ -690,6 +880,17 @@ static int __init _omap_gpio_init(void)
                 gpio_bank = gpio_bank_730;
         }
 #endif
+#ifdef CONFIG_ARCH_OMAP24XX
+        if (cpu_is_omap24xx()) {
+                int rev;
+
+                gpio_bank_count = 4;
+                gpio_bank = gpio_bank_24xx;
+                rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
+                printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n",
+                        (rev >> 4) & 0x0f, rev & 0x0f);
+        }
+#endif
         for (i = 0; i < gpio_bank_count; i++) {
                 int j, gpio_count = 16;
 
@@ -710,6 +911,7 @@ static int __init _omap_gpio_init(void)
                 if (bank->method == METHOD_GPIO_1610) {
                         __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
                         __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
+                        __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
                 }
 #endif
 #ifdef CONFIG_ARCH_OMAP730
@@ -720,6 +922,14 @@ static int __init _omap_gpio_init(void)
                         gpio_count = 32; /* 730 has 32-bit GPIOs */
                 }
 #endif
+#ifdef CONFIG_ARCH_OMAP24XX
+                if (bank->method == METHOD_GPIO_24XX) {
+                        __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
+                        __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
+
+                        gpio_count = 32;
+                }
+#endif
                 for (j = bank->virtual_irq_start;
                      j < bank->virtual_irq_start + gpio_count; j++) {
                         if (bank->method == METHOD_MPUIO)
@@ -735,12 +945,97 @@ static int __init _omap_gpio_init(void)
 
         /* Enable system clock for GPIO module.
          * The CAM_CLK_CTRL *is* really the right place. */
-        if (cpu_is_omap1610() || cpu_is_omap1710())
+        if (cpu_is_omap16xx())
                 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
 
         return 0;
 }
 
+#if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
+static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
+{
+        int i;
+
+        if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
+                return 0;
+
+        for (i = 0; i < gpio_bank_count; i++) {
+                struct gpio_bank *bank = &gpio_bank[i];
+                void __iomem *wake_status;
+                void __iomem *wake_clear;
+                void __iomem *wake_set;
+
+                switch (bank->method) {
+                case METHOD_GPIO_1610:
+                        wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
+                        wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
+                        wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
+                        break;
+                case METHOD_GPIO_24XX:
+                        wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
+                        wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
+                        wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
+                        break;
+                default:
+                        continue;
+                }
+
+                spin_lock(&bank->lock);
+                bank->saved_wakeup = __raw_readl(wake_status);
+                __raw_writel(0xffffffff, wake_clear);
+                __raw_writel(bank->suspend_wakeup, wake_set);
+                spin_unlock(&bank->lock);
+        }
+
+        return 0;
+}
+
+static int omap_gpio_resume(struct sys_device *dev)
+{
+        int i;
+
+        if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
+                return 0;
+
+        for (i = 0; i < gpio_bank_count; i++) {
+                struct gpio_bank *bank = &gpio_bank[i];
+                void __iomem *wake_clear;
+                void __iomem *wake_set;
+
+                switch (bank->method) {
+                case METHOD_GPIO_1610:
+                        wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
+                        wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
+                        break;
+                case METHOD_GPIO_24XX:
+                        wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
+                        wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
+                        break;
+                default:
+                        continue;
+                }
+
+                spin_lock(&bank->lock);
+                __raw_writel(0xffffffff, wake_clear);
+                __raw_writel(bank->saved_wakeup, wake_set);
+                spin_unlock(&bank->lock);
+        }
+
+        return 0;
+}
+
+static struct sysdev_class omap_gpio_sysclass = {
+        set_kset_name("gpio"),
+        .suspend        = omap_gpio_suspend,
+        .resume         = omap_gpio_resume,
+};
+
+static struct sys_device omap_gpio_device = {
+        .id             = 0,
+        .cls            = &omap_gpio_sysclass,
+};
+#endif
+
 /*
  * This may get called early from board specific init
  */
@@ -752,11 +1047,30 @@ int omap_gpio_init(void)
                 return 0;
 }
 
+static int __init omap_gpio_sysinit(void)
+{
+        int ret = 0;
+
+        if (!initialized)
+                ret = _omap_gpio_init();
+
+#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
+        if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
+                if (ret == 0) {
+                        ret = sysdev_class_register(&omap_gpio_sysclass);
+                        if (ret == 0)
+                                ret = sysdev_register(&omap_gpio_device);
+                }
+        }
+#endif
+
+        return ret;
+}
+
 EXPORT_SYMBOL(omap_request_gpio);
 EXPORT_SYMBOL(omap_free_gpio);
 EXPORT_SYMBOL(omap_set_gpio_direction);
 EXPORT_SYMBOL(omap_set_gpio_dataout);
 EXPORT_SYMBOL(omap_get_gpio_datain);
-EXPORT_SYMBOL(omap_set_gpio_edge_ctrl);
 
-arch_initcall(omap_gpio_init);
+arch_initcall(omap_gpio_sysinit);