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Diffstat (limited to 'arch/arm/plat-omap/gpio.c')
-rw-r--r--arch/arm/plat-omap/gpio.c660
1 files changed, 222 insertions, 438 deletions
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index e0e2fa725269..8d493b992e70 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -21,6 +21,8 @@
21#include <linux/err.h> 21#include <linux/err.h>
22#include <linux/clk.h> 22#include <linux/clk.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/slab.h>
25#include <linux/pm_runtime.h>
24 26
25#include <mach/hardware.h> 27#include <mach/hardware.h>
26#include <asm/irq.h> 28#include <asm/irq.h>
@@ -32,7 +34,6 @@
32/* 34/*
33 * OMAP1510 GPIO registers 35 * OMAP1510 GPIO registers
34 */ 36 */
35#define OMAP1510_GPIO_BASE 0xfffce000
36#define OMAP1510_GPIO_DATA_INPUT 0x00 37#define OMAP1510_GPIO_DATA_INPUT 0x00
37#define OMAP1510_GPIO_DATA_OUTPUT 0x04 38#define OMAP1510_GPIO_DATA_OUTPUT 0x04
38#define OMAP1510_GPIO_DIR_CONTROL 0x08 39#define OMAP1510_GPIO_DIR_CONTROL 0x08
@@ -46,10 +47,6 @@
46/* 47/*
47 * OMAP1610 specific GPIO registers 48 * OMAP1610 specific GPIO registers
48 */ 49 */
49#define OMAP1610_GPIO1_BASE 0xfffbe400
50#define OMAP1610_GPIO2_BASE 0xfffbec00
51#define OMAP1610_GPIO3_BASE 0xfffbb400
52#define OMAP1610_GPIO4_BASE 0xfffbbc00
53#define OMAP1610_GPIO_REVISION 0x0000 50#define OMAP1610_GPIO_REVISION 0x0000
54#define OMAP1610_GPIO_SYSCONFIG 0x0010 51#define OMAP1610_GPIO_SYSCONFIG 0x0010
55#define OMAP1610_GPIO_SYSSTATUS 0x0014 52#define OMAP1610_GPIO_SYSSTATUS 0x0014
@@ -71,12 +68,6 @@
71/* 68/*
72 * OMAP7XX specific GPIO registers 69 * OMAP7XX specific GPIO registers
73 */ 70 */
74#define OMAP7XX_GPIO1_BASE 0xfffbc000
75#define OMAP7XX_GPIO2_BASE 0xfffbc800
76#define OMAP7XX_GPIO3_BASE 0xfffbd000
77#define OMAP7XX_GPIO4_BASE 0xfffbd800
78#define OMAP7XX_GPIO5_BASE 0xfffbe000
79#define OMAP7XX_GPIO6_BASE 0xfffbe800
80#define OMAP7XX_GPIO_DATA_INPUT 0x00 71#define OMAP7XX_GPIO_DATA_INPUT 0x00
81#define OMAP7XX_GPIO_DATA_OUTPUT 0x04 72#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
82#define OMAP7XX_GPIO_DIR_CONTROL 0x08 73#define OMAP7XX_GPIO_DIR_CONTROL 0x08
@@ -84,25 +75,10 @@
84#define OMAP7XX_GPIO_INT_MASK 0x10 75#define OMAP7XX_GPIO_INT_MASK 0x10
85#define OMAP7XX_GPIO_INT_STATUS 0x14 76#define OMAP7XX_GPIO_INT_STATUS 0x14
86 77
87#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
88
89/* 78/*
90 * omap24xx specific GPIO registers 79 * omap2+ specific GPIO registers
91 */ 80 */
92#define OMAP242X_GPIO1_BASE 0x48018000
93#define OMAP242X_GPIO2_BASE 0x4801a000
94#define OMAP242X_GPIO3_BASE 0x4801c000
95#define OMAP242X_GPIO4_BASE 0x4801e000
96
97#define OMAP243X_GPIO1_BASE 0x4900C000
98#define OMAP243X_GPIO2_BASE 0x4900E000
99#define OMAP243X_GPIO3_BASE 0x49010000
100#define OMAP243X_GPIO4_BASE 0x49012000
101#define OMAP243X_GPIO5_BASE 0x480B6000
102
103#define OMAP24XX_GPIO_REVISION 0x0000 81#define OMAP24XX_GPIO_REVISION 0x0000
104#define OMAP24XX_GPIO_SYSCONFIG 0x0010
105#define OMAP24XX_GPIO_SYSSTATUS 0x0014
106#define OMAP24XX_GPIO_IRQSTATUS1 0x0018 82#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
107#define OMAP24XX_GPIO_IRQSTATUS2 0x0028 83#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
108#define OMAP24XX_GPIO_IRQENABLE2 0x002c 84#define OMAP24XX_GPIO_IRQENABLE2 0x002c
@@ -126,7 +102,6 @@
126#define OMAP24XX_GPIO_SETDATAOUT 0x0094 102#define OMAP24XX_GPIO_SETDATAOUT 0x0094
127 103
128#define OMAP4_GPIO_REVISION 0x0000 104#define OMAP4_GPIO_REVISION 0x0000
129#define OMAP4_GPIO_SYSCONFIG 0x0010
130#define OMAP4_GPIO_EOI 0x0020 105#define OMAP4_GPIO_EOI 0x0020
131#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024 106#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
132#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028 107#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
@@ -138,7 +113,6 @@
138#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040 113#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
139#define OMAP4_GPIO_IRQWAKEN0 0x0044 114#define OMAP4_GPIO_IRQWAKEN0 0x0044
140#define OMAP4_GPIO_IRQWAKEN1 0x0048 115#define OMAP4_GPIO_IRQWAKEN1 0x0048
141#define OMAP4_GPIO_SYSSTATUS 0x0114
142#define OMAP4_GPIO_IRQENABLE1 0x011c 116#define OMAP4_GPIO_IRQENABLE1 0x011c
143#define OMAP4_GPIO_WAKE_EN 0x0120 117#define OMAP4_GPIO_WAKE_EN 0x0120
144#define OMAP4_GPIO_IRQSTATUS2 0x0128 118#define OMAP4_GPIO_IRQSTATUS2 0x0128
@@ -159,26 +133,6 @@
159#define OMAP4_GPIO_SETWKUENA 0x0184 133#define OMAP4_GPIO_SETWKUENA 0x0184
160#define OMAP4_GPIO_CLEARDATAOUT 0x0190 134#define OMAP4_GPIO_CLEARDATAOUT 0x0190
161#define OMAP4_GPIO_SETDATAOUT 0x0194 135#define OMAP4_GPIO_SETDATAOUT 0x0194
162/*
163 * omap34xx specific GPIO registers
164 */
165
166#define OMAP34XX_GPIO1_BASE 0x48310000
167#define OMAP34XX_GPIO2_BASE 0x49050000
168#define OMAP34XX_GPIO3_BASE 0x49052000
169#define OMAP34XX_GPIO4_BASE 0x49054000
170#define OMAP34XX_GPIO5_BASE 0x49056000
171#define OMAP34XX_GPIO6_BASE 0x49058000
172
173/*
174 * OMAP44XX specific GPIO registers
175 */
176#define OMAP44XX_GPIO1_BASE 0x4a310000
177#define OMAP44XX_GPIO2_BASE 0x48055000
178#define OMAP44XX_GPIO3_BASE 0x48057000
179#define OMAP44XX_GPIO4_BASE 0x48059000
180#define OMAP44XX_GPIO5_BASE 0x4805B000
181#define OMAP44XX_GPIO6_BASE 0x4805D000
182 136
183struct gpio_bank { 137struct gpio_bank {
184 unsigned long pbase; 138 unsigned long pbase;
@@ -190,14 +144,12 @@ struct gpio_bank {
190 u32 suspend_wakeup; 144 u32 suspend_wakeup;
191 u32 saved_wakeup; 145 u32 saved_wakeup;
192#endif 146#endif
193#ifdef CONFIG_ARCH_OMAP2PLUS
194 u32 non_wakeup_gpios; 147 u32 non_wakeup_gpios;
195 u32 enabled_non_wakeup_gpios; 148 u32 enabled_non_wakeup_gpios;
196 149
197 u32 saved_datain; 150 u32 saved_datain;
198 u32 saved_fallingdetect; 151 u32 saved_fallingdetect;
199 u32 saved_risingdetect; 152 u32 saved_risingdetect;
200#endif
201 u32 level_mask; 153 u32 level_mask;
202 u32 toggle_mask; 154 u32 toggle_mask;
203 spinlock_t lock; 155 spinlock_t lock;
@@ -205,104 +157,13 @@ struct gpio_bank {
205 struct clk *dbck; 157 struct clk *dbck;
206 u32 mod_usage; 158 u32 mod_usage;
207 u32 dbck_enable_mask; 159 u32 dbck_enable_mask;
160 struct device *dev;
161 bool dbck_flag;
162 int stride;
208}; 163};
209 164
210#define METHOD_MPUIO 0
211#define METHOD_GPIO_1510 1
212#define METHOD_GPIO_1610 2
213#define METHOD_GPIO_7XX 3
214#define METHOD_GPIO_24XX 5
215#define METHOD_GPIO_44XX 6
216
217#ifdef CONFIG_ARCH_OMAP16XX
218static struct gpio_bank gpio_bank_1610[5] = {
219 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
220 METHOD_MPUIO },
221 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
222 METHOD_GPIO_1610 },
223 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
224 METHOD_GPIO_1610 },
225 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
226 METHOD_GPIO_1610 },
227 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
228 METHOD_GPIO_1610 },
229};
230#endif
231
232#ifdef CONFIG_ARCH_OMAP15XX
233static struct gpio_bank gpio_bank_1510[2] = {
234 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
235 METHOD_MPUIO },
236 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
237 METHOD_GPIO_1510 }
238};
239#endif
240
241#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
242static struct gpio_bank gpio_bank_7xx[7] = {
243 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
244 METHOD_MPUIO },
245 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
246 METHOD_GPIO_7XX },
247 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
248 METHOD_GPIO_7XX },
249 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
250 METHOD_GPIO_7XX },
251 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
252 METHOD_GPIO_7XX },
253 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
254 METHOD_GPIO_7XX },
255 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
256 METHOD_GPIO_7XX },
257};
258#endif
259
260#ifdef CONFIG_ARCH_OMAP2
261
262static struct gpio_bank gpio_bank_242x[4] = {
263 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
264 METHOD_GPIO_24XX },
265 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
266 METHOD_GPIO_24XX },
267 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
268 METHOD_GPIO_24XX },
269 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
270 METHOD_GPIO_24XX },
271};
272
273static struct gpio_bank gpio_bank_243x[5] = {
274 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
275 METHOD_GPIO_24XX },
276 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
277 METHOD_GPIO_24XX },
278 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
279 METHOD_GPIO_24XX },
280 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
281 METHOD_GPIO_24XX },
282 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
283 METHOD_GPIO_24XX },
284};
285
286#endif
287
288#ifdef CONFIG_ARCH_OMAP3 165#ifdef CONFIG_ARCH_OMAP3
289static struct gpio_bank gpio_bank_34xx[6] = {
290 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
291 METHOD_GPIO_24XX },
292 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
293 METHOD_GPIO_24XX },
294 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
295 METHOD_GPIO_24XX },
296 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
297 METHOD_GPIO_24XX },
298 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
299 METHOD_GPIO_24XX },
300 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
301 METHOD_GPIO_24XX },
302};
303
304struct omap3_gpio_regs { 166struct omap3_gpio_regs {
305 u32 sysconfig;
306 u32 irqenable1; 167 u32 irqenable1;
307 u32 irqenable2; 168 u32 irqenable2;
308 u32 wake_en; 169 u32 wake_en;
@@ -318,26 +179,16 @@ struct omap3_gpio_regs {
318static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; 179static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
319#endif 180#endif
320 181
321#ifdef CONFIG_ARCH_OMAP4 182/*
322static struct gpio_bank gpio_bank_44xx[6] = { 183 * TODO: Cleanup gpio_bank usage as it is having information
323 { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE, 184 * related to all instances of the device
324 METHOD_GPIO_44XX }, 185 */
325 { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32, 186static struct gpio_bank *gpio_bank;
326 METHOD_GPIO_44XX },
327 { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
328 METHOD_GPIO_44XX },
329 { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
330 METHOD_GPIO_44XX },
331 { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
332 METHOD_GPIO_44XX },
333 { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
334 METHOD_GPIO_44XX },
335};
336 187
337#endif 188static int bank_width;
338 189
339static struct gpio_bank *gpio_bank; 190/* TODO: Analyze removing gpio_bank_count usage from driver code */
340static int gpio_bank_count; 191int gpio_bank_count;
341 192
342static inline struct gpio_bank *get_gpio_bank(int gpio) 193static inline struct gpio_bank *get_gpio_bank(int gpio)
343{ 194{
@@ -417,7 +268,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
417 switch (bank->method) { 268 switch (bank->method) {
418#ifdef CONFIG_ARCH_OMAP1 269#ifdef CONFIG_ARCH_OMAP1
419 case METHOD_MPUIO: 270 case METHOD_MPUIO:
420 reg += OMAP_MPUIO_IO_CNTL; 271 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
421 break; 272 break;
422#endif 273#endif
423#ifdef CONFIG_ARCH_OMAP15XX 274#ifdef CONFIG_ARCH_OMAP15XX
@@ -465,7 +316,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
465 switch (bank->method) { 316 switch (bank->method) {
466#ifdef CONFIG_ARCH_OMAP1 317#ifdef CONFIG_ARCH_OMAP1
467 case METHOD_MPUIO: 318 case METHOD_MPUIO:
468 reg += OMAP_MPUIO_OUTPUT; 319 reg += OMAP_MPUIO_OUTPUT / bank->stride;
469 l = __raw_readl(reg); 320 l = __raw_readl(reg);
470 if (enable) 321 if (enable)
471 l |= 1 << gpio; 322 l |= 1 << gpio;
@@ -537,7 +388,7 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
537 switch (bank->method) { 388 switch (bank->method) {
538#ifdef CONFIG_ARCH_OMAP1 389#ifdef CONFIG_ARCH_OMAP1
539 case METHOD_MPUIO: 390 case METHOD_MPUIO:
540 reg += OMAP_MPUIO_INPUT_LATCH; 391 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
541 break; 392 break;
542#endif 393#endif
543#ifdef CONFIG_ARCH_OMAP15XX 394#ifdef CONFIG_ARCH_OMAP15XX
@@ -583,7 +434,7 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
583 switch (bank->method) { 434 switch (bank->method) {
584#ifdef CONFIG_ARCH_OMAP1 435#ifdef CONFIG_ARCH_OMAP1
585 case METHOD_MPUIO: 436 case METHOD_MPUIO:
586 reg += OMAP_MPUIO_OUTPUT; 437 reg += OMAP_MPUIO_OUTPUT / bank->stride;
587 break; 438 break;
588#endif 439#endif
589#ifdef CONFIG_ARCH_OMAP15XX 440#ifdef CONFIG_ARCH_OMAP15XX
@@ -642,6 +493,9 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
642 u32 val; 493 u32 val;
643 u32 l; 494 u32 l;
644 495
496 if (!bank->dbck_flag)
497 return;
498
645 if (debounce < 32) 499 if (debounce < 32)
646 debounce = 0x01; 500 debounce = 0x01;
647 else if (debounce > 7936) 501 else if (debounce > 7936)
@@ -651,7 +505,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
651 505
652 l = 1 << get_gpio_index(gpio); 506 l = 1 << get_gpio_index(gpio);
653 507
654 if (cpu_is_omap44xx()) 508 if (bank->method == METHOD_GPIO_44XX)
655 reg += OMAP4_GPIO_DEBOUNCINGTIME; 509 reg += OMAP4_GPIO_DEBOUNCINGTIME;
656 else 510 else
657 reg += OMAP24XX_GPIO_DEBOUNCE_VAL; 511 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
@@ -659,7 +513,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
659 __raw_writel(debounce, reg); 513 __raw_writel(debounce, reg);
660 514
661 reg = bank->base; 515 reg = bank->base;
662 if (cpu_is_omap44xx()) 516 if (bank->method == METHOD_GPIO_44XX)
663 reg += OMAP4_GPIO_DEBOUNCENABLE; 517 reg += OMAP4_GPIO_DEBOUNCENABLE;
664 else 518 else
665 reg += OMAP24XX_GPIO_DEBOUNCE_EN; 519 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
@@ -668,12 +522,10 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
668 522
669 if (debounce) { 523 if (debounce) {
670 val |= l; 524 val |= l;
671 if (cpu_is_omap34xx() || cpu_is_omap44xx()) 525 clk_enable(bank->dbck);
672 clk_enable(bank->dbck);
673 } else { 526 } else {
674 val &= ~l; 527 val &= ~l;
675 if (cpu_is_omap34xx() || cpu_is_omap44xx()) 528 clk_disable(bank->dbck);
676 clk_disable(bank->dbck);
677 } 529 }
678 bank->dbck_enable_mask = val; 530 bank->dbck_enable_mask = val;
679 531
@@ -769,7 +621,7 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
769 621
770 switch (bank->method) { 622 switch (bank->method) {
771 case METHOD_MPUIO: 623 case METHOD_MPUIO:
772 reg += OMAP_MPUIO_GPIO_INT_EDGE; 624 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
773 break; 625 break;
774#ifdef CONFIG_ARCH_OMAP15XX 626#ifdef CONFIG_ARCH_OMAP15XX
775 case METHOD_GPIO_1510: 627 case METHOD_GPIO_1510:
@@ -803,7 +655,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
803 switch (bank->method) { 655 switch (bank->method) {
804#ifdef CONFIG_ARCH_OMAP1 656#ifdef CONFIG_ARCH_OMAP1
805 case METHOD_MPUIO: 657 case METHOD_MPUIO:
806 reg += OMAP_MPUIO_GPIO_INT_EDGE; 658 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
807 l = __raw_readl(reg); 659 l = __raw_readl(reg);
808 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 660 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
809 bank->toggle_mask |= 1 << gpio; 661 bank->toggle_mask |= 1 << gpio;
@@ -989,7 +841,7 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
989 switch (bank->method) { 841 switch (bank->method) {
990#ifdef CONFIG_ARCH_OMAP1 842#ifdef CONFIG_ARCH_OMAP1
991 case METHOD_MPUIO: 843 case METHOD_MPUIO:
992 reg += OMAP_MPUIO_GPIO_MASKIT; 844 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
993 mask = 0xffff; 845 mask = 0xffff;
994 inv = 1; 846 inv = 1;
995 break; 847 break;
@@ -1046,7 +898,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
1046 switch (bank->method) { 898 switch (bank->method) {
1047#ifdef CONFIG_ARCH_OMAP1 899#ifdef CONFIG_ARCH_OMAP1
1048 case METHOD_MPUIO: 900 case METHOD_MPUIO:
1049 reg += OMAP_MPUIO_GPIO_MASKIT; 901 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1050 l = __raw_readl(reg); 902 l = __raw_readl(reg);
1051 if (enable) 903 if (enable)
1052 l &= ~(gpio_mask); 904 l &= ~(gpio_mask);
@@ -1296,7 +1148,8 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1296 bank = get_irq_data(irq); 1148 bank = get_irq_data(irq);
1297#ifdef CONFIG_ARCH_OMAP1 1149#ifdef CONFIG_ARCH_OMAP1
1298 if (bank->method == METHOD_MPUIO) 1150 if (bank->method == METHOD_MPUIO)
1299 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; 1151 isr_reg = bank->base +
1152 OMAP_MPUIO_GPIO_INT / bank->stride;
1300#endif 1153#endif
1301#ifdef CONFIG_ARCH_OMAP15XX 1154#ifdef CONFIG_ARCH_OMAP15XX
1302 if (bank->method == METHOD_GPIO_1510) 1155 if (bank->method == METHOD_GPIO_1510)
@@ -1494,7 +1347,8 @@ static int omap_mpuio_suspend_noirq(struct device *dev)
1494{ 1347{
1495 struct platform_device *pdev = to_platform_device(dev); 1348 struct platform_device *pdev = to_platform_device(dev);
1496 struct gpio_bank *bank = platform_get_drvdata(pdev); 1349 struct gpio_bank *bank = platform_get_drvdata(pdev);
1497 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; 1350 void __iomem *mask_reg = bank->base +
1351 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1498 unsigned long flags; 1352 unsigned long flags;
1499 1353
1500 spin_lock_irqsave(&bank->lock, flags); 1354 spin_lock_irqsave(&bank->lock, flags);
@@ -1509,7 +1363,8 @@ static int omap_mpuio_resume_noirq(struct device *dev)
1509{ 1363{
1510 struct platform_device *pdev = to_platform_device(dev); 1364 struct platform_device *pdev = to_platform_device(dev);
1511 struct gpio_bank *bank = platform_get_drvdata(pdev); 1365 struct gpio_bank *bank = platform_get_drvdata(pdev);
1512 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; 1366 void __iomem *mask_reg = bank->base +
1367 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1513 unsigned long flags; 1368 unsigned long flags;
1514 1369
1515 spin_lock_irqsave(&bank->lock, flags); 1370 spin_lock_irqsave(&bank->lock, flags);
@@ -1545,7 +1400,8 @@ static struct platform_device omap_mpuio_device = {
1545 1400
1546static inline void mpuio_init(void) 1401static inline void mpuio_init(void)
1547{ 1402{
1548 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); 1403 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1404 platform_set_drvdata(&omap_mpuio_device, bank);
1549 1405
1550 if (platform_driver_register(&omap_mpuio_driver) == 0) 1406 if (platform_driver_register(&omap_mpuio_driver) == 0)
1551 (void) platform_device_register(&omap_mpuio_device); 1407 (void) platform_device_register(&omap_mpuio_device);
@@ -1588,7 +1444,7 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
1588 1444
1589 switch (bank->method) { 1445 switch (bank->method) {
1590 case METHOD_MPUIO: 1446 case METHOD_MPUIO:
1591 reg += OMAP_MPUIO_IO_CNTL; 1447 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1592 break; 1448 break;
1593 case METHOD_GPIO_1510: 1449 case METHOD_GPIO_1510:
1594 reg += OMAP1510_GPIO_DIR_CONTROL; 1450 reg += OMAP1510_GPIO_DIR_CONTROL;
@@ -1650,6 +1506,13 @@ static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1650 unsigned long flags; 1506 unsigned long flags;
1651 1507
1652 bank = container_of(chip, struct gpio_bank, chip); 1508 bank = container_of(chip, struct gpio_bank, chip);
1509
1510 if (!bank->dbck) {
1511 bank->dbck = clk_get(bank->dev, "dbclk");
1512 if (IS_ERR(bank->dbck))
1513 dev_err(bank->dev, "Could not get gpio dbck\n");
1514 }
1515
1653 spin_lock_irqsave(&bank->lock, flags); 1516 spin_lock_irqsave(&bank->lock, flags);
1654 _set_gpio_debounce(bank, offset, debounce); 1517 _set_gpio_debounce(bank, offset, debounce);
1655 spin_unlock_irqrestore(&bank->lock, flags); 1518 spin_unlock_irqrestore(&bank->lock, flags);
@@ -1678,34 +1541,16 @@ static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1678 1541
1679/*---------------------------------------------------------------------*/ 1542/*---------------------------------------------------------------------*/
1680 1543
1681static int initialized; 1544static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1682#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
1683static struct clk * gpio_ick;
1684#endif
1685
1686#if defined(CONFIG_ARCH_OMAP2)
1687static struct clk * gpio_fck;
1688#endif
1689
1690#if defined(CONFIG_ARCH_OMAP2430)
1691static struct clk * gpio5_ick;
1692static struct clk * gpio5_fck;
1693#endif
1694
1695#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1696static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1697#endif
1698
1699static void __init omap_gpio_show_rev(void)
1700{ 1545{
1701 u32 rev; 1546 u32 rev;
1702 1547
1703 if (cpu_is_omap16xx()) 1548 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1704 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); 1549 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1705 else if (cpu_is_omap24xx() || cpu_is_omap34xx()) 1550 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1706 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1551 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1707 else if (cpu_is_omap44xx()) 1552 else if (cpu_is_omap44xx())
1708 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION); 1553 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1709 else 1554 else
1710 return; 1555 return;
1711 1556
@@ -1718,250 +1563,190 @@ static void __init omap_gpio_show_rev(void)
1718 */ 1563 */
1719static struct lock_class_key gpio_lock_class; 1564static struct lock_class_key gpio_lock_class;
1720 1565
1721static int __init _omap_gpio_init(void) 1566static inline int init_gpio_info(struct platform_device *pdev)
1722{ 1567{
1723 int i; 1568 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1724 int gpio = 0; 1569 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1725 struct gpio_bank *bank; 1570 GFP_KERNEL);
1726 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ 1571 if (!gpio_bank) {
1727 char clk_name[11]; 1572 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1728 1573 return -ENOMEM;
1729 initialized = 1;
1730
1731#if defined(CONFIG_ARCH_OMAP1)
1732 if (cpu_is_omap15xx()) {
1733 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1734 if (IS_ERR(gpio_ick))
1735 printk("Could not get arm_gpio_ck\n");
1736 else
1737 clk_enable(gpio_ick);
1738 } 1574 }
1739#endif 1575 return 0;
1740#if defined(CONFIG_ARCH_OMAP2) 1576}
1741 if (cpu_class_is_omap2()) {
1742 gpio_ick = clk_get(NULL, "gpios_ick");
1743 if (IS_ERR(gpio_ick))
1744 printk("Could not get gpios_ick\n");
1745 else
1746 clk_enable(gpio_ick);
1747 gpio_fck = clk_get(NULL, "gpios_fck");
1748 if (IS_ERR(gpio_fck))
1749 printk("Could not get gpios_fck\n");
1750 else
1751 clk_enable(gpio_fck);
1752 1577
1753 /* 1578/* TODO: Cleanup cpu_is_* checks */
1754 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK 1579static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1755 */ 1580{
1756#if defined(CONFIG_ARCH_OMAP2430) 1581 if (cpu_class_is_omap2()) {
1757 if (cpu_is_omap2430()) { 1582 if (cpu_is_omap44xx()) {
1758 gpio5_ick = clk_get(NULL, "gpio5_ick"); 1583 __raw_writel(0xffffffff, bank->base +
1759 if (IS_ERR(gpio5_ick)) 1584 OMAP4_GPIO_IRQSTATUSCLR0);
1760 printk("Could not get gpio5_ick\n"); 1585 __raw_writel(0x00000000, bank->base +
1761 else 1586 OMAP4_GPIO_DEBOUNCENABLE);
1762 clk_enable(gpio5_ick); 1587 /* Initialize interface clk ungated, module enabled */
1763 gpio5_fck = clk_get(NULL, "gpio5_fck"); 1588 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1764 if (IS_ERR(gpio5_fck)) 1589 } else if (cpu_is_omap34xx()) {
1765 printk("Could not get gpio5_fck\n"); 1590 __raw_writel(0x00000000, bank->base +
1766 else 1591 OMAP24XX_GPIO_IRQENABLE1);
1767 clk_enable(gpio5_fck); 1592 __raw_writel(0xffffffff, bank->base +
1593 OMAP24XX_GPIO_IRQSTATUS1);
1594 __raw_writel(0x00000000, bank->base +
1595 OMAP24XX_GPIO_DEBOUNCE_EN);
1596
1597 /* Initialize interface clk ungated, module enabled */
1598 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1599 } else if (cpu_is_omap24xx()) {
1600 static const u32 non_wakeup_gpios[] = {
1601 0xe203ffc0, 0x08700040
1602 };
1603 if (id < ARRAY_SIZE(non_wakeup_gpios))
1604 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1768 } 1605 }
1769#endif 1606 } else if (cpu_class_is_omap1()) {
1770 } 1607 if (bank_is_mpuio(bank))
1771#endif 1608 __raw_writew(0xffff, bank->base +
1609 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1610 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1611 __raw_writew(0xffff, bank->base
1612 + OMAP1510_GPIO_INT_MASK);
1613 __raw_writew(0x0000, bank->base
1614 + OMAP1510_GPIO_INT_STATUS);
1615 }
1616 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1617 __raw_writew(0x0000, bank->base
1618 + OMAP1610_GPIO_IRQENABLE1);
1619 __raw_writew(0xffff, bank->base
1620 + OMAP1610_GPIO_IRQSTATUS1);
1621 __raw_writew(0x0014, bank->base
1622 + OMAP1610_GPIO_SYSCONFIG);
1772 1623
1773#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 1624 /*
1774 if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 1625 * Enable system clock for GPIO module.
1775 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { 1626 * The CAM_CLK_CTRL *is* really the right place.
1776 sprintf(clk_name, "gpio%d_ick", i + 1); 1627 */
1777 gpio_iclks[i] = clk_get(NULL, clk_name); 1628 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1778 if (IS_ERR(gpio_iclks[i])) 1629 ULPD_CAM_CLK_CTRL);
1779 printk(KERN_ERR "Could not get %s\n", clk_name); 1630 }
1780 else 1631 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1781 clk_enable(gpio_iclks[i]); 1632 __raw_writel(0xffffffff, bank->base
1633 + OMAP7XX_GPIO_INT_MASK);
1634 __raw_writel(0x00000000, bank->base
1635 + OMAP7XX_GPIO_INT_STATUS);
1782 } 1636 }
1783 } 1637 }
1784#endif 1638}
1785 1639
1640static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1641{
1642 int j;
1643 static int gpio;
1786 1644
1787#ifdef CONFIG_ARCH_OMAP15XX 1645 bank->mod_usage = 0;
1788 if (cpu_is_omap15xx()) { 1646 /*
1789 gpio_bank_count = 2; 1647 * REVISIT eventually switch from OMAP-specific gpio structs
1790 gpio_bank = gpio_bank_1510; 1648 * over to the generic ones
1791 bank_size = SZ_2K; 1649 */
1792 } 1650 bank->chip.request = omap_gpio_request;
1793#endif 1651 bank->chip.free = omap_gpio_free;
1794#if defined(CONFIG_ARCH_OMAP16XX) 1652 bank->chip.direction_input = gpio_input;
1795 if (cpu_is_omap16xx()) { 1653 bank->chip.get = gpio_get;
1796 gpio_bank_count = 5; 1654 bank->chip.direction_output = gpio_output;
1797 gpio_bank = gpio_bank_1610; 1655 bank->chip.set_debounce = gpio_debounce;
1798 bank_size = SZ_2K; 1656 bank->chip.set = gpio_set;
1799 } 1657 bank->chip.to_irq = gpio_2irq;
1800#endif 1658 if (bank_is_mpuio(bank)) {
1801#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 1659 bank->chip.label = "mpuio";
1802 if (cpu_is_omap7xx()) { 1660#ifdef CONFIG_ARCH_OMAP16XX
1803 gpio_bank_count = 7; 1661 bank->chip.dev = &omap_mpuio_device.dev;
1804 gpio_bank = gpio_bank_7xx;
1805 bank_size = SZ_2K;
1806 }
1807#endif
1808#ifdef CONFIG_ARCH_OMAP2
1809 if (cpu_is_omap242x()) {
1810 gpio_bank_count = 4;
1811 gpio_bank = gpio_bank_242x;
1812 }
1813 if (cpu_is_omap243x()) {
1814 gpio_bank_count = 5;
1815 gpio_bank = gpio_bank_243x;
1816 }
1817#endif 1662#endif
1818#ifdef CONFIG_ARCH_OMAP3 1663 bank->chip.base = OMAP_MPUIO(0);
1819 if (cpu_is_omap34xx()) { 1664 } else {
1820 gpio_bank_count = OMAP34XX_NR_GPIOS; 1665 bank->chip.label = "gpio";
1821 gpio_bank = gpio_bank_34xx; 1666 bank->chip.base = gpio;
1667 gpio += bank_width;
1822 } 1668 }
1823#endif 1669 bank->chip.ngpio = bank_width;
1824#ifdef CONFIG_ARCH_OMAP4 1670
1825 if (cpu_is_omap44xx()) { 1671 gpiochip_add(&bank->chip);
1826 gpio_bank_count = OMAP34XX_NR_GPIOS; 1672
1827 gpio_bank = gpio_bank_44xx; 1673 for (j = bank->virtual_irq_start;
1674 j < bank->virtual_irq_start + bank_width; j++) {
1675 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1676 set_irq_chip_data(j, bank);
1677 if (bank_is_mpuio(bank))
1678 set_irq_chip(j, &mpuio_irq_chip);
1679 else
1680 set_irq_chip(j, &gpio_irq_chip);
1681 set_irq_handler(j, handle_simple_irq);
1682 set_irq_flags(j, IRQF_VALID);
1828 } 1683 }
1829#endif 1684 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1830 for (i = 0; i < gpio_bank_count; i++) { 1685 set_irq_data(bank->irq, bank);
1831 int j, gpio_count = 16; 1686}
1832 1687
1833 bank = &gpio_bank[i]; 1688static int __devinit omap_gpio_probe(struct platform_device *pdev)
1834 spin_lock_init(&bank->lock); 1689{
1690 static int gpio_init_done;
1691 struct omap_gpio_platform_data *pdata;
1692 struct resource *res;
1693 int id;
1694 struct gpio_bank *bank;
1835 1695
1836 /* Static mapping, never released */ 1696 if (!pdev->dev.platform_data)
1837 bank->base = ioremap(bank->pbase, bank_size); 1697 return -EINVAL;
1838 if (!bank->base) {
1839 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
1840 continue;
1841 }
1842 1698
1843 if (bank_is_mpuio(bank)) 1699 pdata = pdev->dev.platform_data;
1844 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1845 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1846 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1847 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1848 }
1849 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1850 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1851 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1852 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1853 }
1854 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1855 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1856 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
1857 1700
1858 gpio_count = 32; /* 7xx has 32-bit GPIOs */ 1701 if (!gpio_init_done) {
1859 } 1702 int ret;
1860 1703
1861#ifdef CONFIG_ARCH_OMAP2PLUS 1704 ret = init_gpio_info(pdev);
1862 if ((bank->method == METHOD_GPIO_24XX) || 1705 if (ret)
1863 (bank->method == METHOD_GPIO_44XX)) { 1706 return ret;
1864 static const u32 non_wakeup_gpios[] = { 1707 }
1865 0xe203ffc0, 0x08700040
1866 };
1867 1708
1868 if (cpu_is_omap44xx()) { 1709 id = pdev->id;
1869 __raw_writel(0xffffffff, bank->base + 1710 bank = &gpio_bank[id];
1870 OMAP4_GPIO_IRQSTATUSCLR0);
1871 __raw_writew(0x0015, bank->base +
1872 OMAP4_GPIO_SYSCONFIG);
1873 __raw_writel(0x00000000, bank->base +
1874 OMAP4_GPIO_DEBOUNCENABLE);
1875 /*
1876 * Initialize interface clock ungated,
1877 * module enabled
1878 */
1879 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1880 } else {
1881 __raw_writel(0x00000000, bank->base +
1882 OMAP24XX_GPIO_IRQENABLE1);
1883 __raw_writel(0xffffffff, bank->base +
1884 OMAP24XX_GPIO_IRQSTATUS1);
1885 __raw_writew(0x0015, bank->base +
1886 OMAP24XX_GPIO_SYSCONFIG);
1887 __raw_writel(0x00000000, bank->base +
1888 OMAP24XX_GPIO_DEBOUNCE_EN);
1889
1890 /*
1891 * Initialize interface clock ungated,
1892 * module enabled
1893 */
1894 __raw_writel(0, bank->base +
1895 OMAP24XX_GPIO_CTRL);
1896 }
1897 if (cpu_is_omap24xx() &&
1898 i < ARRAY_SIZE(non_wakeup_gpios))
1899 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1900 gpio_count = 32;
1901 }
1902#endif
1903 1711
1904 bank->mod_usage = 0; 1712 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1905 /* REVISIT eventually switch from OMAP-specific gpio structs 1713 if (unlikely(!res)) {
1906 * over to the generic ones 1714 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1907 */ 1715 return -ENODEV;
1908 bank->chip.request = omap_gpio_request; 1716 }
1909 bank->chip.free = omap_gpio_free;
1910 bank->chip.direction_input = gpio_input;
1911 bank->chip.get = gpio_get;
1912 bank->chip.direction_output = gpio_output;
1913 bank->chip.set_debounce = gpio_debounce;
1914 bank->chip.set = gpio_set;
1915 bank->chip.to_irq = gpio_2irq;
1916 if (bank_is_mpuio(bank)) {
1917 bank->chip.label = "mpuio";
1918#ifdef CONFIG_ARCH_OMAP16XX
1919 bank->chip.dev = &omap_mpuio_device.dev;
1920#endif
1921 bank->chip.base = OMAP_MPUIO(0);
1922 } else {
1923 bank->chip.label = "gpio";
1924 bank->chip.base = gpio;
1925 gpio += gpio_count;
1926 }
1927 bank->chip.ngpio = gpio_count;
1928 1717
1929 gpiochip_add(&bank->chip); 1718 bank->irq = res->start;
1719 bank->virtual_irq_start = pdata->virtual_irq_start;
1720 bank->method = pdata->bank_type;
1721 bank->dev = &pdev->dev;
1722 bank->dbck_flag = pdata->dbck_flag;
1723 bank->stride = pdata->bank_stride;
1724 bank_width = pdata->bank_width;
1930 1725
1931 for (j = bank->virtual_irq_start; 1726 spin_lock_init(&bank->lock);
1932 j < bank->virtual_irq_start + gpio_count; j++) { 1727
1933 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); 1728 /* Static mapping, never released */
1934 set_irq_chip_data(j, bank); 1729 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1935 if (bank_is_mpuio(bank)) 1730 if (unlikely(!res)) {
1936 set_irq_chip(j, &mpuio_irq_chip); 1731 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1937 else 1732 return -ENODEV;
1938 set_irq_chip(j, &gpio_irq_chip); 1733 }
1939 set_irq_handler(j, handle_simple_irq); 1734
1940 set_irq_flags(j, IRQF_VALID); 1735 bank->base = ioremap(res->start, resource_size(res));
1941 } 1736 if (!bank->base) {
1942 set_irq_chained_handler(bank->irq, gpio_irq_handler); 1737 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1943 set_irq_data(bank->irq, bank); 1738 return -ENOMEM;
1944
1945 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1946 sprintf(clk_name, "gpio%d_dbck", i + 1);
1947 bank->dbck = clk_get(NULL, clk_name);
1948 if (IS_ERR(bank->dbck))
1949 printk(KERN_ERR "Could not get %s\n", clk_name);
1950 }
1951 } 1739 }
1952 1740
1953 /* Enable system clock for GPIO module. 1741 pm_runtime_enable(bank->dev);
1954 * The CAM_CLK_CTRL *is* really the right place. */ 1742 pm_runtime_get_sync(bank->dev);
1955 if (cpu_is_omap16xx())
1956 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1957 1743
1958 /* Enable autoidle for the OCP interface */ 1744 omap_gpio_mod_init(bank, id);
1959 if (cpu_is_omap24xx()) 1745 omap_gpio_chip_init(bank);
1960 omap_writel(1 << 0, 0x48019010); 1746 omap_gpio_show_rev(bank);
1961 if (cpu_is_omap34xx())
1962 omap_writel(1 << 0, 0x48306814);
1963 1747
1964 omap_gpio_show_rev(); 1748 if (!gpio_init_done)
1749 gpio_init_done = 1;
1965 1750
1966 return 0; 1751 return 0;
1967} 1752}
@@ -2256,8 +2041,6 @@ void omap_gpio_save_context(void)
2256 /* saving banks from 2-6 only since GPIO1 is in WKUP */ 2041 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2257 for (i = 1; i < gpio_bank_count; i++) { 2042 for (i = 1; i < gpio_bank_count; i++) {
2258 struct gpio_bank *bank = &gpio_bank[i]; 2043 struct gpio_bank *bank = &gpio_bank[i];
2259 gpio_context[i].sysconfig =
2260 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
2261 gpio_context[i].irqenable1 = 2044 gpio_context[i].irqenable1 =
2262 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); 2045 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2263 gpio_context[i].irqenable2 = 2046 gpio_context[i].irqenable2 =
@@ -2288,8 +2071,6 @@ void omap_gpio_restore_context(void)
2288 2071
2289 for (i = 1; i < gpio_bank_count; i++) { 2072 for (i = 1; i < gpio_bank_count; i++) {
2290 struct gpio_bank *bank = &gpio_bank[i]; 2073 struct gpio_bank *bank = &gpio_bank[i];
2291 __raw_writel(gpio_context[i].sysconfig,
2292 bank->base + OMAP24XX_GPIO_SYSCONFIG);
2293 __raw_writel(gpio_context[i].irqenable1, 2074 __raw_writel(gpio_context[i].irqenable1,
2294 bank->base + OMAP24XX_GPIO_IRQENABLE1); 2075 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2295 __raw_writel(gpio_context[i].irqenable2, 2076 __raw_writel(gpio_context[i].irqenable2,
@@ -2314,25 +2095,28 @@ void omap_gpio_restore_context(void)
2314} 2095}
2315#endif 2096#endif
2316 2097
2098static struct platform_driver omap_gpio_driver = {
2099 .probe = omap_gpio_probe,
2100 .driver = {
2101 .name = "omap_gpio",
2102 },
2103};
2104
2317/* 2105/*
2318 * This may get called early from board specific init 2106 * gpio driver register needs to be done before
2319 * for boards that have interrupts routed via FPGA. 2107 * machine_init functions access gpio APIs.
2108 * Hence omap_gpio_drv_reg() is a postcore_initcall.
2320 */ 2109 */
2321int __init omap_gpio_init(void) 2110static int __init omap_gpio_drv_reg(void)
2322{ 2111{
2323 if (!initialized) 2112 return platform_driver_register(&omap_gpio_driver);
2324 return _omap_gpio_init();
2325 else
2326 return 0;
2327} 2113}
2114postcore_initcall(omap_gpio_drv_reg);
2328 2115
2329static int __init omap_gpio_sysinit(void) 2116static int __init omap_gpio_sysinit(void)
2330{ 2117{
2331 int ret = 0; 2118 int ret = 0;
2332 2119
2333 if (!initialized)
2334 ret = _omap_gpio_init();
2335
2336 mpuio_init(); 2120 mpuio_init();
2337 2121
2338#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) 2122#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 06:24:12 -0500