aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-omap/dma.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/plat-omap/dma.c')
-rw-r--r--arch/arm/plat-omap/dma.c102
1 files changed, 68 insertions, 34 deletions
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 7fc8c045ad5d..def14ec265b3 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -10,6 +10,9 @@
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com> 10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. 11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 * 12 *
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 *
13 * Support functions for the OMAP internal DMA channels. 16 * Support functions for the OMAP internal DMA channels.
14 * 17 *
15 * This program is free software; you can redistribute it and/or modify 18 * This program is free software; you can redistribute it and/or modify
@@ -310,41 +313,62 @@ EXPORT_SYMBOL(omap_set_dma_transfer_params);
310 313
311void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) 314void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
312{ 315{
313 u16 w;
314
315 BUG_ON(omap_dma_in_1510_mode()); 316 BUG_ON(omap_dma_in_1510_mode());
316 317
317 if (cpu_class_is_omap2()) { 318 if (cpu_class_is_omap1()) {
318 REVISIT_24XX(); 319 u16 w;
319 return;
320 }
321 320
322 w = dma_read(CCR2(lch)); 321 w = dma_read(CCR2(lch));
323 w &= ~0x03; 322 w &= ~0x03;
324 323
325 switch (mode) { 324 switch (mode) {
326 case OMAP_DMA_CONSTANT_FILL: 325 case OMAP_DMA_CONSTANT_FILL:
327 w |= 0x01; 326 w |= 0x01;
328 break; 327 break;
329 case OMAP_DMA_TRANSPARENT_COPY: 328 case OMAP_DMA_TRANSPARENT_COPY:
330 w |= 0x02; 329 w |= 0x02;
331 break; 330 break;
332 case OMAP_DMA_COLOR_DIS: 331 case OMAP_DMA_COLOR_DIS:
333 break; 332 break;
334 default: 333 default:
335 BUG(); 334 BUG();
335 }
336 dma_write(w, CCR2(lch));
337
338 w = dma_read(LCH_CTRL(lch));
339 w &= ~0x0f;
340 /* Default is channel type 2D */
341 if (mode) {
342 dma_write((u16)color, COLOR_L(lch));
343 dma_write((u16)(color >> 16), COLOR_U(lch));
344 w |= 1; /* Channel type G */
345 }
346 dma_write(w, LCH_CTRL(lch));
336 } 347 }
337 dma_write(w, CCR2(lch));
338 348
339 w = dma_read(LCH_CTRL(lch)); 349 if (cpu_class_is_omap2()) {
340 w &= ~0x0f; 350 u32 val;
341 /* Default is channel type 2D */ 351
342 if (mode) { 352 val = dma_read(CCR(lch));
343 dma_write((u16)color, COLOR_L(lch)); 353 val &= ~((1 << 17) | (1 << 16));
344 dma_write((u16)(color >> 16), COLOR_U(lch)); 354
345 w |= 1; /* Channel type G */ 355 switch (mode) {
356 case OMAP_DMA_CONSTANT_FILL:
357 val |= 1 << 16;
358 break;
359 case OMAP_DMA_TRANSPARENT_COPY:
360 val |= 1 << 17;
361 break;
362 case OMAP_DMA_COLOR_DIS:
363 break;
364 default:
365 BUG();
366 }
367 dma_write(val, CCR(lch));
368
369 color &= 0xffffff;
370 dma_write(color, COLOR(lch));
346 } 371 }
347 dma_write(w, LCH_CTRL(lch));
348} 372}
349EXPORT_SYMBOL(omap_set_dma_color_mode); 373EXPORT_SYMBOL(omap_set_dma_color_mode);
350 374
@@ -851,7 +875,7 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio,
851 } 875 }
852 l = dma_read(CCR(lch)); 876 l = dma_read(CCR(lch));
853 l &= ~((1 << 6) | (1 << 26)); 877 l &= ~((1 << 6) | (1 << 26));
854 if (cpu_is_omap2430() || cpu_is_omap34xx()) 878 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
855 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); 879 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
856 else 880 else
857 l |= ((read_prio & 0x1) << 6); 881 l |= ((read_prio & 0x1) << 6);
@@ -1199,7 +1223,7 @@ static void create_dma_lch_chain(int lch_head, int lch_queue)
1199 * Failure: -EINVAL/-ENOMEM 1223 * Failure: -EINVAL/-ENOMEM
1200 */ 1224 */
1201int omap_request_dma_chain(int dev_id, const char *dev_name, 1225int omap_request_dma_chain(int dev_id, const char *dev_name,
1202 void (*callback) (int chain_id, u16 ch_status, 1226 void (*callback) (int lch, u16 ch_status,
1203 void *data), 1227 void *data),
1204 int *chain_id, int no_of_chans, int chain_mode, 1228 int *chain_id, int no_of_chans, int chain_mode,
1205 struct omap_dma_channel_params params) 1229 struct omap_dma_channel_params params)
@@ -1823,7 +1847,8 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1823#define omap1_dma_irq_handler NULL 1847#define omap1_dma_irq_handler NULL
1824#endif 1848#endif
1825 1849
1826#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 1850#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
1851 defined(CONFIG_ARCH_OMAP4)
1827 1852
1828static int omap2_dma_handle_ch(int ch) 1853static int omap2_dma_handle_ch(int ch)
1829{ 1854{
@@ -2318,6 +2343,9 @@ static int __init omap_init_dma(void)
2318 } else if (cpu_is_omap34xx()) { 2343 } else if (cpu_is_omap34xx()) {
2319 omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE); 2344 omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
2320 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; 2345 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2346 } else if (cpu_is_omap44xx()) {
2347 omap_dma_base = IO_ADDRESS(OMAP44XX_DMA4_BASE);
2348 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2321 } else { 2349 } else {
2322 pr_err("DMA init failed for unsupported omap\n"); 2350 pr_err("DMA init failed for unsupported omap\n");
2323 return -ENODEV; 2351 return -ENODEV;
@@ -2416,12 +2444,18 @@ static int __init omap_init_dma(void)
2416 } 2444 }
2417 } 2445 }
2418 2446
2419 if (cpu_is_omap2430() || cpu_is_omap34xx()) 2447 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2420 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, 2448 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2421 DMA_DEFAULT_FIFO_DEPTH, 0); 2449 DMA_DEFAULT_FIFO_DEPTH, 0);
2422 2450
2423 if (cpu_class_is_omap2()) 2451 if (cpu_class_is_omap2()) {
2424 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq); 2452 int irq;
2453 if (cpu_is_omap44xx())
2454 irq = INT_44XX_SDMA_IRQ0;
2455 else
2456 irq = INT_24XX_SDMA_IRQ0;
2457 setup_irq(irq, &omap24xx_dma_irq);
2458 }
2425 2459
2426 /* FIXME: Update LCD DMA to work on 24xx */ 2460 /* FIXME: Update LCD DMA to work on 24xx */
2427 if (cpu_class_is_omap1()) { 2461 if (cpu_class_is_omap1()) {