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-rw-r--r--arch/arm/plat-omap/dma.c764
1 files changed, 469 insertions, 295 deletions
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 39c637b0ffea..fac8e994f588 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/plat-omap/dma.c 2 * linux/arch/arm/plat-omap/dma.c
3 * 3 *
4 * Copyright (C) 2003 Nokia Corporation 4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com> 5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> 6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations 7 * Graphics DMA and LCD DMA graphics tranformations
@@ -25,11 +25,11 @@
25#include <linux/errno.h> 25#include <linux/errno.h>
26#include <linux/interrupt.h> 26#include <linux/interrupt.h>
27#include <linux/irq.h> 27#include <linux/irq.h>
28#include <linux/io.h>
28 29
29#include <asm/system.h> 30#include <asm/system.h>
30#include <asm/hardware.h> 31#include <asm/hardware.h>
31#include <asm/dma.h> 32#include <asm/dma.h>
32#include <asm/io.h>
33 33
34#include <asm/arch/tc.h> 34#include <asm/arch/tc.h>
35 35
@@ -43,13 +43,13 @@ enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
43enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; 43enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
44#endif 44#endif
45 45
46#define OMAP_DMA_ACTIVE 0x01 46#define OMAP_DMA_ACTIVE 0x01
47#define OMAP_DMA_CCR_EN (1 << 7) 47#define OMAP_DMA_CCR_EN (1 << 7)
48#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe 48#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
49 49
50#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) 50#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
51 51
52static int enable_1510_mode = 0; 52static int enable_1510_mode;
53 53
54struct omap_dma_lch { 54struct omap_dma_lch {
55 int next_lch; 55 int next_lch;
@@ -57,7 +57,7 @@ struct omap_dma_lch {
57 u16 saved_csr; 57 u16 saved_csr;
58 u16 enabled_irqs; 58 u16 enabled_irqs;
59 const char *dev_name; 59 const char *dev_name;
60 void (* callback)(int lch, u16 ch_status, void *data); 60 void (*callback)(int lch, u16 ch_status, void *data);
61 void *data; 61 void *data;
62 62
63#ifndef CONFIG_ARCH_OMAP1 63#ifndef CONFIG_ARCH_OMAP1
@@ -72,7 +72,6 @@ struct omap_dma_lch {
72 long flags; 72 long flags;
73}; 73};
74 74
75#ifndef CONFIG_ARCH_OMAP1
76struct dma_link_info { 75struct dma_link_info {
77 int *linked_dmach_q; 76 int *linked_dmach_q;
78 int no_of_lchs_linked; 77 int no_of_lchs_linked;
@@ -86,7 +85,9 @@ struct dma_link_info {
86 85
87}; 86};
88 87
89static struct dma_link_info dma_linked_lch[OMAP_LOGICAL_DMA_CH_COUNT]; 88static struct dma_link_info *dma_linked_lch;
89
90#ifndef CONFIG_ARCH_OMAP1
90 91
91/* Chain handling macros */ 92/* Chain handling macros */
92#define OMAP_DMA_CHAIN_QINIT(chain_id) \ 93#define OMAP_DMA_CHAIN_QINIT(chain_id) \
@@ -119,12 +120,15 @@ static struct dma_link_info dma_linked_lch[OMAP_LOGICAL_DMA_CH_COUNT];
119 dma_linked_lch[chain_id].q_count++; \ 120 dma_linked_lch[chain_id].q_count++; \
120 } while (0) 121 } while (0)
121#endif 122#endif
123
124static int dma_lch_count;
122static int dma_chan_count; 125static int dma_chan_count;
123 126
124static spinlock_t dma_chan_lock; 127static spinlock_t dma_chan_lock;
125static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT]; 128static struct omap_dma_lch *dma_chan;
129static void __iomem *omap_dma_base;
126 130
127static const u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = { 131static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
128 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3, 132 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
129 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7, 133 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
130 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10, 134 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
@@ -139,6 +143,24 @@ static inline void omap_enable_channel_irq(int lch);
139#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ 143#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
140 __func__); 144 __func__);
141 145
146#define dma_read(reg) \
147({ \
148 u32 __val; \
149 if (cpu_class_is_omap1()) \
150 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
151 else \
152 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
153 __val; \
154})
155
156#define dma_write(val, reg) \
157({ \
158 if (cpu_class_is_omap1()) \
159 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
160 else \
161 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
162})
163
142#ifdef CONFIG_ARCH_OMAP15XX 164#ifdef CONFIG_ARCH_OMAP15XX
143/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ 165/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
144int omap_dma_in_1510_mode(void) 166int omap_dma_in_1510_mode(void)
@@ -173,13 +195,14 @@ static inline void set_gdma_dev(int req, int dev)
173#define set_gdma_dev(req, dev) do {} while (0) 195#define set_gdma_dev(req, dev) do {} while (0)
174#endif 196#endif
175 197
198/* Omap1 only */
176static void clear_lch_regs(int lch) 199static void clear_lch_regs(int lch)
177{ 200{
178 int i; 201 int i;
179 u32 lch_base = OMAP_DMA_BASE + lch * 0x40; 202 void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
180 203
181 for (i = 0; i < 0x2c; i += 2) 204 for (i = 0; i < 0x2c; i += 2)
182 omap_writew(0, lch_base + i); 205 __raw_writew(0, lch_base + i);
183} 206}
184 207
185void omap_set_dma_priority(int lch, int dst_port, int priority) 208void omap_set_dma_priority(int lch, int dst_port, int priority)
@@ -212,33 +235,49 @@ void omap_set_dma_priority(int lch, int dst_port, int priority)
212 } 235 }
213 236
214 if (cpu_class_is_omap2()) { 237 if (cpu_class_is_omap2()) {
238 u32 ccr;
239
240 ccr = dma_read(CCR(lch));
215 if (priority) 241 if (priority)
216 OMAP_DMA_CCR_REG(lch) |= (1 << 6); 242 ccr |= (1 << 6);
217 else 243 else
218 OMAP_DMA_CCR_REG(lch) &= ~(1 << 6); 244 ccr &= ~(1 << 6);
245 dma_write(ccr, CCR(lch));
219 } 246 }
220} 247}
248EXPORT_SYMBOL(omap_set_dma_priority);
221 249
222void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, 250void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
223 int frame_count, int sync_mode, 251 int frame_count, int sync_mode,
224 int dma_trigger, int src_or_dst_synch) 252 int dma_trigger, int src_or_dst_synch)
225{ 253{
226 OMAP_DMA_CSDP_REG(lch) &= ~0x03; 254 u32 l;
227 OMAP_DMA_CSDP_REG(lch) |= data_type; 255
256 l = dma_read(CSDP(lch));
257 l &= ~0x03;
258 l |= data_type;
259 dma_write(l, CSDP(lch));
228 260
229 if (cpu_class_is_omap1()) { 261 if (cpu_class_is_omap1()) {
230 OMAP_DMA_CCR_REG(lch) &= ~(1 << 5); 262 u16 ccr;
263
264 ccr = dma_read(CCR(lch));
265 ccr &= ~(1 << 5);
231 if (sync_mode == OMAP_DMA_SYNC_FRAME) 266 if (sync_mode == OMAP_DMA_SYNC_FRAME)
232 OMAP_DMA_CCR_REG(lch) |= 1 << 5; 267 ccr |= 1 << 5;
268 dma_write(ccr, CCR(lch));
233 269
234 OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2); 270 ccr = dma_read(CCR2(lch));
271 ccr &= ~(1 << 2);
235 if (sync_mode == OMAP_DMA_SYNC_BLOCK) 272 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
236 OMAP1_DMA_CCR2_REG(lch) |= 1 << 2; 273 ccr |= 1 << 2;
274 dma_write(ccr, CCR2(lch));
237 } 275 }
238 276
239 if (cpu_class_is_omap2() && dma_trigger) { 277 if (cpu_class_is_omap2() && dma_trigger) {
240 u32 val = OMAP_DMA_CCR_REG(lch); 278 u32 val;
241 279
280 val = dma_read(CCR(lch));
242 val &= ~(3 << 19); 281 val &= ~(3 << 19);
243 if (dma_trigger > 63) 282 if (dma_trigger > 63)
244 val |= 1 << 20; 283 val |= 1 << 20;
@@ -263,12 +302,13 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
263 else 302 else
264 val &= ~(1 << 24); /* dest synch */ 303 val &= ~(1 << 24); /* dest synch */
265 304
266 OMAP_DMA_CCR_REG(lch) = val; 305 dma_write(val, CCR(lch));
267 } 306 }
268 307
269 OMAP_DMA_CEN_REG(lch) = elem_count; 308 dma_write(elem_count, CEN(lch));
270 OMAP_DMA_CFN_REG(lch) = frame_count; 309 dma_write(frame_count, CFN(lch));
271} 310}
311EXPORT_SYMBOL(omap_set_dma_transfer_params);
272 312
273void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) 313void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
274{ 314{
@@ -281,7 +321,9 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
281 return; 321 return;
282 } 322 }
283 323
284 w = OMAP1_DMA_CCR2_REG(lch) & ~0x03; 324 w = dma_read(CCR2(lch));
325 w &= ~0x03;
326
285 switch (mode) { 327 switch (mode) {
286 case OMAP_DMA_CONSTANT_FILL: 328 case OMAP_DMA_CONSTANT_FILL:
287 w |= 0x01; 329 w |= 0x01;
@@ -294,52 +336,81 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
294 default: 336 default:
295 BUG(); 337 BUG();
296 } 338 }
297 OMAP1_DMA_CCR2_REG(lch) = w; 339 dma_write(w, CCR2(lch));
298 340
299 w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f; 341 w = dma_read(LCH_CTRL(lch));
342 w &= ~0x0f;
300 /* Default is channel type 2D */ 343 /* Default is channel type 2D */
301 if (mode) { 344 if (mode) {
302 OMAP1_DMA_COLOR_L_REG(lch) = (u16)color; 345 dma_write((u16)color, COLOR_L(lch));
303 OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16); 346 dma_write((u16)(color >> 16), COLOR_U(lch));
304 w |= 1; /* Channel type G */ 347 w |= 1; /* Channel type G */
305 } 348 }
306 OMAP1_DMA_LCH_CTRL_REG(lch) = w; 349 dma_write(w, LCH_CTRL(lch));
307} 350}
351EXPORT_SYMBOL(omap_set_dma_color_mode);
308 352
309void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) 353void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
310{ 354{
311 if (cpu_class_is_omap2()) { 355 if (cpu_class_is_omap2()) {
312 OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16); 356 u32 csdp;
313 OMAP_DMA_CSDP_REG(lch) |= (mode << 16); 357
358 csdp = dma_read(CSDP(lch));
359 csdp &= ~(0x3 << 16);
360 csdp |= (mode << 16);
361 dma_write(csdp, CSDP(lch));
362 }
363}
364EXPORT_SYMBOL(omap_set_dma_write_mode);
365
366void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
367{
368 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
369 u32 l;
370
371 l = dma_read(LCH_CTRL(lch));
372 l &= ~0x7;
373 l |= mode;
374 dma_write(l, LCH_CTRL(lch));
314 } 375 }
315} 376}
377EXPORT_SYMBOL(omap_set_dma_channel_mode);
316 378
317/* Note that src_port is only for omap1 */ 379/* Note that src_port is only for omap1 */
318void omap_set_dma_src_params(int lch, int src_port, int src_amode, 380void omap_set_dma_src_params(int lch, int src_port, int src_amode,
319 unsigned long src_start, 381 unsigned long src_start,
320 int src_ei, int src_fi) 382 int src_ei, int src_fi)
321{ 383{
384 u32 l;
385
322 if (cpu_class_is_omap1()) { 386 if (cpu_class_is_omap1()) {
323 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2); 387 u16 w;
324 OMAP_DMA_CSDP_REG(lch) |= src_port << 2; 388
389 w = dma_read(CSDP(lch));
390 w &= ~(0x1f << 2);
391 w |= src_port << 2;
392 dma_write(w, CSDP(lch));
325 } 393 }
326 394
327 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12); 395 l = dma_read(CCR(lch));
328 OMAP_DMA_CCR_REG(lch) |= src_amode << 12; 396 l &= ~(0x03 << 12);
397 l |= src_amode << 12;
398 dma_write(l, CCR(lch));
329 399
330 if (cpu_class_is_omap1()) { 400 if (cpu_class_is_omap1()) {
331 OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16; 401 dma_write(src_start >> 16, CSSA_U(lch));
332 OMAP1_DMA_CSSA_L_REG(lch) = src_start; 402 dma_write((u16)src_start, CSSA_L(lch));
333 } 403 }
334 404
335 if (cpu_class_is_omap2()) 405 if (cpu_class_is_omap2())
336 OMAP2_DMA_CSSA_REG(lch) = src_start; 406 dma_write(src_start, CSSA(lch));
337 407
338 OMAP_DMA_CSEI_REG(lch) = src_ei; 408 dma_write(src_ei, CSEI(lch));
339 OMAP_DMA_CSFI_REG(lch) = src_fi; 409 dma_write(src_fi, CSFI(lch));
340} 410}
411EXPORT_SYMBOL(omap_set_dma_src_params);
341 412
342void omap_set_dma_params(int lch, struct omap_dma_channel_params * params) 413void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
343{ 414{
344 omap_set_dma_transfer_params(lch, params->data_type, 415 omap_set_dma_transfer_params(lch, params->data_type,
345 params->elem_count, params->frame_count, 416 params->elem_count, params->frame_count,
@@ -356,28 +427,37 @@ void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
356 omap_dma_set_prio_lch(lch, params->read_prio, 427 omap_dma_set_prio_lch(lch, params->read_prio,
357 params->write_prio); 428 params->write_prio);
358} 429}
430EXPORT_SYMBOL(omap_set_dma_params);
359 431
360void omap_set_dma_src_index(int lch, int eidx, int fidx) 432void omap_set_dma_src_index(int lch, int eidx, int fidx)
361{ 433{
362 if (cpu_class_is_omap2()) { 434 if (cpu_class_is_omap2())
363 REVISIT_24XX();
364 return; 435 return;
365 } 436
366 OMAP_DMA_CSEI_REG(lch) = eidx; 437 dma_write(eidx, CSEI(lch));
367 OMAP_DMA_CSFI_REG(lch) = fidx; 438 dma_write(fidx, CSFI(lch));
368} 439}
440EXPORT_SYMBOL(omap_set_dma_src_index);
369 441
370void omap_set_dma_src_data_pack(int lch, int enable) 442void omap_set_dma_src_data_pack(int lch, int enable)
371{ 443{
372 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6); 444 u32 l;
445
446 l = dma_read(CSDP(lch));
447 l &= ~(1 << 6);
373 if (enable) 448 if (enable)
374 OMAP_DMA_CSDP_REG(lch) |= (1 << 6); 449 l |= (1 << 6);
450 dma_write(l, CSDP(lch));
375} 451}
452EXPORT_SYMBOL(omap_set_dma_src_data_pack);
376 453
377void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) 454void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
378{ 455{
379 unsigned int burst = 0; 456 unsigned int burst = 0;
380 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7); 457 u32 l;
458
459 l = dma_read(CSDP(lch));
460 l &= ~(0x03 << 7);
381 461
382 switch (burst_mode) { 462 switch (burst_mode) {
383 case OMAP_DMA_DATA_BURST_DIS: 463 case OMAP_DMA_DATA_BURST_DIS:
@@ -408,55 +488,73 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
408 default: 488 default:
409 BUG(); 489 BUG();
410 } 490 }
411 OMAP_DMA_CSDP_REG(lch) |= (burst << 7); 491
492 l |= (burst << 7);
493 dma_write(l, CSDP(lch));
412} 494}
495EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
413 496
414/* Note that dest_port is only for OMAP1 */ 497/* Note that dest_port is only for OMAP1 */
415void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, 498void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
416 unsigned long dest_start, 499 unsigned long dest_start,
417 int dst_ei, int dst_fi) 500 int dst_ei, int dst_fi)
418{ 501{
502 u32 l;
503
419 if (cpu_class_is_omap1()) { 504 if (cpu_class_is_omap1()) {
420 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9); 505 l = dma_read(CSDP(lch));
421 OMAP_DMA_CSDP_REG(lch) |= dest_port << 9; 506 l &= ~(0x1f << 9);
507 l |= dest_port << 9;
508 dma_write(l, CSDP(lch));
422 } 509 }
423 510
424 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14); 511 l = dma_read(CCR(lch));
425 OMAP_DMA_CCR_REG(lch) |= dest_amode << 14; 512 l &= ~(0x03 << 14);
513 l |= dest_amode << 14;
514 dma_write(l, CCR(lch));
426 515
427 if (cpu_class_is_omap1()) { 516 if (cpu_class_is_omap1()) {
428 OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16; 517 dma_write(dest_start >> 16, CDSA_U(lch));
429 OMAP1_DMA_CDSA_L_REG(lch) = dest_start; 518 dma_write(dest_start, CDSA_L(lch));
430 } 519 }
431 520
432 if (cpu_class_is_omap2()) 521 if (cpu_class_is_omap2())
433 OMAP2_DMA_CDSA_REG(lch) = dest_start; 522 dma_write(dest_start, CDSA(lch));
434 523
435 OMAP_DMA_CDEI_REG(lch) = dst_ei; 524 dma_write(dst_ei, CDEI(lch));
436 OMAP_DMA_CDFI_REG(lch) = dst_fi; 525 dma_write(dst_fi, CDFI(lch));
437} 526}
527EXPORT_SYMBOL(omap_set_dma_dest_params);
438 528
439void omap_set_dma_dest_index(int lch, int eidx, int fidx) 529void omap_set_dma_dest_index(int lch, int eidx, int fidx)
440{ 530{
441 if (cpu_class_is_omap2()) { 531 if (cpu_class_is_omap2())
442 REVISIT_24XX();
443 return; 532 return;
444 } 533
445 OMAP_DMA_CDEI_REG(lch) = eidx; 534 dma_write(eidx, CDEI(lch));
446 OMAP_DMA_CDFI_REG(lch) = fidx; 535 dma_write(fidx, CDFI(lch));
447} 536}
537EXPORT_SYMBOL(omap_set_dma_dest_index);
448 538
449void omap_set_dma_dest_data_pack(int lch, int enable) 539void omap_set_dma_dest_data_pack(int lch, int enable)
450{ 540{
451 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13); 541 u32 l;
542
543 l = dma_read(CSDP(lch));
544 l &= ~(1 << 13);
452 if (enable) 545 if (enable)
453 OMAP_DMA_CSDP_REG(lch) |= 1 << 13; 546 l |= 1 << 13;
547 dma_write(l, CSDP(lch));
454} 548}
549EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
455 550
456void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) 551void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
457{ 552{
458 unsigned int burst = 0; 553 unsigned int burst = 0;
459 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14); 554 u32 l;
555
556 l = dma_read(CSDP(lch));
557 l &= ~(0x03 << 14);
460 558
461 switch (burst_mode) { 559 switch (burst_mode) {
462 case OMAP_DMA_DATA_BURST_DIS: 560 case OMAP_DMA_DATA_BURST_DIS:
@@ -486,8 +584,10 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
486 BUG(); 584 BUG();
487 return; 585 return;
488 } 586 }
489 OMAP_DMA_CSDP_REG(lch) |= (burst << 14); 587 l |= (burst << 14);
588 dma_write(l, CSDP(lch));
490} 589}
590EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
491 591
492static inline void omap_enable_channel_irq(int lch) 592static inline void omap_enable_channel_irq(int lch)
493{ 593{
@@ -495,62 +595,74 @@ static inline void omap_enable_channel_irq(int lch)
495 595
496 /* Clear CSR */ 596 /* Clear CSR */
497 if (cpu_class_is_omap1()) 597 if (cpu_class_is_omap1())
498 status = OMAP_DMA_CSR_REG(lch); 598 status = dma_read(CSR(lch));
499 else if (cpu_class_is_omap2()) 599 else if (cpu_class_is_omap2())
500 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK; 600 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
501 601
502 /* Enable some nice interrupts. */ 602 /* Enable some nice interrupts. */
503 OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs; 603 dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
504} 604}
505 605
506static void omap_disable_channel_irq(int lch) 606static void omap_disable_channel_irq(int lch)
507{ 607{
508 if (cpu_class_is_omap2()) 608 if (cpu_class_is_omap2())
509 OMAP_DMA_CICR_REG(lch) = 0; 609 dma_write(0, CICR(lch));
510} 610}
511 611
512void omap_enable_dma_irq(int lch, u16 bits) 612void omap_enable_dma_irq(int lch, u16 bits)
513{ 613{
514 dma_chan[lch].enabled_irqs |= bits; 614 dma_chan[lch].enabled_irqs |= bits;
515} 615}
616EXPORT_SYMBOL(omap_enable_dma_irq);
516 617
517void omap_disable_dma_irq(int lch, u16 bits) 618void omap_disable_dma_irq(int lch, u16 bits)
518{ 619{
519 dma_chan[lch].enabled_irqs &= ~bits; 620 dma_chan[lch].enabled_irqs &= ~bits;
520} 621}
622EXPORT_SYMBOL(omap_disable_dma_irq);
521 623
522static inline void enable_lnk(int lch) 624static inline void enable_lnk(int lch)
523{ 625{
626 u32 l;
627
628 l = dma_read(CLNK_CTRL(lch));
629
524 if (cpu_class_is_omap1()) 630 if (cpu_class_is_omap1())
525 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14); 631 l &= ~(1 << 14);
526 632
527 /* Set the ENABLE_LNK bits */ 633 /* Set the ENABLE_LNK bits */
528 if (dma_chan[lch].next_lch != -1) 634 if (dma_chan[lch].next_lch != -1)
529 OMAP_DMA_CLNK_CTRL_REG(lch) = 635 l = dma_chan[lch].next_lch | (1 << 15);
530 dma_chan[lch].next_lch | (1 << 15);
531 636
532#ifndef CONFIG_ARCH_OMAP1 637#ifndef CONFIG_ARCH_OMAP1
533 if (dma_chan[lch].next_linked_ch != -1) 638 if (cpu_class_is_omap2())
534 OMAP_DMA_CLNK_CTRL_REG(lch) = 639 if (dma_chan[lch].next_linked_ch != -1)
535 dma_chan[lch].next_linked_ch | (1 << 15); 640 l = dma_chan[lch].next_linked_ch | (1 << 15);
536#endif 641#endif
642
643 dma_write(l, CLNK_CTRL(lch));
537} 644}
538 645
539static inline void disable_lnk(int lch) 646static inline void disable_lnk(int lch)
540{ 647{
648 u32 l;
649
650 l = dma_read(CLNK_CTRL(lch));
651
541 /* Disable interrupts */ 652 /* Disable interrupts */
542 if (cpu_class_is_omap1()) { 653 if (cpu_class_is_omap1()) {
543 OMAP_DMA_CICR_REG(lch) = 0; 654 dma_write(0, CICR(lch));
544 /* Set the STOP_LNK bit */ 655 /* Set the STOP_LNK bit */
545 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14; 656 l |= 1 << 14;
546 } 657 }
547 658
548 if (cpu_class_is_omap2()) { 659 if (cpu_class_is_omap2()) {
549 omap_disable_channel_irq(lch); 660 omap_disable_channel_irq(lch);
550 /* Clear the ENABLE_LNK bit */ 661 /* Clear the ENABLE_LNK bit */
551 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15); 662 l &= ~(1 << 15);
552 } 663 }
553 664
665 dma_write(l, CLNK_CTRL(lch));
554 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; 666 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
555} 667}
556 668
@@ -561,13 +673,13 @@ static inline void omap2_enable_irq_lch(int lch)
561 if (!cpu_class_is_omap2()) 673 if (!cpu_class_is_omap2())
562 return; 674 return;
563 675
564 val = omap_readl(OMAP_DMA4_IRQENABLE_L0); 676 val = dma_read(IRQENABLE_L0);
565 val |= 1 << lch; 677 val |= 1 << lch;
566 omap_writel(val, OMAP_DMA4_IRQENABLE_L0); 678 dma_write(val, IRQENABLE_L0);
567} 679}
568 680
569int omap_request_dma(int dev_id, const char *dev_name, 681int omap_request_dma(int dev_id, const char *dev_name,
570 void (* callback)(int lch, u16 ch_status, void *data), 682 void (*callback)(int lch, u16 ch_status, void *data),
571 void *data, int *dma_ch_out) 683 void *data, int *dma_ch_out)
572{ 684{
573 int ch, free_ch = -1; 685 int ch, free_ch = -1;
@@ -600,10 +712,14 @@ int omap_request_dma(int dev_id, const char *dev_name,
600 chan->dev_name = dev_name; 712 chan->dev_name = dev_name;
601 chan->callback = callback; 713 chan->callback = callback;
602 chan->data = data; 714 chan->data = data;
715
603#ifndef CONFIG_ARCH_OMAP1 716#ifndef CONFIG_ARCH_OMAP1
604 chan->chain_id = -1; 717 if (cpu_class_is_omap2()) {
605 chan->next_linked_ch = -1; 718 chan->chain_id = -1;
719 chan->next_linked_ch = -1;
720 }
606#endif 721#endif
722
607 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; 723 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
608 724
609 if (cpu_class_is_omap1()) 725 if (cpu_class_is_omap1())
@@ -618,26 +734,28 @@ int omap_request_dma(int dev_id, const char *dev_name,
618 set_gdma_dev(free_ch + 1, dev_id); 734 set_gdma_dev(free_ch + 1, dev_id);
619 dev_id = free_ch + 1; 735 dev_id = free_ch + 1;
620 } 736 }
621 /* Disable the 1510 compatibility mode and set the sync device 737 /*
622 * id. */ 738 * Disable the 1510 compatibility mode and set the sync device
623 OMAP_DMA_CCR_REG(free_ch) = dev_id | (1 << 10); 739 * id.
740 */
741 dma_write(dev_id | (1 << 10), CCR(free_ch));
624 } else if (cpu_is_omap730() || cpu_is_omap15xx()) { 742 } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
625 OMAP_DMA_CCR_REG(free_ch) = dev_id; 743 dma_write(dev_id, CCR(free_ch));
626 } 744 }
627 745
628 if (cpu_class_is_omap2()) { 746 if (cpu_class_is_omap2()) {
629 omap2_enable_irq_lch(free_ch); 747 omap2_enable_irq_lch(free_ch);
630
631 omap_enable_channel_irq(free_ch); 748 omap_enable_channel_irq(free_ch);
632 /* Clear the CSR register and IRQ status register */ 749 /* Clear the CSR register and IRQ status register */
633 OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK; 750 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
634 omap_writel(1 << free_ch, OMAP_DMA4_IRQSTATUS_L0); 751 dma_write(1 << free_ch, IRQSTATUS_L0);
635 } 752 }
636 753
637 *dma_ch_out = free_ch; 754 *dma_ch_out = free_ch;
638 755
639 return 0; 756 return 0;
640} 757}
758EXPORT_SYMBOL(omap_request_dma);
641 759
642void omap_free_dma(int lch) 760void omap_free_dma(int lch)
643{ 761{
@@ -645,11 +763,12 @@ void omap_free_dma(int lch)
645 763
646 spin_lock_irqsave(&dma_chan_lock, flags); 764 spin_lock_irqsave(&dma_chan_lock, flags);
647 if (dma_chan[lch].dev_id == -1) { 765 if (dma_chan[lch].dev_id == -1) {
648 printk("omap_dma: trying to free nonallocated DMA channel %d\n", 766 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
649 lch); 767 lch);
650 spin_unlock_irqrestore(&dma_chan_lock, flags); 768 spin_unlock_irqrestore(&dma_chan_lock, flags);
651 return; 769 return;
652 } 770 }
771
653 dma_chan[lch].dev_id = -1; 772 dma_chan[lch].dev_id = -1;
654 dma_chan[lch].next_lch = -1; 773 dma_chan[lch].next_lch = -1;
655 dma_chan[lch].callback = NULL; 774 dma_chan[lch].callback = NULL;
@@ -657,30 +776,31 @@ void omap_free_dma(int lch)
657 776
658 if (cpu_class_is_omap1()) { 777 if (cpu_class_is_omap1()) {
659 /* Disable all DMA interrupts for the channel. */ 778 /* Disable all DMA interrupts for the channel. */
660 OMAP_DMA_CICR_REG(lch) = 0; 779 dma_write(0, CICR(lch));
661 /* Make sure the DMA transfer is stopped. */ 780 /* Make sure the DMA transfer is stopped. */
662 OMAP_DMA_CCR_REG(lch) = 0; 781 dma_write(0, CCR(lch));
663 } 782 }
664 783
665 if (cpu_class_is_omap2()) { 784 if (cpu_class_is_omap2()) {
666 u32 val; 785 u32 val;
667 /* Disable interrupts */ 786 /* Disable interrupts */
668 val = omap_readl(OMAP_DMA4_IRQENABLE_L0); 787 val = dma_read(IRQENABLE_L0);
669 val &= ~(1 << lch); 788 val &= ~(1 << lch);
670 omap_writel(val, OMAP_DMA4_IRQENABLE_L0); 789 dma_write(val, IRQENABLE_L0);
671 790
672 /* Clear the CSR register and IRQ status register */ 791 /* Clear the CSR register and IRQ status register */
673 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK; 792 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
674 omap_writel(1 << lch, OMAP_DMA4_IRQSTATUS_L0); 793 dma_write(1 << lch, IRQSTATUS_L0);
675 794
676 /* Disable all DMA interrupts for the channel. */ 795 /* Disable all DMA interrupts for the channel. */
677 OMAP_DMA_CICR_REG(lch) = 0; 796 dma_write(0, CICR(lch));
678 797
679 /* Make sure the DMA transfer is stopped. */ 798 /* Make sure the DMA transfer is stopped. */
680 OMAP_DMA_CCR_REG(lch) = 0; 799 dma_write(0, CCR(lch));
681 omap_clear_dma(lch); 800 omap_clear_dma(lch);
682 } 801 }
683} 802}
803EXPORT_SYMBOL(omap_free_dma);
684 804
685/** 805/**
686 * @brief omap_dma_set_global_params : Set global priority settings for dma 806 * @brief omap_dma_set_global_params : Set global priority settings for dma
@@ -708,7 +828,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
708 reg = (arb_rate & 0xff) << 16; 828 reg = (arb_rate & 0xff) << 16;
709 reg |= (0xff & max_fifo_depth); 829 reg |= (0xff & max_fifo_depth);
710 830
711 omap_writel(reg, OMAP_DMA4_GCR_REG); 831 dma_write(reg, GCR);
712} 832}
713EXPORT_SYMBOL(omap_dma_set_global_params); 833EXPORT_SYMBOL(omap_dma_set_global_params);
714 834
@@ -725,20 +845,21 @@ int
725omap_dma_set_prio_lch(int lch, unsigned char read_prio, 845omap_dma_set_prio_lch(int lch, unsigned char read_prio,
726 unsigned char write_prio) 846 unsigned char write_prio)
727{ 847{
728 u32 w; 848 u32 l;
729 849
730 if (unlikely((lch < 0 || lch >= OMAP_LOGICAL_DMA_CH_COUNT))) { 850 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
731 printk(KERN_ERR "Invalid channel id\n"); 851 printk(KERN_ERR "Invalid channel id\n");
732 return -EINVAL; 852 return -EINVAL;
733 } 853 }
734 w = OMAP_DMA_CCR_REG(lch); 854 l = dma_read(CCR(lch));
735 w &= ~((1 << 6) | (1 << 26)); 855 l &= ~((1 << 6) | (1 << 26));
736 if (cpu_is_omap2430() || cpu_is_omap34xx()) 856 if (cpu_is_omap2430() || cpu_is_omap34xx())
737 w |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); 857 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
738 else 858 else
739 w |= ((read_prio & 0x1) << 6); 859 l |= ((read_prio & 0x1) << 6);
860
861 dma_write(l, CCR(lch));
740 862
741 OMAP_DMA_CCR_REG(lch) = w;
742 return 0; 863 return 0;
743} 864}
744EXPORT_SYMBOL(omap_dma_set_prio_lch); 865EXPORT_SYMBOL(omap_dma_set_prio_lch);
@@ -754,28 +875,34 @@ void omap_clear_dma(int lch)
754 local_irq_save(flags); 875 local_irq_save(flags);
755 876
756 if (cpu_class_is_omap1()) { 877 if (cpu_class_is_omap1()) {
757 int status; 878 u32 l;
758 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN; 879
880 l = dma_read(CCR(lch));
881 l &= ~OMAP_DMA_CCR_EN;
882 dma_write(l, CCR(lch));
759 883
760 /* Clear pending interrupts */ 884 /* Clear pending interrupts */
761 status = OMAP_DMA_CSR_REG(lch); 885 l = dma_read(CSR(lch));
762 } 886 }
763 887
764 if (cpu_class_is_omap2()) { 888 if (cpu_class_is_omap2()) {
765 int i; 889 int i;
766 u32 lch_base = OMAP_DMA4_BASE + lch * 0x60 + 0x80; 890 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
767 for (i = 0; i < 0x44; i += 4) 891 for (i = 0; i < 0x44; i += 4)
768 omap_writel(0, lch_base + i); 892 __raw_writel(0, lch_base + i);
769 } 893 }
770 894
771 local_irq_restore(flags); 895 local_irq_restore(flags);
772} 896}
897EXPORT_SYMBOL(omap_clear_dma);
773 898
774void omap_start_dma(int lch) 899void omap_start_dma(int lch)
775{ 900{
901 u32 l;
902
776 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { 903 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
777 int next_lch, cur_lch; 904 int next_lch, cur_lch;
778 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT]; 905 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
779 906
780 dma_chan_link_map[lch] = 1; 907 dma_chan_link_map[lch] = 1;
781 /* Set the link register of the first channel */ 908 /* Set the link register of the first channel */
@@ -799,27 +926,34 @@ void omap_start_dma(int lch)
799 } while (next_lch != -1); 926 } while (next_lch != -1);
800 } else if (cpu_class_is_omap2()) { 927 } else if (cpu_class_is_omap2()) {
801 /* Errata: Need to write lch even if not using chaining */ 928 /* Errata: Need to write lch even if not using chaining */
802 OMAP_DMA_CLNK_CTRL_REG(lch) = lch; 929 dma_write(lch, CLNK_CTRL(lch));
803 } 930 }
804 931
805 omap_enable_channel_irq(lch); 932 omap_enable_channel_irq(lch);
806 933
807 /* Errata: On ES2.0 BUFFERING disable must be set. 934 l = dma_read(CCR(lch));
808 * This will always fail on ES1.0 */ 935
809 if (cpu_is_omap24xx()) { 936 /*
810 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN; 937 * Errata: On ES2.0 BUFFERING disable must be set.
811 } 938 * This will always fail on ES1.0
939 */
940 if (cpu_is_omap24xx())
941 l |= OMAP_DMA_CCR_EN;
812 942
813 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN; 943 l |= OMAP_DMA_CCR_EN;
944 dma_write(l, CCR(lch));
814 945
815 dma_chan[lch].flags |= OMAP_DMA_ACTIVE; 946 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
816} 947}
948EXPORT_SYMBOL(omap_start_dma);
817 949
818void omap_stop_dma(int lch) 950void omap_stop_dma(int lch)
819{ 951{
952 u32 l;
953
820 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { 954 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
821 int next_lch, cur_lch = lch; 955 int next_lch, cur_lch = lch;
822 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT]; 956 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
823 957
824 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); 958 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
825 do { 959 do {
@@ -840,18 +974,22 @@ void omap_stop_dma(int lch)
840 974
841 /* Disable all interrupts on the channel */ 975 /* Disable all interrupts on the channel */
842 if (cpu_class_is_omap1()) 976 if (cpu_class_is_omap1())
843 OMAP_DMA_CICR_REG(lch) = 0; 977 dma_write(0, CICR(lch));
978
979 l = dma_read(CCR(lch));
980 l &= ~OMAP_DMA_CCR_EN;
981 dma_write(l, CCR(lch));
844 982
845 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
846 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; 983 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
847} 984}
985EXPORT_SYMBOL(omap_stop_dma);
848 986
849/* 987/*
850 * Allows changing the DMA callback function or data. This may be needed if 988 * Allows changing the DMA callback function or data. This may be needed if
851 * the driver shares a single DMA channel for multiple dma triggers. 989 * the driver shares a single DMA channel for multiple dma triggers.
852 */ 990 */
853int omap_set_dma_callback(int lch, 991int omap_set_dma_callback(int lch,
854 void (* callback)(int lch, u16 ch_status, void *data), 992 void (*callback)(int lch, u16 ch_status, void *data),
855 void *data) 993 void *data)
856{ 994{
857 unsigned long flags; 995 unsigned long flags;
@@ -871,6 +1009,7 @@ int omap_set_dma_callback(int lch,
871 1009
872 return 0; 1010 return 0;
873} 1011}
1012EXPORT_SYMBOL(omap_set_dma_callback);
874 1013
875/* 1014/*
876 * Returns current physical source address for the given DMA channel. 1015 * Returns current physical source address for the given DMA channel.
@@ -884,15 +1023,24 @@ dma_addr_t omap_get_dma_src_pos(int lch)
884{ 1023{
885 dma_addr_t offset = 0; 1024 dma_addr_t offset = 0;
886 1025
887 if (cpu_class_is_omap1()) 1026 if (cpu_is_omap15xx())
888 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) | 1027 offset = dma_read(CPC(lch));
889 (OMAP1_DMA_CSSA_U_REG(lch) << 16)); 1028 else
1029 offset = dma_read(CSAC(lch));
890 1030
891 if (cpu_class_is_omap2()) 1031 /*
892 offset = OMAP_DMA_CSAC_REG(lch); 1032 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1033 * read before the DMA controller finished disabling the channel.
1034 */
1035 if (!cpu_is_omap15xx() && offset == 0)
1036 offset = dma_read(CSAC(lch));
1037
1038 if (cpu_class_is_omap1())
1039 offset |= (dma_read(CSSA_U(lch)) << 16);
893 1040
894 return offset; 1041 return offset;
895} 1042}
1043EXPORT_SYMBOL(omap_get_dma_src_pos);
896 1044
897/* 1045/*
898 * Returns current physical destination address for the given DMA channel. 1046 * Returns current physical destination address for the given DMA channel.
@@ -906,25 +1054,30 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
906{ 1054{
907 dma_addr_t offset = 0; 1055 dma_addr_t offset = 0;
908 1056
909 if (cpu_class_is_omap1()) 1057 if (cpu_is_omap15xx())
910 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) | 1058 offset = dma_read(CPC(lch));
911 (OMAP1_DMA_CDSA_U_REG(lch) << 16)); 1059 else
1060 offset = dma_read(CDAC(lch));
912 1061
913 if (cpu_class_is_omap2()) 1062 /*
914 offset = OMAP_DMA_CDAC_REG(lch); 1063 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1064 * read before the DMA controller finished disabling the channel.
1065 */
1066 if (!cpu_is_omap15xx() && offset == 0)
1067 offset = dma_read(CDAC(lch));
1068
1069 if (cpu_class_is_omap1())
1070 offset |= (dma_read(CDSA_U(lch)) << 16);
915 1071
916 return offset; 1072 return offset;
917} 1073}
1074EXPORT_SYMBOL(omap_get_dma_dst_pos);
918 1075
919/* 1076int omap_get_dma_active_status(int lch)
920 * Returns current source transfer counting for the given DMA channel.
921 * Can be used to monitor the progress of a transfer inside a block.
922 * It must be called with disabled interrupts.
923 */
924int omap_get_dma_src_addr_counter(int lch)
925{ 1077{
926 return (dma_addr_t) OMAP_DMA_CSAC_REG(lch); 1078 return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
927} 1079}
1080EXPORT_SYMBOL(omap_get_dma_active_status);
928 1081
929int omap_dma_running(void) 1082int omap_dma_running(void)
930{ 1083{
@@ -936,7 +1089,7 @@ int omap_dma_running(void)
936 return 1; 1089 return 1;
937 1090
938 for (lch = 0; lch < dma_chan_count; lch++) 1091 for (lch = 0; lch < dma_chan_count; lch++)
939 if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN) 1092 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
940 return 1; 1093 return 1;
941 1094
942 return 0; 1095 return 0;
@@ -947,7 +1100,7 @@ int omap_dma_running(void)
947 * For this DMA link to start, you still need to start (see omap_start_dma) 1100 * For this DMA link to start, you still need to start (see omap_start_dma)
948 * the first one. That will fire up the entire queue. 1101 * the first one. That will fire up the entire queue.
949 */ 1102 */
950void omap_dma_link_lch (int lch_head, int lch_queue) 1103void omap_dma_link_lch(int lch_head, int lch_queue)
951{ 1104{
952 if (omap_dma_in_1510_mode()) { 1105 if (omap_dma_in_1510_mode()) {
953 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); 1106 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
@@ -964,11 +1117,12 @@ void omap_dma_link_lch (int lch_head, int lch_queue)
964 1117
965 dma_chan[lch_head].next_lch = lch_queue; 1118 dma_chan[lch_head].next_lch = lch_queue;
966} 1119}
1120EXPORT_SYMBOL(omap_dma_link_lch);
967 1121
968/* 1122/*
969 * Once the DMA queue is stopped, we can destroy it. 1123 * Once the DMA queue is stopped, we can destroy it.
970 */ 1124 */
971void omap_dma_unlink_lch (int lch_head, int lch_queue) 1125void omap_dma_unlink_lch(int lch_head, int lch_queue)
972{ 1126{
973 if (omap_dma_in_1510_mode()) { 1127 if (omap_dma_in_1510_mode()) {
974 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); 1128 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
@@ -983,7 +1137,6 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue)
983 dump_stack(); 1137 dump_stack();
984 } 1138 }
985 1139
986
987 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) || 1140 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
988 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) { 1141 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
989 printk(KERN_ERR "omap_dma: You need to stop the DMA channels " 1142 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
@@ -993,12 +1146,15 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue)
993 1146
994 dma_chan[lch_head].next_lch = -1; 1147 dma_chan[lch_head].next_lch = -1;
995} 1148}
1149EXPORT_SYMBOL(omap_dma_unlink_lch);
1150
1151/*----------------------------------------------------------------------------*/
996 1152
997#ifndef CONFIG_ARCH_OMAP1 1153#ifndef CONFIG_ARCH_OMAP1
998/* Create chain of DMA channesls */ 1154/* Create chain of DMA channesls */
999static void create_dma_lch_chain(int lch_head, int lch_queue) 1155static void create_dma_lch_chain(int lch_head, int lch_queue)
1000{ 1156{
1001 u32 w; 1157 u32 l;
1002 1158
1003 /* Check if this is the first link in chain */ 1159 /* Check if this is the first link in chain */
1004 if (dma_chan[lch_head].next_linked_ch == -1) { 1160 if (dma_chan[lch_head].next_linked_ch == -1) {
@@ -1018,15 +1174,15 @@ static void create_dma_lch_chain(int lch_head, int lch_queue)
1018 lch_queue; 1174 lch_queue;
1019 } 1175 }
1020 1176
1021 w = OMAP_DMA_CLNK_CTRL_REG(lch_head); 1177 l = dma_read(CLNK_CTRL(lch_head));
1022 w &= ~(0x1f); 1178 l &= ~(0x1f);
1023 w |= lch_queue; 1179 l |= lch_queue;
1024 OMAP_DMA_CLNK_CTRL_REG(lch_head) = w; 1180 dma_write(l, CLNK_CTRL(lch_head));
1025 1181
1026 w = OMAP_DMA_CLNK_CTRL_REG(lch_queue); 1182 l = dma_read(CLNK_CTRL(lch_queue));
1027 w &= ~(0x1f); 1183 l &= ~(0x1f);
1028 w |= (dma_chan[lch_queue].next_linked_ch); 1184 l |= (dma_chan[lch_queue].next_linked_ch);
1029 OMAP_DMA_CLNK_CTRL_REG(lch_queue) = w; 1185 dma_write(l, CLNK_CTRL(lch_queue));
1030} 1186}
1031 1187
1032/** 1188/**
@@ -1061,7 +1217,7 @@ int omap_request_dma_chain(int dev_id, const char *dev_name,
1061 } 1217 }
1062 1218
1063 if (unlikely((no_of_chans < 1 1219 if (unlikely((no_of_chans < 1
1064 || no_of_chans > OMAP_LOGICAL_DMA_CH_COUNT))) { 1220 || no_of_chans > dma_lch_count))) {
1065 printk(KERN_ERR "Invalid Number of channels requested\n"); 1221 printk(KERN_ERR "Invalid Number of channels requested\n");
1066 return -EINVAL; 1222 return -EINVAL;
1067 } 1223 }
@@ -1116,6 +1272,7 @@ int omap_request_dma_chain(int dev_id, const char *dev_name,
1116 for (i = 0; i < (no_of_chans - 1); i++) 1272 for (i = 0; i < (no_of_chans - 1); i++)
1117 create_dma_lch_chain(channels[i], channels[i + 1]); 1273 create_dma_lch_chain(channels[i], channels[i + 1]);
1118 } 1274 }
1275
1119 return 0; 1276 return 0;
1120} 1277}
1121EXPORT_SYMBOL(omap_request_dma_chain); 1278EXPORT_SYMBOL(omap_request_dma_chain);
@@ -1138,7 +1295,7 @@ int omap_modify_dma_chain_params(int chain_id,
1138 1295
1139 /* Check for input params */ 1296 /* Check for input params */
1140 if (unlikely((chain_id < 0 1297 if (unlikely((chain_id < 0
1141 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1298 || chain_id >= dma_lch_count))) {
1142 printk(KERN_ERR "Invalid chain id\n"); 1299 printk(KERN_ERR "Invalid chain id\n");
1143 return -EINVAL; 1300 return -EINVAL;
1144 } 1301 }
@@ -1158,6 +1315,7 @@ int omap_modify_dma_chain_params(int chain_id,
1158 */ 1315 */
1159 omap_set_dma_params(channels[i], &params); 1316 omap_set_dma_params(channels[i], &params);
1160 } 1317 }
1318
1161 return 0; 1319 return 0;
1162} 1320}
1163EXPORT_SYMBOL(omap_modify_dma_chain_params); 1321EXPORT_SYMBOL(omap_modify_dma_chain_params);
@@ -1176,7 +1334,7 @@ int omap_free_dma_chain(int chain_id)
1176 u32 i; 1334 u32 i;
1177 1335
1178 /* Check for input params */ 1336 /* Check for input params */
1179 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1337 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1180 printk(KERN_ERR "Invalid chain id\n"); 1338 printk(KERN_ERR "Invalid chain id\n");
1181 return -EINVAL; 1339 return -EINVAL;
1182 } 1340 }
@@ -1201,6 +1359,7 @@ int omap_free_dma_chain(int chain_id)
1201 dma_linked_lch[chain_id].linked_dmach_q = NULL; 1359 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1202 dma_linked_lch[chain_id].chain_mode = -1; 1360 dma_linked_lch[chain_id].chain_mode = -1;
1203 dma_linked_lch[chain_id].chain_state = -1; 1361 dma_linked_lch[chain_id].chain_state = -1;
1362
1204 return (0); 1363 return (0);
1205} 1364}
1206EXPORT_SYMBOL(omap_free_dma_chain); 1365EXPORT_SYMBOL(omap_free_dma_chain);
@@ -1216,7 +1375,7 @@ EXPORT_SYMBOL(omap_free_dma_chain);
1216int omap_dma_chain_status(int chain_id) 1375int omap_dma_chain_status(int chain_id)
1217{ 1376{
1218 /* Check for input params */ 1377 /* Check for input params */
1219 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1378 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1220 printk(KERN_ERR "Invalid chain id\n"); 1379 printk(KERN_ERR "Invalid chain id\n");
1221 return -EINVAL; 1380 return -EINVAL;
1222 } 1381 }
@@ -1231,6 +1390,7 @@ int omap_dma_chain_status(int chain_id)
1231 1390
1232 if (OMAP_DMA_CHAIN_QEMPTY(chain_id)) 1391 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1233 return OMAP_DMA_CHAIN_INACTIVE; 1392 return OMAP_DMA_CHAIN_INACTIVE;
1393
1234 return OMAP_DMA_CHAIN_ACTIVE; 1394 return OMAP_DMA_CHAIN_ACTIVE;
1235} 1395}
1236EXPORT_SYMBOL(omap_dma_chain_status); 1396EXPORT_SYMBOL(omap_dma_chain_status);
@@ -1253,11 +1413,13 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1253 int elem_count, int frame_count, void *callbk_data) 1413 int elem_count, int frame_count, void *callbk_data)
1254{ 1414{
1255 int *channels; 1415 int *channels;
1256 u32 w, lch; 1416 u32 l, lch;
1257 int start_dma = 0; 1417 int start_dma = 0;
1258 1418
1259 /* if buffer size is less than 1 then there is 1419 /*
1260 * no use of starting the chain */ 1420 * if buffer size is less than 1 then there is
1421 * no use of starting the chain
1422 */
1261 if (elem_count < 1) { 1423 if (elem_count < 1) {
1262 printk(KERN_ERR "Invalid buffer size\n"); 1424 printk(KERN_ERR "Invalid buffer size\n");
1263 return -EINVAL; 1425 return -EINVAL;
@@ -1265,7 +1427,7 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1265 1427
1266 /* Check for input params */ 1428 /* Check for input params */
1267 if (unlikely((chain_id < 0 1429 if (unlikely((chain_id < 0
1268 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1430 || chain_id >= dma_lch_count))) {
1269 printk(KERN_ERR "Invalid chain id\n"); 1431 printk(KERN_ERR "Invalid chain id\n");
1270 return -EINVAL; 1432 return -EINVAL;
1271 } 1433 }
@@ -1294,20 +1456,24 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1294 1456
1295 /* Set the params to the free channel */ 1457 /* Set the params to the free channel */
1296 if (src_start != 0) 1458 if (src_start != 0)
1297 OMAP2_DMA_CSSA_REG(lch) = src_start; 1459 dma_write(src_start, CSSA(lch));
1298 if (dest_start != 0) 1460 if (dest_start != 0)
1299 OMAP2_DMA_CDSA_REG(lch) = dest_start; 1461 dma_write(dest_start, CDSA(lch));
1300 1462
1301 /* Write the buffer size */ 1463 /* Write the buffer size */
1302 OMAP_DMA_CEN_REG(lch) = elem_count; 1464 dma_write(elem_count, CEN(lch));
1303 OMAP_DMA_CFN_REG(lch) = frame_count; 1465 dma_write(frame_count, CFN(lch));
1304 1466
1305 /* If the chain is dynamically linked, 1467 /*
1306 * then we may have to start the chain if its not active */ 1468 * If the chain is dynamically linked,
1469 * then we may have to start the chain if its not active
1470 */
1307 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) { 1471 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1308 1472
1309 /* In Dynamic chain, if the chain is not started, 1473 /*
1310 * queue the channel */ 1474 * In Dynamic chain, if the chain is not started,
1475 * queue the channel
1476 */
1311 if (dma_linked_lch[chain_id].chain_state == 1477 if (dma_linked_lch[chain_id].chain_state ==
1312 DMA_CHAIN_NOTSTARTED) { 1478 DMA_CHAIN_NOTSTARTED) {
1313 /* Enable the link in previous channel */ 1479 /* Enable the link in previous channel */
@@ -1317,8 +1483,10 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1317 dma_chan[lch].state = DMA_CH_QUEUED; 1483 dma_chan[lch].state = DMA_CH_QUEUED;
1318 } 1484 }
1319 1485
1320 /* Chain is already started, make sure its active, 1486 /*
1321 * if not then start the chain */ 1487 * Chain is already started, make sure its active,
1488 * if not then start the chain
1489 */
1322 else { 1490 else {
1323 start_dma = 1; 1491 start_dma = 1;
1324 1492
@@ -1327,8 +1495,8 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1327 enable_lnk(dma_chan[lch].prev_linked_ch); 1495 enable_lnk(dma_chan[lch].prev_linked_ch);
1328 dma_chan[lch].state = DMA_CH_QUEUED; 1496 dma_chan[lch].state = DMA_CH_QUEUED;
1329 start_dma = 0; 1497 start_dma = 0;
1330 if (0 == ((1 << 7) & (OMAP_DMA_CCR_REG 1498 if (0 == ((1 << 7) & dma_read(
1331 (dma_chan[lch].prev_linked_ch)))) { 1499 CCR(dma_chan[lch].prev_linked_ch)))) {
1332 disable_lnk(dma_chan[lch]. 1500 disable_lnk(dma_chan[lch].
1333 prev_linked_ch); 1501 prev_linked_ch);
1334 pr_debug("\n prev ch is stopped\n"); 1502 pr_debug("\n prev ch is stopped\n");
@@ -1344,27 +1512,28 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1344 } 1512 }
1345 omap_enable_channel_irq(lch); 1513 omap_enable_channel_irq(lch);
1346 1514
1347 w = OMAP_DMA_CCR_REG(lch); 1515 l = dma_read(CCR(lch));
1348 1516
1349 if ((0 == (w & (1 << 24)))) 1517 if ((0 == (l & (1 << 24))))
1350 w &= ~(1 << 25); 1518 l &= ~(1 << 25);
1351 else 1519 else
1352 w |= (1 << 25); 1520 l |= (1 << 25);
1353 if (start_dma == 1) { 1521 if (start_dma == 1) {
1354 if (0 == (w & (1 << 7))) { 1522 if (0 == (l & (1 << 7))) {
1355 w |= (1 << 7); 1523 l |= (1 << 7);
1356 dma_chan[lch].state = DMA_CH_STARTED; 1524 dma_chan[lch].state = DMA_CH_STARTED;
1357 pr_debug("starting %d\n", lch); 1525 pr_debug("starting %d\n", lch);
1358 OMAP_DMA_CCR_REG(lch) = w; 1526 dma_write(l, CCR(lch));
1359 } else 1527 } else
1360 start_dma = 0; 1528 start_dma = 0;
1361 } else { 1529 } else {
1362 if (0 == (w & (1 << 7))) 1530 if (0 == (l & (1 << 7)))
1363 OMAP_DMA_CCR_REG(lch) = w; 1531 dma_write(l, CCR(lch));
1364 } 1532 }
1365 dma_chan[lch].flags |= OMAP_DMA_ACTIVE; 1533 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1366 } 1534 }
1367 } 1535 }
1536
1368 return 0; 1537 return 0;
1369} 1538}
1370EXPORT_SYMBOL(omap_dma_chain_a_transfer); 1539EXPORT_SYMBOL(omap_dma_chain_a_transfer);
@@ -1380,9 +1549,9 @@ EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1380int omap_start_dma_chain_transfers(int chain_id) 1549int omap_start_dma_chain_transfers(int chain_id)
1381{ 1550{
1382 int *channels; 1551 int *channels;
1383 u32 w, i; 1552 u32 l, i;
1384 1553
1385 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1554 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1386 printk(KERN_ERR "Invalid chain id\n"); 1555 printk(KERN_ERR "Invalid chain id\n");
1387 return -EINVAL; 1556 return -EINVAL;
1388 } 1557 }
@@ -1404,18 +1573,19 @@ int omap_start_dma_chain_transfers(int chain_id)
1404 omap_enable_channel_irq(channels[0]); 1573 omap_enable_channel_irq(channels[0]);
1405 } 1574 }
1406 1575
1407 w = OMAP_DMA_CCR_REG(channels[0]); 1576 l = dma_read(CCR(channels[0]));
1408 w |= (1 << 7); 1577 l |= (1 << 7);
1409 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED; 1578 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1410 dma_chan[channels[0]].state = DMA_CH_STARTED; 1579 dma_chan[channels[0]].state = DMA_CH_STARTED;
1411 1580
1412 if ((0 == (w & (1 << 24)))) 1581 if ((0 == (l & (1 << 24))))
1413 w &= ~(1 << 25); 1582 l &= ~(1 << 25);
1414 else 1583 else
1415 w |= (1 << 25); 1584 l |= (1 << 25);
1416 OMAP_DMA_CCR_REG(channels[0]) = w; 1585 dma_write(l, CCR(channels[0]));
1417 1586
1418 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE; 1587 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1588
1419 return 0; 1589 return 0;
1420} 1590}
1421EXPORT_SYMBOL(omap_start_dma_chain_transfers); 1591EXPORT_SYMBOL(omap_start_dma_chain_transfers);
@@ -1431,11 +1601,11 @@ EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1431int omap_stop_dma_chain_transfers(int chain_id) 1601int omap_stop_dma_chain_transfers(int chain_id)
1432{ 1602{
1433 int *channels; 1603 int *channels;
1434 u32 w, i; 1604 u32 l, i;
1435 u32 sys_cf; 1605 u32 sys_cf;
1436 1606
1437 /* Check for input params */ 1607 /* Check for input params */
1438 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1608 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1439 printk(KERN_ERR "Invalid chain id\n"); 1609 printk(KERN_ERR "Invalid chain id\n");
1440 return -EINVAL; 1610 return -EINVAL;
1441 } 1611 }
@@ -1447,21 +1617,22 @@ int omap_stop_dma_chain_transfers(int chain_id)
1447 } 1617 }
1448 channels = dma_linked_lch[chain_id].linked_dmach_q; 1618 channels = dma_linked_lch[chain_id].linked_dmach_q;
1449 1619
1450 /* DMA Errata: 1620 /*
1621 * DMA Errata:
1451 * Special programming model needed to disable DMA before end of block 1622 * Special programming model needed to disable DMA before end of block
1452 */ 1623 */
1453 sys_cf = omap_readl(OMAP_DMA4_OCP_SYSCONFIG); 1624 sys_cf = dma_read(OCP_SYSCONFIG);
1454 w = sys_cf; 1625 l = sys_cf;
1455 /* Middle mode reg set no Standby */ 1626 /* Middle mode reg set no Standby */
1456 w &= ~((1 << 12)|(1 << 13)); 1627 l &= ~((1 << 12)|(1 << 13));
1457 omap_writel(w, OMAP_DMA4_OCP_SYSCONFIG); 1628 dma_write(l, OCP_SYSCONFIG);
1458 1629
1459 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { 1630 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1460 1631
1461 /* Stop the Channel transmission */ 1632 /* Stop the Channel transmission */
1462 w = OMAP_DMA_CCR_REG(channels[i]); 1633 l = dma_read(CCR(channels[i]));
1463 w &= ~(1 << 7); 1634 l &= ~(1 << 7);
1464 OMAP_DMA_CCR_REG(channels[i]) = w; 1635 dma_write(l, CCR(channels[i]));
1465 1636
1466 /* Disable the link in all the channels */ 1637 /* Disable the link in all the channels */
1467 disable_lnk(channels[i]); 1638 disable_lnk(channels[i]);
@@ -1474,7 +1645,8 @@ int omap_stop_dma_chain_transfers(int chain_id)
1474 OMAP_DMA_CHAIN_QINIT(chain_id); 1645 OMAP_DMA_CHAIN_QINIT(chain_id);
1475 1646
1476 /* Errata - put in the old value */ 1647 /* Errata - put in the old value */
1477 omap_writel(sys_cf, OMAP_DMA4_OCP_SYSCONFIG); 1648 dma_write(sys_cf, OCP_SYSCONFIG);
1649
1478 return 0; 1650 return 0;
1479} 1651}
1480EXPORT_SYMBOL(omap_stop_dma_chain_transfers); 1652EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
@@ -1497,7 +1669,7 @@ int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1497 int *channels; 1669 int *channels;
1498 1670
1499 /* Check for input params */ 1671 /* Check for input params */
1500 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1672 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1501 printk(KERN_ERR "Invalid chain id\n"); 1673 printk(KERN_ERR "Invalid chain id\n");
1502 return -EINVAL; 1674 return -EINVAL;
1503 } 1675 }
@@ -1515,8 +1687,8 @@ int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1515 /* Get the current channel */ 1687 /* Get the current channel */
1516 lch = channels[dma_linked_lch[chain_id].q_head]; 1688 lch = channels[dma_linked_lch[chain_id].q_head];
1517 1689
1518 *ei = OMAP2_DMA_CCEN_REG(lch); 1690 *ei = dma_read(CCEN(lch));
1519 *fi = OMAP2_DMA_CCFN_REG(lch); 1691 *fi = dma_read(CCFN(lch));
1520 1692
1521 return 0; 1693 return 0;
1522} 1694}
@@ -1537,7 +1709,7 @@ int omap_get_dma_chain_dst_pos(int chain_id)
1537 int *channels; 1709 int *channels;
1538 1710
1539 /* Check for input params */ 1711 /* Check for input params */
1540 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1712 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1541 printk(KERN_ERR "Invalid chain id\n"); 1713 printk(KERN_ERR "Invalid chain id\n");
1542 return -EINVAL; 1714 return -EINVAL;
1543 } 1715 }
@@ -1553,7 +1725,7 @@ int omap_get_dma_chain_dst_pos(int chain_id)
1553 /* Get the current channel */ 1725 /* Get the current channel */
1554 lch = channels[dma_linked_lch[chain_id].q_head]; 1726 lch = channels[dma_linked_lch[chain_id].q_head];
1555 1727
1556 return (OMAP_DMA_CDAC_REG(lch)); 1728 return dma_read(CDAC(lch));
1557} 1729}
1558EXPORT_SYMBOL(omap_get_dma_chain_dst_pos); 1730EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1559 1731
@@ -1571,7 +1743,7 @@ int omap_get_dma_chain_src_pos(int chain_id)
1571 int *channels; 1743 int *channels;
1572 1744
1573 /* Check for input params */ 1745 /* Check for input params */
1574 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1746 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1575 printk(KERN_ERR "Invalid chain id\n"); 1747 printk(KERN_ERR "Invalid chain id\n");
1576 return -EINVAL; 1748 return -EINVAL;
1577 } 1749 }
@@ -1587,10 +1759,10 @@ int omap_get_dma_chain_src_pos(int chain_id)
1587 /* Get the current channel */ 1759 /* Get the current channel */
1588 lch = channels[dma_linked_lch[chain_id].q_head]; 1760 lch = channels[dma_linked_lch[chain_id].q_head];
1589 1761
1590 return (OMAP_DMA_CSAC_REG(lch)); 1762 return dma_read(CSAC(lch));
1591} 1763}
1592EXPORT_SYMBOL(omap_get_dma_chain_src_pos); 1764EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1593#endif 1765#endif /* ifndef CONFIG_ARCH_OMAP1 */
1594 1766
1595/*----------------------------------------------------------------------------*/ 1767/*----------------------------------------------------------------------------*/
1596 1768
@@ -1598,13 +1770,13 @@ EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1598 1770
1599static int omap1_dma_handle_ch(int ch) 1771static int omap1_dma_handle_ch(int ch)
1600{ 1772{
1601 u16 csr; 1773 u32 csr;
1602 1774
1603 if (enable_1510_mode && ch >= 6) { 1775 if (enable_1510_mode && ch >= 6) {
1604 csr = dma_chan[ch].saved_csr; 1776 csr = dma_chan[ch].saved_csr;
1605 dma_chan[ch].saved_csr = 0; 1777 dma_chan[ch].saved_csr = 0;
1606 } else 1778 } else
1607 csr = OMAP_DMA_CSR_REG(ch); 1779 csr = dma_read(CSR(ch));
1608 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { 1780 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1609 dma_chan[ch + 6].saved_csr = csr >> 7; 1781 dma_chan[ch + 6].saved_csr = csr >> 7;
1610 csr &= 0x7f; 1782 csr &= 0x7f;
@@ -1626,6 +1798,7 @@ static int omap1_dma_handle_ch(int ch)
1626 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; 1798 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1627 if (likely(dma_chan[ch].callback != NULL)) 1799 if (likely(dma_chan[ch].callback != NULL))
1628 dma_chan[ch].callback(ch, csr, dma_chan[ch].data); 1800 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1801
1629 return 1; 1802 return 1;
1630} 1803}
1631 1804
@@ -1656,12 +1829,13 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1656 1829
1657static int omap2_dma_handle_ch(int ch) 1830static int omap2_dma_handle_ch(int ch)
1658{ 1831{
1659 u32 status = OMAP_DMA_CSR_REG(ch); 1832 u32 status = dma_read(CSR(ch));
1660 1833
1661 if (!status) { 1834 if (!status) {
1662 if (printk_ratelimit()) 1835 if (printk_ratelimit())
1663 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", ch); 1836 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1664 omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0); 1837 ch);
1838 dma_write(1 << ch, IRQSTATUS_L0);
1665 return 0; 1839 return 0;
1666 } 1840 }
1667 if (unlikely(dma_chan[ch].dev_id == -1)) { 1841 if (unlikely(dma_chan[ch].dev_id == -1)) {
@@ -1684,14 +1858,14 @@ static int omap2_dma_handle_ch(int ch)
1684 printk(KERN_INFO "DMA misaligned error with device %d\n", 1858 printk(KERN_INFO "DMA misaligned error with device %d\n",
1685 dma_chan[ch].dev_id); 1859 dma_chan[ch].dev_id);
1686 1860
1687 OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK; 1861 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1688 omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0); 1862 dma_write(1 << ch, IRQSTATUS_L0);
1689 1863
1690 /* If the ch is not chained then chain_id will be -1 */ 1864 /* If the ch is not chained then chain_id will be -1 */
1691 if (dma_chan[ch].chain_id != -1) { 1865 if (dma_chan[ch].chain_id != -1) {
1692 int chain_id = dma_chan[ch].chain_id; 1866 int chain_id = dma_chan[ch].chain_id;
1693 dma_chan[ch].state = DMA_CH_NOTSTARTED; 1867 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1694 if (OMAP_DMA_CLNK_CTRL_REG(ch) & (1 << 15)) 1868 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1695 dma_chan[dma_chan[ch].next_linked_ch].state = 1869 dma_chan[dma_chan[ch].next_linked_ch].state =
1696 DMA_CH_STARTED; 1870 DMA_CH_STARTED;
1697 if (dma_linked_lch[chain_id].chain_mode == 1871 if (dma_linked_lch[chain_id].chain_mode ==
@@ -1701,13 +1875,13 @@ static int omap2_dma_handle_ch(int ch)
1701 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) 1875 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1702 OMAP_DMA_CHAIN_INCQHEAD(chain_id); 1876 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1703 1877
1704 status = OMAP_DMA_CSR_REG(ch); 1878 status = dma_read(CSR(ch));
1705 } 1879 }
1706 1880
1707 if (likely(dma_chan[ch].callback != NULL)) 1881 if (likely(dma_chan[ch].callback != NULL))
1708 dma_chan[ch].callback(ch, status, dma_chan[ch].data); 1882 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1709 1883
1710 OMAP_DMA_CSR_REG(ch) = status; 1884 dma_write(status, CSR(ch));
1711 1885
1712 return 0; 1886 return 0;
1713} 1887}
@@ -1718,13 +1892,13 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1718 u32 val; 1892 u32 val;
1719 int i; 1893 int i;
1720 1894
1721 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0); 1895 val = dma_read(IRQSTATUS_L0);
1722 if (val == 0) { 1896 if (val == 0) {
1723 if (printk_ratelimit()) 1897 if (printk_ratelimit())
1724 printk(KERN_WARNING "Spurious DMA IRQ\n"); 1898 printk(KERN_WARNING "Spurious DMA IRQ\n");
1725 return IRQ_HANDLED; 1899 return IRQ_HANDLED;
1726 } 1900 }
1727 for (i = 0; i < OMAP_LOGICAL_DMA_CH_COUNT && val != 0; i++) { 1901 for (i = 0; i < dma_lch_count && val != 0; i++) {
1728 if (val & 1) 1902 if (val & 1)
1729 omap2_dma_handle_ch(i); 1903 omap2_dma_handle_ch(i);
1730 val >>= 1; 1904 val >>= 1;
@@ -1748,7 +1922,7 @@ static struct irqaction omap24xx_dma_irq;
1748static struct lcd_dma_info { 1922static struct lcd_dma_info {
1749 spinlock_t lock; 1923 spinlock_t lock;
1750 int reserved; 1924 int reserved;
1751 void (* callback)(u16 status, void *data); 1925 void (*callback)(u16 status, void *data);
1752 void *cb_data; 1926 void *cb_data;
1753 1927
1754 int active; 1928 int active;
@@ -1770,6 +1944,7 @@ void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1770 lcd_dma.xres = fb_xres; 1944 lcd_dma.xres = fb_xres;
1771 lcd_dma.yres = fb_yres; 1945 lcd_dma.yres = fb_yres;
1772} 1946}
1947EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1773 1948
1774void omap_set_lcd_dma_src_port(int port) 1949void omap_set_lcd_dma_src_port(int port)
1775{ 1950{
@@ -1780,12 +1955,13 @@ void omap_set_lcd_dma_ext_controller(int external)
1780{ 1955{
1781 lcd_dma.ext_ctrl = external; 1956 lcd_dma.ext_ctrl = external;
1782} 1957}
1958EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1783 1959
1784void omap_set_lcd_dma_single_transfer(int single) 1960void omap_set_lcd_dma_single_transfer(int single)
1785{ 1961{
1786 lcd_dma.single_transfer = single; 1962 lcd_dma.single_transfer = single;
1787} 1963}
1788 1964EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
1789 1965
1790void omap_set_lcd_dma_b1_rotation(int rotate) 1966void omap_set_lcd_dma_b1_rotation(int rotate)
1791{ 1967{
@@ -1796,6 +1972,7 @@ void omap_set_lcd_dma_b1_rotation(int rotate)
1796 } 1972 }
1797 lcd_dma.rotate = rotate; 1973 lcd_dma.rotate = rotate;
1798} 1974}
1975EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
1799 1976
1800void omap_set_lcd_dma_b1_mirror(int mirror) 1977void omap_set_lcd_dma_b1_mirror(int mirror)
1801{ 1978{
@@ -1805,6 +1982,7 @@ void omap_set_lcd_dma_b1_mirror(int mirror)
1805 } 1982 }
1806 lcd_dma.mirror = mirror; 1983 lcd_dma.mirror = mirror;
1807} 1984}
1985EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
1808 1986
1809void omap_set_lcd_dma_b1_vxres(unsigned long vxres) 1987void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1810{ 1988{
@@ -1815,6 +1993,7 @@ void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1815 } 1993 }
1816 lcd_dma.vxres = vxres; 1994 lcd_dma.vxres = vxres;
1817} 1995}
1996EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
1818 1997
1819void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale) 1998void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
1820{ 1999{
@@ -1825,6 +2004,7 @@ void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
1825 lcd_dma.xscale = xscale; 2004 lcd_dma.xscale = xscale;
1826 lcd_dma.yscale = yscale; 2005 lcd_dma.yscale = yscale;
1827} 2006}
2007EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
1828 2008
1829static void set_b1_regs(void) 2009static void set_b1_regs(void)
1830{ 2010{
@@ -1855,8 +2035,11 @@ static void set_b1_regs(void)
1855 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1; 2035 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
1856 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1; 2036 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
1857 BUG_ON(vxres < lcd_dma.xres); 2037 BUG_ON(vxres < lcd_dma.xres);
1858#define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es) 2038
2039#define PIXADDR(x, y) (lcd_dma.addr + \
2040 ((y) * vxres * yscale + (x) * xscale) * es)
1859#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1) 2041#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2042
1860 switch (lcd_dma.rotate) { 2043 switch (lcd_dma.rotate) {
1861 case 0: 2044 case 0:
1862 if (!lcd_dma.mirror) { 2045 if (!lcd_dma.mirror) {
@@ -1865,8 +2048,8 @@ static void set_b1_regs(void)
1865 /* 1510 DMA requires the bottom address to be 2 more 2048 /* 1510 DMA requires the bottom address to be 2 more
1866 * than the actual last memory access location. */ 2049 * than the actual last memory access location. */
1867 if (omap_dma_in_1510_mode() && 2050 if (omap_dma_in_1510_mode() &&
1868 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32) 2051 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
1869 bottom += 2; 2052 bottom += 2;
1870 ei = PIXSTEP(0, 0, 1, 0); 2053 ei = PIXSTEP(0, 0, 1, 0);
1871 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1); 2054 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
1872 } else { 2055 } else {
@@ -1993,7 +2176,7 @@ static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
1993 return IRQ_HANDLED; 2176 return IRQ_HANDLED;
1994} 2177}
1995 2178
1996int omap_request_lcd_dma(void (* callback)(u16 status, void *data), 2179int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
1997 void *data) 2180 void *data)
1998{ 2181{
1999 spin_lock_irq(&lcd_dma.lock); 2182 spin_lock_irq(&lcd_dma.lock);
@@ -2019,6 +2202,7 @@ int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
2019 2202
2020 return 0; 2203 return 0;
2021} 2204}
2205EXPORT_SYMBOL(omap_request_lcd_dma);
2022 2206
2023void omap_free_lcd_dma(void) 2207void omap_free_lcd_dma(void)
2024{ 2208{
@@ -2035,12 +2219,14 @@ void omap_free_lcd_dma(void)
2035 lcd_dma.reserved = 0; 2219 lcd_dma.reserved = 0;
2036 spin_unlock(&lcd_dma.lock); 2220 spin_unlock(&lcd_dma.lock);
2037} 2221}
2222EXPORT_SYMBOL(omap_free_lcd_dma);
2038 2223
2039void omap_enable_lcd_dma(void) 2224void omap_enable_lcd_dma(void)
2040{ 2225{
2041 u16 w; 2226 u16 w;
2042 2227
2043 /* Set the Enable bit only if an external controller is 2228 /*
2229 * Set the Enable bit only if an external controller is
2044 * connected. Otherwise the OMAP internal controller will 2230 * connected. Otherwise the OMAP internal controller will
2045 * start the transfer when it gets enabled. 2231 * start the transfer when it gets enabled.
2046 */ 2232 */
@@ -2057,6 +2243,7 @@ void omap_enable_lcd_dma(void)
2057 w |= 1 << 7; 2243 w |= 1 << 7;
2058 omap_writew(w, OMAP1610_DMA_LCD_CCR); 2244 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2059} 2245}
2246EXPORT_SYMBOL(omap_enable_lcd_dma);
2060 2247
2061void omap_setup_lcd_dma(void) 2248void omap_setup_lcd_dma(void)
2062{ 2249{
@@ -2072,16 +2259,18 @@ void omap_setup_lcd_dma(void)
2072 u16 w; 2259 u16 w;
2073 2260
2074 w = omap_readw(OMAP1610_DMA_LCD_CCR); 2261 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2075 /* If DMA was already active set the end_prog bit to have 2262 /*
2263 * If DMA was already active set the end_prog bit to have
2076 * the programmed register set loaded into the active 2264 * the programmed register set loaded into the active
2077 * register set. 2265 * register set.
2078 */ 2266 */
2079 w |= 1 << 11; /* End_prog */ 2267 w |= 1 << 11; /* End_prog */
2080 if (!lcd_dma.single_transfer) 2268 if (!lcd_dma.single_transfer)
2081 w |= (3 << 8); /* Auto_init, repeat */ 2269 w |= (3 << 8); /* Auto_init, repeat */
2082 omap_writew(w, OMAP1610_DMA_LCD_CCR); 2270 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2083 } 2271 }
2084} 2272}
2273EXPORT_SYMBOL(omap_setup_lcd_dma);
2085 2274
2086void omap_stop_lcd_dma(void) 2275void omap_stop_lcd_dma(void)
2087{ 2276{
@@ -2099,6 +2288,7 @@ void omap_stop_lcd_dma(void)
2099 w &= ~(1 << 8); 2288 w &= ~(1 << 8);
2100 omap_writew(w, OMAP1610_DMA_LCD_CTRL); 2289 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2101} 2290}
2291EXPORT_SYMBOL(omap_stop_lcd_dma);
2102 2292
2103/*----------------------------------------------------------------------------*/ 2293/*----------------------------------------------------------------------------*/
2104 2294
@@ -2106,27 +2296,55 @@ static int __init omap_init_dma(void)
2106{ 2296{
2107 int ch, r; 2297 int ch, r;
2108 2298
2299 if (cpu_class_is_omap1()) {
2300 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP1_DMA_BASE);
2301 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2302 } else if (cpu_is_omap24xx()) {
2303 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP24XX_DMA4_BASE);
2304 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2305 } else if (cpu_is_omap34xx()) {
2306 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP34XX_DMA4_BASE);
2307 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2308 } else {
2309 pr_err("DMA init failed for unsupported omap\n");
2310 return -ENODEV;
2311 }
2312
2313 dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2314 GFP_KERNEL);
2315 if (!dma_chan)
2316 return -ENOMEM;
2317
2318 if (cpu_class_is_omap2()) {
2319 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2320 dma_lch_count, GFP_KERNEL);
2321 if (!dma_linked_lch) {
2322 kfree(dma_chan);
2323 return -ENOMEM;
2324 }
2325 }
2326
2109 if (cpu_is_omap15xx()) { 2327 if (cpu_is_omap15xx()) {
2110 printk(KERN_INFO "DMA support for OMAP15xx initialized\n"); 2328 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2111 dma_chan_count = 9; 2329 dma_chan_count = 9;
2112 enable_1510_mode = 1; 2330 enable_1510_mode = 1;
2113 } else if (cpu_is_omap16xx() || cpu_is_omap730()) { 2331 } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
2114 printk(KERN_INFO "OMAP DMA hardware version %d\n", 2332 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2115 omap_readw(OMAP_DMA_HW_ID)); 2333 dma_read(HW_ID));
2116 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", 2334 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2117 (omap_readw(OMAP_DMA_CAPS_0_U) << 16) | 2335 (dma_read(CAPS_0_U) << 16) |
2118 omap_readw(OMAP_DMA_CAPS_0_L), 2336 dma_read(CAPS_0_L),
2119 (omap_readw(OMAP_DMA_CAPS_1_U) << 16) | 2337 (dma_read(CAPS_1_U) << 16) |
2120 omap_readw(OMAP_DMA_CAPS_1_L), 2338 dma_read(CAPS_1_L),
2121 omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3), 2339 dma_read(CAPS_2), dma_read(CAPS_3),
2122 omap_readw(OMAP_DMA_CAPS_4)); 2340 dma_read(CAPS_4));
2123 if (!enable_1510_mode) { 2341 if (!enable_1510_mode) {
2124 u16 w; 2342 u16 w;
2125 2343
2126 /* Disable OMAP 3.0/3.1 compatibility mode. */ 2344 /* Disable OMAP 3.0/3.1 compatibility mode. */
2127 w = omap_readw(OMAP_DMA_GSCR); 2345 w = dma_read(GSCR);
2128 w |= 1 << 3; 2346 w |= 1 << 3;
2129 omap_writew(w, OMAP_DMA_GSCR); 2347 dma_write(w, GSCR);
2130 dma_chan_count = 16; 2348 dma_chan_count = 16;
2131 } else 2349 } else
2132 dma_chan_count = 9; 2350 dma_chan_count = 9;
@@ -2139,19 +2357,17 @@ static int __init omap_init_dma(void)
2139 omap_writew(w, OMAP1610_DMA_LCD_CTRL); 2357 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2140 } 2358 }
2141 } else if (cpu_class_is_omap2()) { 2359 } else if (cpu_class_is_omap2()) {
2142 u8 revision = omap_readb(OMAP_DMA4_REVISION); 2360 u8 revision = dma_read(REVISION) & 0xff;
2143 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", 2361 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2144 revision >> 4, revision & 0xf); 2362 revision >> 4, revision & 0xf);
2145 dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT; 2363 dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2146 } else { 2364 } else {
2147 dma_chan_count = 0; 2365 dma_chan_count = 0;
2148 return 0; 2366 return 0;
2149 } 2367 }
2150 2368
2151 memset(&lcd_dma, 0, sizeof(lcd_dma));
2152 spin_lock_init(&lcd_dma.lock); 2369 spin_lock_init(&lcd_dma.lock);
2153 spin_lock_init(&dma_chan_lock); 2370 spin_lock_init(&dma_chan_lock);
2154 memset(&dma_chan, 0, sizeof(dma_chan));
2155 2371
2156 for (ch = 0; ch < dma_chan_count; ch++) { 2372 for (ch = 0; ch < dma_chan_count; ch++) {
2157 omap_clear_dma(ch); 2373 omap_clear_dma(ch);
@@ -2162,8 +2378,10 @@ static int __init omap_init_dma(void)
2162 continue; 2378 continue;
2163 2379
2164 if (cpu_class_is_omap1()) { 2380 if (cpu_class_is_omap1()) {
2165 /* request_irq() doesn't like dev_id (ie. ch) being 2381 /*
2166 * zero, so we have to kludge around this. */ 2382 * request_irq() doesn't like dev_id (ie. ch) being
2383 * zero, so we have to kludge around this.
2384 */
2167 r = request_irq(omap1_dma_irq[ch], 2385 r = request_irq(omap1_dma_irq[ch],
2168 omap1_dma_irq_handler, 0, "DMA", 2386 omap1_dma_irq_handler, 0, "DMA",
2169 (void *) (ch + 1)); 2387 (void *) (ch + 1));
@@ -2208,48 +2426,4 @@ static int __init omap_init_dma(void)
2208 2426
2209arch_initcall(omap_init_dma); 2427arch_initcall(omap_init_dma);
2210 2428
2211EXPORT_SYMBOL(omap_get_dma_src_pos);
2212EXPORT_SYMBOL(omap_get_dma_dst_pos);
2213EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
2214EXPORT_SYMBOL(omap_clear_dma);
2215EXPORT_SYMBOL(omap_set_dma_priority);
2216EXPORT_SYMBOL(omap_request_dma);
2217EXPORT_SYMBOL(omap_free_dma);
2218EXPORT_SYMBOL(omap_start_dma);
2219EXPORT_SYMBOL(omap_stop_dma);
2220EXPORT_SYMBOL(omap_set_dma_callback);
2221EXPORT_SYMBOL(omap_enable_dma_irq);
2222EXPORT_SYMBOL(omap_disable_dma_irq);
2223
2224EXPORT_SYMBOL(omap_set_dma_transfer_params);
2225EXPORT_SYMBOL(omap_set_dma_color_mode);
2226EXPORT_SYMBOL(omap_set_dma_write_mode);
2227
2228EXPORT_SYMBOL(omap_set_dma_src_params);
2229EXPORT_SYMBOL(omap_set_dma_src_index);
2230EXPORT_SYMBOL(omap_set_dma_src_data_pack);
2231EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
2232
2233EXPORT_SYMBOL(omap_set_dma_dest_params);
2234EXPORT_SYMBOL(omap_set_dma_dest_index);
2235EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
2236EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
2237
2238EXPORT_SYMBOL(omap_set_dma_params);
2239
2240EXPORT_SYMBOL(omap_dma_link_lch);
2241EXPORT_SYMBOL(omap_dma_unlink_lch);
2242
2243EXPORT_SYMBOL(omap_request_lcd_dma);
2244EXPORT_SYMBOL(omap_free_lcd_dma);
2245EXPORT_SYMBOL(omap_enable_lcd_dma);
2246EXPORT_SYMBOL(omap_setup_lcd_dma);
2247EXPORT_SYMBOL(omap_stop_lcd_dma);
2248EXPORT_SYMBOL(omap_set_lcd_dma_b1);
2249EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2250EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
2251EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2252EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2253EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2254EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2255 2429
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 17:42:05 -0500