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-rw-r--r--arch/arm/plat-mxc/avic.c2
-rw-r--r--arch/arm/plat-mxc/cpu.c24
-rw-r--r--arch/arm/plat-mxc/devices/platform-ahci-imx.c16
-rw-r--r--arch/arm/plat-mxc/epit.c2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31ads.h33
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h10
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S2
-rw-r--r--arch/arm/plat-mxc/include/mach/dma.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/io.h39
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx25.h42
-rw-r--r--arch/arm/plat-mxc/pwm.c4
-rw-r--r--arch/arm/plat-mxc/system.c4
-rw-r--r--arch/arm/plat-mxc/time.c2
14 files changed, 74 insertions, 116 deletions
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 55f15699a383..689f81f9593b 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -60,7 +60,7 @@ static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
60 unsigned int mask = 0x0F << irq % 8 * 4; 60 unsigned int mask = 0x0F << irq % 8 * 4;
61 61
62 if (irq >= AVIC_NUM_IRQS) 62 if (irq >= AVIC_NUM_IRQS)
63 return -EINVAL;; 63 return -EINVAL;
64 64
65 temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8)); 65 temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
66 temp &= ~mask; 66 temp &= ~mask;
diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c
index f5b7e0fa237f..220dd6f93126 100644
--- a/arch/arm/plat-mxc/cpu.c
+++ b/arch/arm/plat-mxc/cpu.c
@@ -1,5 +1,6 @@
1 1
2#include <linux/module.h> 2#include <linux/module.h>
3#include <linux/io.h>
3#include <mach/hardware.h> 4#include <mach/hardware.h>
4 5
5unsigned int __mxc_cpu_type; 6unsigned int __mxc_cpu_type;
@@ -18,3 +19,26 @@ void imx_print_silicon_rev(const char *cpu, int srev)
18 pr_info("CPU identified as %s, silicon rev %d.%d\n", 19 pr_info("CPU identified as %s, silicon rev %d.%d\n",
19 cpu, (srev >> 4) & 0xf, srev & 0xf); 20 cpu, (srev >> 4) & 0xf, srev & 0xf);
20} 21}
22
23void __init imx_set_aips(void __iomem *base)
24{
25 unsigned int reg;
26/*
27 * Set all MPROTx to be non-bufferable, trusted for R/W,
28 * not forced to user-mode.
29 */
30 __raw_writel(0x77777777, base + 0x0);
31 __raw_writel(0x77777777, base + 0x4);
32
33/*
34 * Set all OPACRx to be non-bufferable, to not require
35 * supervisor privilege level for access, allow for
36 * write access and untrusted master access.
37 */
38 __raw_writel(0x0, base + 0x40);
39 __raw_writel(0x0, base + 0x44);
40 __raw_writel(0x0, base + 0x48);
41 __raw_writel(0x0, base + 0x4C);
42 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
43 __raw_writel(reg, base + 0x50);
44}
diff --git a/arch/arm/plat-mxc/devices/platform-ahci-imx.c b/arch/arm/plat-mxc/devices/platform-ahci-imx.c
index d8a56aee521b..ade4a1c4e2a3 100644
--- a/arch/arm/plat-mxc/devices/platform-ahci-imx.c
+++ b/arch/arm/plat-mxc/devices/platform-ahci-imx.c
@@ -60,9 +60,9 @@ static int imx_sata_init(struct device *dev, void __iomem *addr)
60 dev_err(dev, "no sata clock.\n"); 60 dev_err(dev, "no sata clock.\n");
61 return PTR_ERR(sata_clk); 61 return PTR_ERR(sata_clk);
62 } 62 }
63 ret = clk_enable(sata_clk); 63 ret = clk_prepare_enable(sata_clk);
64 if (ret) { 64 if (ret) {
65 dev_err(dev, "can't enable sata clock.\n"); 65 dev_err(dev, "can't prepare/enable sata clock.\n");
66 goto put_sata_clk; 66 goto put_sata_clk;
67 } 67 }
68 68
@@ -73,9 +73,9 @@ static int imx_sata_init(struct device *dev, void __iomem *addr)
73 ret = PTR_ERR(sata_ref_clk); 73 ret = PTR_ERR(sata_ref_clk);
74 goto release_sata_clk; 74 goto release_sata_clk;
75 } 75 }
76 ret = clk_enable(sata_ref_clk); 76 ret = clk_prepare_enable(sata_ref_clk);
77 if (ret) { 77 if (ret) {
78 dev_err(dev, "can't enable sata ref clock.\n"); 78 dev_err(dev, "can't prepare/enable sata ref clock.\n");
79 goto put_sata_ref_clk; 79 goto put_sata_ref_clk;
80 } 80 }
81 81
@@ -104,11 +104,11 @@ static int imx_sata_init(struct device *dev, void __iomem *addr)
104 return 0; 104 return 0;
105 105
106release_sata_ref_clk: 106release_sata_ref_clk:
107 clk_disable(sata_ref_clk); 107 clk_disable_unprepare(sata_ref_clk);
108put_sata_ref_clk: 108put_sata_ref_clk:
109 clk_put(sata_ref_clk); 109 clk_put(sata_ref_clk);
110release_sata_clk: 110release_sata_clk:
111 clk_disable(sata_clk); 111 clk_disable_unprepare(sata_clk);
112put_sata_clk: 112put_sata_clk:
113 clk_put(sata_clk); 113 clk_put(sata_clk);
114 114
@@ -117,10 +117,10 @@ put_sata_clk:
117 117
118static void imx_sata_exit(struct device *dev) 118static void imx_sata_exit(struct device *dev)
119{ 119{
120 clk_disable(sata_ref_clk); 120 clk_disable_unprepare(sata_ref_clk);
121 clk_put(sata_ref_clk); 121 clk_put(sata_ref_clk);
122 122
123 clk_disable(sata_clk); 123 clk_disable_unprepare(sata_clk);
124 clk_put(sata_clk); 124 clk_put(sata_clk);
125 125
126} 126}
diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c
index d3467f818c33..9129c9e7d532 100644
--- a/arch/arm/plat-mxc/epit.c
+++ b/arch/arm/plat-mxc/epit.c
@@ -203,7 +203,7 @@ static int __init epit_clockevent_init(struct clk *timer_clk)
203 203
204void __init epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq) 204void __init epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
205{ 205{
206 clk_enable(timer_clk); 206 clk_prepare_enable(timer_clk);
207 207
208 timer_base = base; 208 timer_base = base;
209 209
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
deleted file mode 100644
index 94b60dd47137..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
12#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
13
14#include <mach/hardware.h>
15
16/*
17 * These symbols are used by drivers/net/cs89x0.c.
18 * This is ugly as hell, but we have to provide them until
19 * someone fixed the driver.
20 */
21
22/* Base address of PBC controller */
23#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
24/* Offsets for the PBC Controller register */
25
26/* Ethernet Controller IO base address */
27#define PBC_CS8900A_IOBASE 0x020000
28
29#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
30
31#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
32
33#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 1bf0df81bdc6..0319c4a0cafa 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -65,6 +65,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
65 unsigned long ckih1, unsigned long ckih2); 65 unsigned long ckih1, unsigned long ckih2);
66extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, 66extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
67 unsigned long ckih1, unsigned long ckih2); 67 unsigned long ckih1, unsigned long ckih2);
68extern int mx27_clocks_init_dt(void);
68extern int mx51_clocks_init_dt(void); 69extern int mx51_clocks_init_dt(void);
69extern int mx53_clocks_init_dt(void); 70extern int mx53_clocks_init_dt(void);
70extern int mx6q_clocks_init(void); 71extern int mx6q_clocks_init(void);
@@ -75,6 +76,7 @@ extern void mxc_restart(char, const char *);
75extern void mxc_arch_reset_init(void __iomem *); 76extern void mxc_arch_reset_init(void __iomem *);
76extern int mx53_revision(void); 77extern int mx53_revision(void);
77extern int mx53_display_revision(void); 78extern int mx53_display_revision(void);
79extern void imx_set_aips(void __iomem *);
78 80
79enum mxc_cpu_pwr_mode { 81enum mxc_cpu_pwr_mode {
80 WAIT_CLOCKED, /* wfi only */ 82 WAIT_CLOCKED, /* wfi only */
@@ -84,6 +86,14 @@ enum mxc_cpu_pwr_mode {
84 STOP_POWER_OFF, /* STOP + SRPG */ 86 STOP_POWER_OFF, /* STOP + SRPG */
85}; 87};
86 88
89enum mx3_cpu_pwr_mode {
90 MX3_RUN,
91 MX3_WAIT,
92 MX3_DOZE,
93 MX3_SLEEP,
94};
95
96extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
87extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode); 97extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
88extern void imx_print_silicon_rev(const char *cpu, int srev); 98extern void imx_print_silicon_rev(const char *cpu, int srev);
89 99
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 6e192c4a391a..8ddda365f1a0 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -24,7 +24,7 @@
24#define UART_PADDR MX51_UART1_BASE_ADDR 24#define UART_PADDR MX51_UART1_BASE_ADDR
25#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART) 25#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
26#define UART_PADDR MX53_UART1_BASE_ADDR 26#define UART_PADDR MX53_UART1_BASE_ADDR
27#elif defined (CONFIG_DEBUG_IMX6Q_UART) 27#elif defined (CONFIG_DEBUG_IMX6Q_UART4)
28#define UART_PADDR MX6Q_UART4_BASE_ADDR 28#define UART_PADDR MX6Q_UART4_BASE_ADDR
29#endif 29#endif
30 30
diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h
index 233d0a5e2d68..1b9080385b46 100644
--- a/arch/arm/plat-mxc/include/mach/dma.h
+++ b/arch/arm/plat-mxc/include/mach/dma.h
@@ -60,8 +60,7 @@ static inline int imx_dma_is_ipu(struct dma_chan *chan)
60 60
61static inline int imx_dma_is_general_purpose(struct dma_chan *chan) 61static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
62{ 62{
63 return !strcmp(dev_name(chan->device->dev), "imx31-sdma") || 63 return strstr(dev_name(chan->device->dev), "sdma") ||
64 !strcmp(dev_name(chan->device->dev), "imx35-sdma") ||
65 !strcmp(dev_name(chan->device->dev), "imx-dma"); 64 !strcmp(dev_name(chan->device->dev), "imx-dma");
66} 65}
67 66
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index a599f01f8b92..0630513554de 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -22,11 +22,8 @@
22 22
23#include <asm/sizes.h> 23#include <asm/sizes.h>
24 24
25#ifdef __ASSEMBLER__ 25#define addr_in_module(addr, mod) \
26#define IOMEM(addr) (addr) 26 ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
27#else
28#define IOMEM(addr) ((void __force __iomem *)(addr))
29#endif
30 27
31#define IMX_IO_P2V_MODULE(addr, module) \ 28#define IMX_IO_P2V_MODULE(addr, module) \
32 (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \ 29 (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \
diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h
deleted file mode 100644
index 338300b18b00..000000000000
--- a/arch/arm/plat-mxc/include/mach/io.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_IO_H__
12#define __ASM_ARCH_MXC_IO_H__
13
14/* Allow IO space to be anywhere in the memory */
15#define IO_SPACE_LIMIT 0xffffffff
16
17#define __arch_ioremap __imx_ioremap
18#define __arch_iounmap __iounmap
19
20#define addr_in_module(addr, mod) \
21 ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
22
23extern void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int);
24
25static inline void __iomem *
26__imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
27{
28 if (imx_ioremap != NULL)
29 return imx_ioremap(phys_addr, size, mtype);
30 else
31 return __arm_ioremap(phys_addr, size, mtype);
32}
33
34/* io address mapping macro */
35#define __io(a) __typesafe_io(a)
36
37#define __mem_pci(a) (a)
38
39#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index f0726d48df22..c61ec0fc10d4 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -139,15 +139,15 @@
139#define MX25_PAD_NFRB__GPIO_3_31 IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL) 139#define MX25_PAD_NFRB__GPIO_3_31 IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL)
140 140
141#define MX25_PAD_D15__D15 IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL) 141#define MX25_PAD_D15__D15 IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
142#define MX25_PAD_D15__LD16 IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, NO_PAD_CTRL) 142#define MX25_PAD_D15__LD16 IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST)
143#define MX25_PAD_D15__GPIO_4_5 IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL) 143#define MX25_PAD_D15__GPIO_4_5 IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
144 144
145#define MX25_PAD_D14__D14 IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL) 145#define MX25_PAD_D14__D14 IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
146#define MX25_PAD_D14__LD17 IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, NO_PAD_CTRL) 146#define MX25_PAD_D14__LD17 IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST)
147#define MX25_PAD_D14__GPIO_4_6 IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL) 147#define MX25_PAD_D14__GPIO_4_6 IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
148 148
149#define MX25_PAD_D13__D13 IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL) 149#define MX25_PAD_D13__D13 IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
150#define MX25_PAD_D13__LD18 IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, NO_PAD_CTRL) 150#define MX25_PAD_D13__LD18 IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST)
151#define MX25_PAD_D13__GPIO_4_7 IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL) 151#define MX25_PAD_D13__GPIO_4_7 IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
152 152
153#define MX25_PAD_D12__D12 IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL) 153#define MX25_PAD_D12__D12 IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
@@ -192,54 +192,54 @@
192#define MX25_PAD_D0__D0 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL) 192#define MX25_PAD_D0__D0 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
193#define MX25_PAD_D0__GPIO_4_20 IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL) 193#define MX25_PAD_D0__GPIO_4_20 IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
194 194
195#define MX25_PAD_LD0__LD0 IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, NO_PAD_CTRL) 195#define MX25_PAD_LD0__LD0 IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
196#define MX25_PAD_LD0__CSI_D0 IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL) 196#define MX25_PAD_LD0__CSI_D0 IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL)
197#define MX25_PAD_LD0__GPIO_2_15 IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL) 197#define MX25_PAD_LD0__GPIO_2_15 IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL)
198 198
199#define MX25_PAD_LD1__LD1 IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, NO_PAD_CTRL) 199#define MX25_PAD_LD1__LD1 IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
200#define MX25_PAD_LD1__CSI_D1 IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL) 200#define MX25_PAD_LD1__CSI_D1 IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL)
201#define MX25_PAD_LD1__GPIO_2_16 IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL) 201#define MX25_PAD_LD1__GPIO_2_16 IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL)
202 202
203#define MX25_PAD_LD2__LD2 IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, NO_PAD_CTRL) 203#define MX25_PAD_LD2__LD2 IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
204#define MX25_PAD_LD2__GPIO_2_17 IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL) 204#define MX25_PAD_LD2__GPIO_2_17 IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL)
205 205
206#define MX25_PAD_LD3__LD3 IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, NO_PAD_CTRL) 206#define MX25_PAD_LD3__LD3 IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
207#define MX25_PAD_LD3__GPIO_2_18 IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL) 207#define MX25_PAD_LD3__GPIO_2_18 IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL)
208 208
209#define MX25_PAD_LD4__LD4 IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, NO_PAD_CTRL) 209#define MX25_PAD_LD4__LD4 IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
210#define MX25_PAD_LD4__GPIO_2_19 IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL) 210#define MX25_PAD_LD4__GPIO_2_19 IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL)
211 211
212#define MX25_PAD_LD5__LD5 IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, NO_PAD_CTRL) 212#define MX25_PAD_LD5__LD5 IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
213#define MX25_PAD_LD5__GPIO_1_19 IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL) 213#define MX25_PAD_LD5__GPIO_1_19 IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL)
214 214
215#define MX25_PAD_LD6__LD6 IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, NO_PAD_CTRL) 215#define MX25_PAD_LD6__LD6 IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
216#define MX25_PAD_LD6__GPIO_1_20 IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL) 216#define MX25_PAD_LD6__GPIO_1_20 IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL)
217 217
218#define MX25_PAD_LD7__LD7 IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, NO_PAD_CTRL) 218#define MX25_PAD_LD7__LD7 IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
219#define MX25_PAD_LD7__GPIO_1_21 IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL) 219#define MX25_PAD_LD7__GPIO_1_21 IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
220 220
221#define MX25_PAD_LD8__LD8 IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL) 221#define MX25_PAD_LD8__LD8 IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
222#define MX25_PAD_LD8__FEC_TX_ERR IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL) 222#define MX25_PAD_LD8__FEC_TX_ERR IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL)
223 223
224#define MX25_PAD_LD9__LD9 IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL) 224#define MX25_PAD_LD9__LD9 IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST)
225#define MX25_PAD_LD9__FEC_COL IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL) 225#define MX25_PAD_LD9__FEC_COL IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL)
226 226
227#define MX25_PAD_LD10__LD10 IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL) 227#define MX25_PAD_LD10__LD10 IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
228#define MX25_PAD_LD10__FEC_RX_ER IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL) 228#define MX25_PAD_LD10__FEC_RX_ER IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL)
229 229
230#define MX25_PAD_LD11__LD11 IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL) 230#define MX25_PAD_LD11__LD11 IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
231#define MX25_PAD_LD11__FEC_RDATA2 IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL) 231#define MX25_PAD_LD11__FEC_RDATA2 IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL)
232 232
233#define MX25_PAD_LD12__LD12 IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL) 233#define MX25_PAD_LD12__LD12 IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
234#define MX25_PAD_LD12__FEC_RDATA3 IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL) 234#define MX25_PAD_LD12__FEC_RDATA3 IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL)
235 235
236#define MX25_PAD_LD13__LD13 IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL) 236#define MX25_PAD_LD13__LD13 IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
237#define MX25_PAD_LD13__FEC_TDATA2 IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL) 237#define MX25_PAD_LD13__FEC_TDATA2 IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL)
238 238
239#define MX25_PAD_LD14__LD14 IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL) 239#define MX25_PAD_LD14__LD14 IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST)
240#define MX25_PAD_LD14__FEC_TDATA3 IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL) 240#define MX25_PAD_LD14__FEC_TDATA3 IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL)
241 241
242#define MX25_PAD_LD15__LD15 IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL) 242#define MX25_PAD_LD15__LD15 IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST)
243#define MX25_PAD_LD15__FEC_RX_CLK IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL) 243#define MX25_PAD_LD15__FEC_RX_CLK IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL)
244 244
245#define MX25_PAD_HSYNC__HSYNC IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL) 245#define MX25_PAD_HSYNC__HSYNC IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
@@ -468,11 +468,11 @@
468#define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP) 468#define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
469 469
470#define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL) 470#define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
471#define MX25_PAD_GPIO_E__LD16 IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, NO_PAD_CTRL) 471#define MX25_PAD_GPIO_E__LD16 IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST)
472#define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP) 472#define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
473 473
474#define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL) 474#define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
475#define MX25_PAD_GPIO_F__LD17 IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, NO_PAD_CTRL) 475#define MX25_PAD_GPIO_F__LD17 IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST)
476#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL) 476#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
477 477
478#define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL) 478#define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
index e032717f7d02..c0cab2270dd1 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/arch/arm/plat-mxc/pwm.c
@@ -132,7 +132,7 @@ int pwm_enable(struct pwm_device *pwm)
132 int rc = 0; 132 int rc = 0;
133 133
134 if (!pwm->clk_enabled) { 134 if (!pwm->clk_enabled) {
135 rc = clk_enable(pwm->clk); 135 rc = clk_prepare_enable(pwm->clk);
136 if (!rc) 136 if (!rc)
137 pwm->clk_enabled = 1; 137 pwm->clk_enabled = 1;
138 } 138 }
@@ -145,7 +145,7 @@ void pwm_disable(struct pwm_device *pwm)
145 writel(0, pwm->mmio_base + MX3_PWMCR); 145 writel(0, pwm->mmio_base + MX3_PWMCR);
146 146
147 if (pwm->clk_enabled) { 147 if (pwm->clk_enabled) {
148 clk_disable(pwm->clk); 148 clk_disable_unprepare(pwm->clk);
149 pwm->clk_enabled = 0; 149 pwm->clk_enabled = 0;
150 } 150 }
151} 151}
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 3599bf2cfd4f..1996c3e3b8fe 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -25,8 +25,8 @@
25 25
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/common.h> 27#include <mach/common.h>
28#include <asm/system_misc.h>
28#include <asm/proc-fns.h> 29#include <asm/proc-fns.h>
29#include <asm/system.h>
30#include <asm/mach-types.h> 30#include <asm/mach-types.h>
31 31
32void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL; 32void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
@@ -48,7 +48,7 @@ void mxc_restart(char mode, const char *cmd)
48 48
49 clk = clk_get_sys("imx2-wdt.0", NULL); 49 clk = clk_get_sys("imx2-wdt.0", NULL);
50 if (!IS_ERR(clk)) 50 if (!IS_ERR(clk))
51 clk_enable(clk); 51 clk_prepare_enable(clk);
52 wcr_enable = (1 << 2); 52 wcr_enable = (1 << 2);
53 } 53 }
54 54
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 1c96cdb4c35e..7daf7c9a413b 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -283,7 +283,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
283{ 283{
284 uint32_t tctl_val; 284 uint32_t tctl_val;
285 285
286 clk_enable(timer_clk); 286 clk_prepare_enable(timer_clk);
287 287
288 timer_base = base; 288 timer_base = base;
289 289