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-rw-r--r--arch/arm/plat-mxc/Kconfig17
-rw-r--r--arch/arm/plat-mxc/clock.c170
-rw-r--r--arch/arm/plat-mxc/gpio.c42
-rw-r--r--arch/arm/plat-mxc/include/mach/board-armadillo5x0.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h40
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx21ads.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx27ads.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx27lite.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx27pdk.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31ads.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31lilly.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31lite.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31moboard.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31pdk.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx35pdk.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/board-pcm037.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/board-pcm038.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/board-pcm043.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/board-qong.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h19
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S68
-rw-r--r--arch/arm/plat-mxc/include/mach/entry-macro.S3
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/imxfb.h29
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx25.h517
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx3.h25
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mxc91231.h287
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v3.h35
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mx1.h22
-rw-r--r--arch/arm/plat-mxc/include/mach/mx21.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h44
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/mx2x.h18
-rw-r--r--arch/arm/plat-mxc/include/mach/mx31.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h1
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3x.h21
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h28
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc91231.h315
-rw-r--r--arch/arm/plat-mxc/include/mach/system.h10
-rw-r--r--arch/arm/plat-mxc/include/mach/timex.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h68
-rw-r--r--arch/arm/plat-mxc/iomux-v3.c15
-rw-r--r--arch/arm/plat-mxc/irq.c6
-rw-r--r--arch/arm/plat-mxc/pwm.c19
-rw-r--r--arch/arm/plat-mxc/system.c29
-rw-r--r--arch/arm/plat-mxc/time.c39
49 files changed, 1539 insertions, 465 deletions
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 8986b7412235..ca5c7c226341 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -9,6 +9,7 @@ choice
9config ARCH_MX1 9config ARCH_MX1
10 bool "MX1-based" 10 bool "MX1-based"
11 select CPU_ARM920T 11 select CPU_ARM920T
12 select COMMON_CLKDEV
12 help 13 help
13 This enables support for systems based on the Freescale i.MX1 family 14 This enables support for systems based on the Freescale i.MX1 family
14 15
@@ -19,6 +20,13 @@ config ARCH_MX2
19 help 20 help
20 This enables support for systems based on the Freescale i.MX2 family 21 This enables support for systems based on the Freescale i.MX2 family
21 22
23config ARCH_MX25
24 bool "MX25-based"
25 select CPU_ARM926T
26 select COMMON_CLKDEV
27 help
28 This enables support for systems based on the Freescale i.MX25 family
29
22config ARCH_MX3 30config ARCH_MX3
23 bool "MX3-based" 31 bool "MX3-based"
24 select CPU_V6 32 select CPU_V6
@@ -26,11 +34,20 @@ config ARCH_MX3
26 help 34 help
27 This enables support for systems based on the Freescale i.MX3 family 35 This enables support for systems based on the Freescale i.MX3 family
28 36
37config ARCH_MXC91231
38 bool "MXC91231-based"
39 select CPU_V6
40 select COMMON_CLKDEV
41 help
42 This enables support for systems based on the Freescale MXC91231 family
43
29endchoice 44endchoice
30 45
31source "arch/arm/mach-mx1/Kconfig" 46source "arch/arm/mach-mx1/Kconfig"
32source "arch/arm/mach-mx2/Kconfig" 47source "arch/arm/mach-mx2/Kconfig"
33source "arch/arm/mach-mx3/Kconfig" 48source "arch/arm/mach-mx3/Kconfig"
49source "arch/arm/mach-mx25/Kconfig"
50source "arch/arm/mach-mxc91231/Kconfig"
34 51
35endmenu 52endmenu
36 53
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 92e13566cd4f..9e8fbd57495c 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -39,6 +39,7 @@
39#include <linux/string.h> 39#include <linux/string.h>
40 40
41#include <mach/clock.h> 41#include <mach/clock.h>
42#include <mach/hardware.h>
42 43
43static LIST_HEAD(clocks); 44static LIST_HEAD(clocks);
44static DEFINE_MUTEX(clocks_mutex); 45static DEFINE_MUTEX(clocks_mutex);
@@ -47,76 +48,6 @@ static DEFINE_MUTEX(clocks_mutex);
47 * Standard clock functions defined in include/linux/clk.h 48 * Standard clock functions defined in include/linux/clk.h
48 *-------------------------------------------------------------------------*/ 49 *-------------------------------------------------------------------------*/
49 50
50/*
51 * All the code inside #ifndef CONFIG_COMMON_CLKDEV can be removed once all
52 * MXC architectures have switched to using clkdev.
53 */
54#ifndef CONFIG_COMMON_CLKDEV
55/*
56 * Retrieve a clock by name.
57 *
58 * Note that we first try to use device id on the bus
59 * and clock name. If this fails, we try to use "<name>.<id>". If this fails,
60 * we try to use clock name only.
61 * The reference count to the clock's module owner ref count is incremented.
62 */
63struct clk *clk_get(struct device *dev, const char *id)
64{
65 struct clk *p, *clk = ERR_PTR(-ENOENT);
66 int idno;
67 const char *str;
68
69 if (id == NULL)
70 return clk;
71
72 if (dev == NULL || dev->bus != &platform_bus_type)
73 idno = -1;
74 else
75 idno = to_platform_device(dev)->id;
76
77 mutex_lock(&clocks_mutex);
78
79 list_for_each_entry(p, &clocks, node) {
80 if (p->id == idno &&
81 strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
82 clk = p;
83 goto found;
84 }
85 }
86
87 str = strrchr(id, '.');
88 if (str) {
89 int cnt = str - id;
90 str++;
91 idno = simple_strtol(str, NULL, 10);
92 list_for_each_entry(p, &clocks, node) {
93 if (p->id == idno &&
94 strlen(p->name) == cnt &&
95 strncmp(id, p->name, cnt) == 0 &&
96 try_module_get(p->owner)) {
97 clk = p;
98 goto found;
99 }
100 }
101 }
102
103 list_for_each_entry(p, &clocks, node) {
104 if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
105 clk = p;
106 goto found;
107 }
108 }
109
110 printk(KERN_WARNING "clk: Unable to get requested clock: %s\n", id);
111
112found:
113 mutex_unlock(&clocks_mutex);
114
115 return clk;
116}
117EXPORT_SYMBOL(clk_get);
118#endif
119
120static void __clk_disable(struct clk *clk) 51static void __clk_disable(struct clk *clk)
121{ 52{
122 if (clk == NULL || IS_ERR(clk)) 53 if (clk == NULL || IS_ERR(clk))
@@ -193,16 +124,6 @@ unsigned long clk_get_rate(struct clk *clk)
193} 124}
194EXPORT_SYMBOL(clk_get_rate); 125EXPORT_SYMBOL(clk_get_rate);
195 126
196#ifndef CONFIG_COMMON_CLKDEV
197/* Decrement the clock's module reference count */
198void clk_put(struct clk *clk)
199{
200 if (clk && !IS_ERR(clk))
201 module_put(clk->owner);
202}
203EXPORT_SYMBOL(clk_put);
204#endif
205
206/* Round the requested clock rate to the nearest supported 127/* Round the requested clock rate to the nearest supported
207 * rate that is less than or equal to the requested rate. 128 * rate that is less than or equal to the requested rate.
208 * This is dependent on the clock's current parent. 129 * This is dependent on the clock's current parent.
@@ -265,80 +186,6 @@ struct clk *clk_get_parent(struct clk *clk)
265} 186}
266EXPORT_SYMBOL(clk_get_parent); 187EXPORT_SYMBOL(clk_get_parent);
267 188
268#ifndef CONFIG_COMMON_CLKDEV
269/*
270 * Add a new clock to the clock tree.
271 */
272int clk_register(struct clk *clk)
273{
274 if (clk == NULL || IS_ERR(clk))
275 return -EINVAL;
276
277 mutex_lock(&clocks_mutex);
278 list_add(&clk->node, &clocks);
279 mutex_unlock(&clocks_mutex);
280
281 return 0;
282}
283EXPORT_SYMBOL(clk_register);
284
285/* Remove a clock from the clock tree */
286void clk_unregister(struct clk *clk)
287{
288 if (clk == NULL || IS_ERR(clk))
289 return;
290
291 mutex_lock(&clocks_mutex);
292 list_del(&clk->node);
293 mutex_unlock(&clocks_mutex);
294}
295EXPORT_SYMBOL(clk_unregister);
296
297#ifdef CONFIG_PROC_FS
298static int mxc_clock_read_proc(char *page, char **start, off_t off,
299 int count, int *eof, void *data)
300{
301 struct clk *clkp;
302 char *p = page;
303 int len;
304
305 list_for_each_entry(clkp, &clocks, node) {
306 p += sprintf(p, "%s-%d:\t\t%lu, %d", clkp->name, clkp->id,
307 clk_get_rate(clkp), clkp->usecount);
308 if (clkp->parent)
309 p += sprintf(p, ", %s-%d\n", clkp->parent->name,
310 clkp->parent->id);
311 else
312 p += sprintf(p, "\n");
313 }
314
315 len = (p - page) - off;
316 if (len < 0)
317 len = 0;
318
319 *eof = (len <= count) ? 1 : 0;
320 *start = page + off;
321
322 return len;
323}
324
325static int __init mxc_setup_proc_entry(void)
326{
327 struct proc_dir_entry *res;
328
329 res = create_proc_read_entry("cpu/clocks", 0, NULL,
330 mxc_clock_read_proc, NULL);
331 if (!res) {
332 printk(KERN_ERR "Failed to create proc/cpu/clocks\n");
333 return -ENOMEM;
334 }
335 return 0;
336}
337
338late_initcall(mxc_setup_proc_entry);
339#endif /* CONFIG_PROC_FS */
340#endif
341
342/* 189/*
343 * Get the resulting clock rate from a PLL register value and the input 190 * Get the resulting clock rate from a PLL register value and the input
344 * frequency. PLLs with this register layout can at least be found on 191 * frequency. PLLs with this register layout can at least be found on
@@ -363,12 +210,11 @@ unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
363 210
364 mfn_abs = mfn; 211 mfn_abs = mfn;
365 212
366#if !defined CONFIG_ARCH_MX1 && !defined CONFIG_ARCH_MX21 213 /* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
367 if (mfn >= 0x200) { 214 * 2's complements number
368 mfn |= 0xFFFFFE00; 215 */
369 mfn_abs = -mfn; 216 if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
370 } 217 mfn_abs = 0x400 - mfn;
371#endif
372 218
373 freq *= 2; 219 freq *= 2;
374 freq /= pd + 1; 220 freq /= pd + 1;
@@ -376,8 +222,10 @@ unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
376 ll = (unsigned long long)freq * mfn_abs; 222 ll = (unsigned long long)freq * mfn_abs;
377 223
378 do_div(ll, mfd + 1); 224 do_div(ll, mfd + 1);
379 if (mfn < 0) 225
226 if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
380 ll = -ll; 227 ll = -ll;
228
381 ll = (freq * mfi) + ll; 229 ll = (freq * mfi) + ll;
382 230
383 return ll; 231 return ll;
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 7506d963be4b..cfc4a8b43e6a 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -29,6 +29,23 @@
29static struct mxc_gpio_port *mxc_gpio_ports; 29static struct mxc_gpio_port *mxc_gpio_ports;
30static int gpio_table_size; 30static int gpio_table_size;
31 31
32#define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2())
33
34#define GPIO_DR (cpu_is_mx1_mx2() ? 0x1c : 0x00)
35#define GPIO_GDIR (cpu_is_mx1_mx2() ? 0x00 : 0x04)
36#define GPIO_PSR (cpu_is_mx1_mx2() ? 0x24 : 0x08)
37#define GPIO_ICR1 (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
38#define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10)
39#define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14)
40#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
41#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
42
43#define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0)
44#define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1)
45#define GPIO_INT_RISE_EDGE (cpu_is_mx1_mx2() ? 0x0 : 0x2)
46#define GPIO_INT_FALL_EDGE (cpu_is_mx1_mx2() ? 0x1 : 0x3)
47#define GPIO_INT_NONE 0x4
48
32/* Note: This driver assumes 32 GPIOs are handled in one register */ 49/* Note: This driver assumes 32 GPIOs are handled in one register */
33 50
34static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index) 51static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
@@ -162,7 +179,6 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
162 } 179 }
163} 180}
164 181
165#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
166/* MX1 and MX3 has one interrupt *per* gpio port */ 182/* MX1 and MX3 has one interrupt *per* gpio port */
167static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) 183static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
168{ 184{
@@ -174,9 +190,7 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
174 190
175 mxc_gpio_irq_handler(port, irq_stat); 191 mxc_gpio_irq_handler(port, irq_stat);
176} 192}
177#endif
178 193
179#ifdef CONFIG_ARCH_MX2
180/* MX2 has one interrupt *for all* gpio ports */ 194/* MX2 has one interrupt *for all* gpio ports */
181static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) 195static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
182{ 196{
@@ -195,7 +209,6 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
195 mxc_gpio_irq_handler(&port[i], irq_stat); 209 mxc_gpio_irq_handler(&port[i], irq_stat);
196 } 210 }
197} 211}
198#endif
199 212
200static struct irq_chip gpio_irq_chip = { 213static struct irq_chip gpio_irq_chip = {
201 .ack = gpio_ack_irq, 214 .ack = gpio_ack_irq,
@@ -284,17 +297,18 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
284 /* its a serious configuration bug when it fails */ 297 /* its a serious configuration bug when it fails */
285 BUG_ON( gpiochip_add(&port[i].chip) < 0 ); 298 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
286 299
287#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1) 300 if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25()) {
288 /* setup one handler for each entry */ 301 /* setup one handler for each entry */
289 set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); 302 set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
290 set_irq_data(port[i].irq, &port[i]); 303 set_irq_data(port[i].irq, &port[i]);
291#endif 304 }
305 }
306
307 if (cpu_is_mx2()) {
308 /* setup one handler for all GPIO interrupts */
309 set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
310 set_irq_data(port[0].irq, port);
292 } 311 }
293 312
294#ifdef CONFIG_ARCH_MX2
295 /* setup one handler for all GPIO interrupts */
296 set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
297 set_irq_data(port[0].irq, port);
298#endif
299 return 0; 313 return 0;
300} 314}
diff --git a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
index 8769e910e559..0376c133c9f4 100644
--- a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
+++ b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
@@ -12,11 +12,4 @@
12#ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__ 12#ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
13#define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__ 13#define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
14 14
15#include <mach/hardware.h>
16
17/* mandatory for CONFIG_DEBUG_LL */
18
19#define MXC_LL_UART_PADDR UART1_BASE_ADDR
20#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
21
22#endif 15#endif
diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
new file mode 100644
index 000000000000..a1fd5830af48
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
@@ -0,0 +1,40 @@
1/*
2 * Copyright (C) 2009 Eric Benard - eric@eukrea.com
3 *
4 * Based on board-pcm038.h which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__
23#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__
24
25#ifndef __ASSEMBLY__
26/*
27 * This CPU module needs a baseboard to work. After basic initializing
28 * its own devices, it calls baseboard's init function.
29 * TODO: Add your own baseboard init function and call it from
30 * inside eukrea_cpuimx27_init().
31 *
32 * This example here is for the development board. Refer
33 * eukrea_mbimx27-baseboard.c
34 */
35
36extern void eukrea_mbimx27_baseboard_init(void);
37
38#endif
39
40#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx21ads.h b/arch/arm/plat-mxc/include/mach/board-mx21ads.h
index 06701df74c42..0cf4fa29510c 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx21ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx21ads.h
@@ -15,12 +15,6 @@
15#define __ASM_ARCH_MXC_BOARD_MX21ADS_H__ 15#define __ASM_ARCH_MXC_BOARD_MX21ADS_H__
16 16
17/* 17/*
18 * MXC UART EVB board level configurations
19 */
20#define MXC_LL_UART_PADDR UART1_BASE_ADDR
21#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
22
23/*
24 * Memory-mapped I/O on MX21ADS base board 18 * Memory-mapped I/O on MX21ADS base board
25 */ 19 */
26#define MX21ADS_MMIO_BASE_ADDR 0xF5000000 20#define MX21ADS_MMIO_BASE_ADDR 0xF5000000
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
index d42f4e6116f8..7776d230327f 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
@@ -26,12 +26,6 @@
26 MXC_MAX_VIRTUAL_INTS) 26 MXC_MAX_VIRTUAL_INTS)
27 27
28/* 28/*
29 * MXC UART EVB board level configurations
30 */
31#define MXC_LL_UART_PADDR UART1_BASE_ADDR
32#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
33
34/*
35 * @name Memory Size parameters 29 * @name Memory Size parameters
36 */ 30 */
37 31
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27lite.h b/arch/arm/plat-mxc/include/mach/board-mx27lite.h
index a870f8ea2443..ea87551d2736 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx27lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx27lite.h
@@ -11,9 +11,4 @@
11#ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__ 11#ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__
12#define __ASM_ARCH_MXC_BOARD_MX27LITE_H__ 12#define __ASM_ARCH_MXC_BOARD_MX27LITE_H__
13 13
14/* mandatory for CONFIG_DEBUG_LL */
15
16#define MXC_LL_UART_PADDR UART1_BASE_ADDR
17#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
18
19#endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */ 14#endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
index 552b55d714d8..fec1bcfa9164 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
@@ -11,9 +11,4 @@
11#ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__ 11#ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__
12#define __ASM_ARCH_MXC_BOARD_MX27PDK_H__ 12#define __ASM_ARCH_MXC_BOARD_MX27PDK_H__
13 13
14/* mandatory for CONFIG_DEBUG_LL */
15
16#define MXC_LL_UART_PADDR UART1_BASE_ADDR
17#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
18
19#endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */ 14#endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
index 06e6895f7f65..2cbfa35e82ff 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -114,9 +114,4 @@
114 114
115#define MXC_MAX_EXP_IO_LINES 16 115#define MXC_MAX_EXP_IO_LINES 16
116 116
117/* mandatory for CONFIG_DEBUG_LL */
118
119#define MXC_LL_UART_PADDR UART1_BASE_ADDR
120#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
121
122#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ 117#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
index 78cf31e22e4d..eb5a5024622e 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
@@ -22,11 +22,6 @@
22#ifndef __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ 22#ifndef __ASM_ARCH_MXC_BOARD_MX31LILLY_H__
23#define __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ 23#define __ASM_ARCH_MXC_BOARD_MX31LILLY_H__
24 24
25/* mandatory for CONFIG_LL_DEBUG */
26
27#define MXC_LL_UART_PADDR UART1_BASE_ADDR
28#define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000)
29
30#ifndef __ASSEMBLY__ 25#ifndef __ASSEMBLY__
31 26
32enum mx31lilly_boards { 27enum mx31lilly_boards {
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index 52fbdf2d6f26..8e64325d6905 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -11,8 +11,5 @@
11#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__ 11#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
12#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__ 12#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
13 13
14#define MXC_LL_UART_PADDR UART1_BASE_ADDR
15#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
16
17#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */ 14#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */
18 15
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
index 303fd2434a21..d5be6b5a6acf 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -19,11 +19,6 @@
19#ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ 19#ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
20#define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ 20#define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
21 21
22/* mandatory for CONFIG_DEBUG_LL */
23
24#define MXC_LL_UART_PADDR UART1_BASE_ADDR
25#define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000)
26
27#ifndef __ASSEMBLY__ 22#ifndef __ASSEMBLY__
28 23
29enum mx31moboard_boards { 24enum mx31moboard_boards {
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
index 519bab3eb28b..2bbd6ed17f50 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
@@ -11,11 +11,6 @@
11#ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__ 11#ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__
12#define __ASM_ARCH_MXC_BOARD_MX31PDK_H__ 12#define __ASM_ARCH_MXC_BOARD_MX31PDK_H__
13 13
14/* mandatory for CONFIG_DEBUG_LL */
15
16#define MXC_LL_UART_PADDR UART1_BASE_ADDR
17#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
18
19/* Definitions for components on the Debug board */ 14/* Definitions for components on the Debug board */
20 15
21/* Base address of CPLD controller on the Debug board */ 16/* Base address of CPLD controller on the Debug board */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
index 1111037d6d9d..383f1c04df06 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
@@ -19,9 +19,4 @@
19#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__ 19#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__
20#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__ 20#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__
21 21
22/* mandatory for CONFIG_DEBUG_LL */
23
24#define MXC_LL_UART_PADDR UART1_BASE_ADDR
25#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
26
27#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */ 22#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm037.h b/arch/arm/plat-mxc/include/mach/board-pcm037.h
index f0a1fa1938a2..13411709b13a 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm037.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm037.h
@@ -19,9 +19,4 @@
19#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__ 19#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
20#define __ASM_ARCH_MXC_BOARD_PCM037_H__ 20#define __ASM_ARCH_MXC_BOARD_PCM037_H__
21 21
22/* mandatory for CONFIG_DEBUG_LL */
23
24#define MXC_LL_UART_PADDR UART1_BASE_ADDR
25#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
26
27#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */ 22#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h
index 4fcd7499e092..410f9786ed22 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm038.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h
@@ -19,11 +19,6 @@
19#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__ 19#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
20#define __ASM_ARCH_MXC_BOARD_PCM038_H__ 20#define __ASM_ARCH_MXC_BOARD_PCM038_H__
21 21
22/* mandatory for CONFIG_DEBUG_LL */
23
24#define MXC_LL_UART_PADDR UART1_BASE_ADDR
25#define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000)
26
27#ifndef __ASSEMBLY__ 22#ifndef __ASSEMBLY__
28/* 23/*
29 * This CPU module needs a baseboard to work. After basic initializing 24 * This CPU module needs a baseboard to work. After basic initializing
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm043.h b/arch/arm/plat-mxc/include/mach/board-pcm043.h
index 15fbdf16abcd..1ac4e1682e5c 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm043.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm043.h
@@ -19,9 +19,4 @@
19#ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__ 19#ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__
20#define __ASM_ARCH_MXC_BOARD_PCM043_H__ 20#define __ASM_ARCH_MXC_BOARD_PCM043_H__
21 21
22/* mandatory for CONFIG_LL_DEBUG */
23
24#define MXC_LL_UART_PADDR UART1_BASE_ADDR
25#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
26
27#endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */ 22#endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h
index 04033ec637d2..6d88c7af4b23 100644
--- a/arch/arm/plat-mxc/include/mach/board-qong.h
+++ b/arch/arm/plat-mxc/include/mach/board-qong.h
@@ -11,11 +11,6 @@
11#ifndef __ASM_ARCH_MXC_BOARD_QONG_H__ 11#ifndef __ASM_ARCH_MXC_BOARD_QONG_H__
12#define __ASM_ARCH_MXC_BOARD_QONG_H__ 12#define __ASM_ARCH_MXC_BOARD_QONG_H__
13 13
14/* mandatory for CONFIG_DEBUG_LL */
15
16#define MXC_LL_UART_PADDR UART1_BASE_ADDR
17#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
18
19/* NOR FLASH */ 14/* NOR FLASH */
20#define QONG_NOR_SIZE (128*1024*1024) 15#define QONG_NOR_SIZE (128*1024*1024)
21 16
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 02c3cd004db3..286cb9b0a25b 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -16,18 +16,33 @@ struct clk;
16 16
17extern void mx1_map_io(void); 17extern void mx1_map_io(void);
18extern void mx21_map_io(void); 18extern void mx21_map_io(void);
19extern void mx25_map_io(void);
19extern void mx27_map_io(void); 20extern void mx27_map_io(void);
20extern void mx31_map_io(void); 21extern void mx31_map_io(void);
21extern void mx35_map_io(void); 22extern void mx35_map_io(void);
22extern void mxc_init_irq(void); 23extern void mxc91231_map_io(void);
23extern void mxc_timer_init(struct clk *timer_clk); 24extern void mxc_init_irq(void __iomem *);
25extern void mx1_init_irq(void);
26extern void mx21_init_irq(void);
27extern void mx25_init_irq(void);
28extern void mx27_init_irq(void);
29extern void mx31_init_irq(void);
30extern void mx35_init_irq(void);
31extern void mxc91231_init_irq(void);
32extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
24extern int mx1_clocks_init(unsigned long fref); 33extern int mx1_clocks_init(unsigned long fref);
25extern int mx21_clocks_init(unsigned long lref, unsigned long fref); 34extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
35extern int mx25_clocks_init(unsigned long fref);
26extern int mx27_clocks_init(unsigned long fref); 36extern int mx27_clocks_init(unsigned long fref);
27extern int mx31_clocks_init(unsigned long fref); 37extern int mx31_clocks_init(unsigned long fref);
28extern int mx35_clocks_init(void); 38extern int mx35_clocks_init(void);
39extern int mxc91231_clocks_init(unsigned long fref);
29extern int mxc_register_gpios(void); 40extern int mxc_register_gpios(void);
30extern int mxc_register_device(struct platform_device *pdev, void *data); 41extern int mxc_register_device(struct platform_device *pdev, void *data);
31extern void mxc_set_cpu_type(unsigned int type); 42extern void mxc_set_cpu_type(unsigned int type);
43extern void mxc_arch_reset_init(void __iomem *);
44extern void mxc91231_power_off(void);
45extern void mxc91231_arch_reset(int, const char *);
46extern void mxc91231_prepare_idle(void);
32 47
33#endif 48#endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index bbc5f6753cfb..15b2b148a105 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -11,52 +11,52 @@
11 * 11 *
12 */ 12 */
13 13
14#include <mach/hardware.h> 14#ifdef CONFIG_ARCH_MX1
15 15#include <mach/mx1.h>
16#ifdef CONFIG_MACH_MX31ADS 16#define UART_PADDR UART1_BASE_ADDR
17#include <mach/board-mx31ads.h> 17#define UART_VADDR IO_ADDRESS(UART1_BASE_ADDR)
18#endif
19#ifdef CONFIG_MACH_PCM037
20#include <mach/board-pcm037.h>
21#endif
22#ifdef CONFIG_MACH_MX31LITE
23#include <mach/board-mx31lite.h>
24#endif
25#ifdef CONFIG_MACH_MX27ADS
26#include <mach/board-mx27ads.h>
27#endif
28#ifdef CONFIG_MACH_MX21ADS
29#include <mach/board-mx21ads.h>
30#endif 18#endif
31#ifdef CONFIG_MACH_PCM038 19
32#include <mach/board-pcm038.h> 20#ifdef CONFIG_ARCH_MX25
21#ifdef UART_PADDR
22#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
33#endif 23#endif
34#ifdef CONFIG_MACH_MX31_3DS 24#include <mach/mx25.h>
35#include <mach/board-mx31pdk.h> 25#define UART_PADDR UART1_BASE_ADDR
26#define UART_VADDR MX25_AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
36#endif 27#endif
37#ifdef CONFIG_MACH_QONG 28
38#include <mach/board-qong.h> 29#ifdef CONFIG_ARCH_MX2
30#ifdef UART_PADDR
31#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
39#endif 32#endif
40#ifdef CONFIG_MACH_PCM043 33#include <mach/mx2x.h>
41#include <mach/board-pcm043.h> 34#define UART_PADDR UART1_BASE_ADDR
35#define UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
42#endif 36#endif
43#ifdef CONFIG_MACH_MX27_3DS 37
44#include <mach/board-mx27pdk.h> 38#ifdef CONFIG_ARCH_MX3
39#ifdef UART_PADDR
40#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
45#endif 41#endif
46#ifdef CONFIG_MACH_ARMADILLO5X0 42#include <mach/mx3x.h>
47#include <mach/board-armadillo5x0.h> 43#define UART_PADDR UART1_BASE_ADDR
44#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
48#endif 45#endif
49#ifdef CONFIG_MACH_MX35_3DS 46
50#include <mach/board-mx35pdk.h> 47#ifdef CONFIG_ARCH_MXC91231
48#ifdef UART_PADDR
49#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
51#endif 50#endif
52#ifdef CONFIG_MACH_MX27LITE 51#include <mach/mxc91231.h>
53#include <mach/board-mx27lite.h> 52#define UART_PADDR MXC91231_UART2_BASE_ADDR
53#define UART_VADDR MXC91231_AIPS1_IO_ADDRESS(MXC91231_UART2_BASE_ADDR)
54#endif 54#endif
55 .macro addruart,rx 55 .macro addruart,rx
56 mrc p15, 0, \rx, c1, c0 56 mrc p15, 0, \rx, c1, c0
57 tst \rx, #1 @ MMU enabled? 57 tst \rx, #1 @ MMU enabled?
58 ldreq \rx, =MXC_LL_UART_PADDR @ physical 58 ldreq \rx, =UART_PADDR @ physical
59 ldrne \rx, =MXC_LL_UART_VADDR @ virtual 59 ldrne \rx, =UART_VADDR @ virtual
60 .endm 60 .endm
61 61
62 .macro senduart,rd,rx 62 .macro senduart,rd,rx
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index 5f01d60da845..7cf290efe768 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -18,7 +18,8 @@
18 .endm 18 .endm
19 19
20 .macro get_irqnr_preamble, base, tmp 20 .macro get_irqnr_preamble, base, tmp
21 ldr \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR) 21 ldr \base, =avic_base
22 ldr \base, [\base]
22#ifdef CONFIG_MXC_IRQ_PRIOR 23#ifdef CONFIG_MXC_IRQ_PRIOR
23 ldr r4, [\base, #AVIC_NIMASK] 24 ldr r4, [\base, #AVIC_NIMASK]
24#endif 25#endif
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 42e4ee37ca1f..78db75475f69 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -42,6 +42,14 @@
42# include <mach/mx1.h> 42# include <mach/mx1.h>
43#endif 43#endif
44 44
45#ifdef CONFIG_ARCH_MX25
46# include <mach/mx25.h>
47#endif
48
49#ifdef CONFIG_ARCH_MXC91231
50# include <mach/mxc91231.h>
51#endif
52
45#include <mach/mxc.h> 53#include <mach/mxc.h>
46 54
47#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ 55#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h
index 9f0101157ec1..5263506b7ddf 100644
--- a/arch/arm/plat-mxc/include/mach/imxfb.h
+++ b/arch/arm/plat-mxc/include/mach/imxfb.h
@@ -2,6 +2,8 @@
2 * This structure describes the machine which we are running on. 2 * This structure describes the machine which we are running on.
3 */ 3 */
4 4
5#include <linux/fb.h>
6
5#define PCR_TFT (1 << 31) 7#define PCR_TFT (1 << 31)
6#define PCR_COLOR (1 << 30) 8#define PCR_COLOR (1 << 30)
7#define PCR_PBSIZ_1 (0 << 28) 9#define PCR_PBSIZ_1 (0 << 28)
@@ -13,7 +15,8 @@
13#define PCR_BPIX_4 (2 << 25) 15#define PCR_BPIX_4 (2 << 25)
14#define PCR_BPIX_8 (3 << 25) 16#define PCR_BPIX_8 (3 << 25)
15#define PCR_BPIX_12 (4 << 25) 17#define PCR_BPIX_12 (4 << 25)
16#define PCR_BPIX_16 (4 << 25) 18#define PCR_BPIX_16 (5 << 25)
19#define PCR_BPIX_18 (6 << 25)
17#define PCR_PIXPOL (1 << 24) 20#define PCR_PIXPOL (1 << 24)
18#define PCR_FLMPOL (1 << 23) 21#define PCR_FLMPOL (1 << 23)
19#define PCR_LPPOL (1 << 22) 22#define PCR_LPPOL (1 << 22)
@@ -46,29 +49,21 @@
46#define DMACR_HM(x) (((x) & 0xf) << 16) 49#define DMACR_HM(x) (((x) & 0xf) << 16)
47#define DMACR_TM(x) ((x) & 0xf) 50#define DMACR_TM(x) ((x) & 0xf)
48 51
49struct imx_fb_platform_data { 52struct imx_fb_videomode {
50 u_long pixclock; 53 struct fb_videomode mode;
51 54 u32 pcr;
52 u_short xres; 55 unsigned char bpp;
53 u_short yres; 56};
54
55 u_int nonstd;
56 u_char bpp;
57 u_char hsync_len;
58 u_char left_margin;
59 u_char right_margin;
60 57
61 u_char vsync_len; 58struct imx_fb_platform_data {
62 u_char upper_margin; 59 struct imx_fb_videomode *mode;
63 u_char lower_margin; 60 int num_modes;
64 u_char sync;
65 61
66 u_int cmap_greyscale:1, 62 u_int cmap_greyscale:1,
67 cmap_inverse:1, 63 cmap_inverse:1,
68 cmap_static:1, 64 cmap_static:1,
69 unused:29; 65 unused:29;
70 66
71 u_int pcr;
72 u_int pwmr; 67 u_int pwmr;
73 u_int lscr1; 68 u_int lscr1;
74 u_int dmacr; 69 u_int dmacr;
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
new file mode 100644
index 000000000000..810c47f56e77
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -0,0 +1,517 @@
1/*
2 * arch/arm/plat-mxc/include/mach/iomux-mx25.h
3 *
4 * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
5 *
6 * based on arch/arm/mach-mx25/mx25_pins.h
7 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
8 * and
9 * arch/arm/plat-mxc/include/mach/iomux-mx35.h
10 * Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
11 *
12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License
14 * Version 2 or later at the following locations:
15 *
16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html
18 */
19#ifndef __IOMUX_MX25_H__
20#define __IOMUX_MX25_H__
21
22#include <mach/iomux-v3.h>
23
24#ifndef GPIO_PORTA
25#error Please include mach/iomux.h
26#endif
27
28/*
29 *
30 * @brief MX25 I/O Pin List
31 *
32 * @ingroup GPIO_MX25
33 */
34
35#ifndef __ASSEMBLY__
36
37/*
38 * IOMUX/PAD Bit field definitions
39 */
40
41#define MX25_PAD_A10__A10 IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL)
42#define MX25_PAD_A10__GPIO_4_0 IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL)
43
44#define MX25_PAD_A13__A13 IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL)
45#define MX25_PAD_A13__GPIO_4_1 IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL)
46
47#define MX25_PAD_A14__A14 IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL)
48#define MX25_PAD_A14__GPIO_2_0 IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL)
49
50#define MX25_PAD_A15__A15 IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL)
51#define MX25_PAD_A15__GPIO_2_1 IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL)
52
53#define MX25_PAD_A16__A16 IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL)
54#define MX25_PAD_A16__GPIO_2_2 IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL)
55
56#define MX25_PAD_A17__A17 IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL)
57#define MX25_PAD_A17__GPIO_2_3 IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL)
58
59#define MX25_PAD_A18__A18 IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL)
60#define MX25_PAD_A18__GPIO_2_4 IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL)
61#define MX25_PAD_A18__FEC_COL IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTL)
62
63#define MX25_PAD_A19__A19 IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL)
64#define MX25_PAD_A19__FEC_RX_ER IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTL)
65#define MX25_PAD_A19__GPIO_2_5 IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL)
66
67#define MX25_PAD_A20__A20 IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL)
68#define MX25_PAD_A20__GPIO_2_6 IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL)
69#define MX25_PAD_A20__FEC_RDATA2 IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTL)
70
71#define MX25_PAD_A21__A21 IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL)
72#define MX25_PAD_A21__GPIO_2_7 IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL)
73#define MX25_PAD_A21__FEC_RDATA3 IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTL)
74
75#define MX25_PAD_A22__A22 IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL)
76#define MX25_PAD_A22__GPIO_2_8 IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL)
77
78#define MX25_PAD_A23__A23 IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL)
79#define MX25_PAD_A23__GPIO_2_9 IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL)
80
81#define MX25_PAD_A24__A24 IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL)
82#define MX25_PAD_A24__GPIO_2_10 IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL)
83#define MX25_PAD_A24__FEC_RX_CLK IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTL)
84
85#define MX25_PAD_A25__A25 IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL)
86#define MX25_PAD_A25__GPIO_2_11 IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL)
87#define MX25_PAD_A25__FEC_CRS IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTL)
88
89#define MX25_PAD_EB0__EB0 IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL)
90#define MX25_PAD_EB0__AUD4_TXD IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL)
91#define MX25_PAD_EB0__GPIO_2_12 IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL)
92
93#define MX25_PAD_EB1__EB1 IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL)
94#define MX25_PAD_EB1__AUD4_RXD IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL)
95#define MX25_PAD_EB1__GPIO_2_13 IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL)
96
97#define MX25_PAD_OE__OE IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL)
98#define MX25_PAD_OE__AUD4_TXC IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL)
99#define MX25_PAD_OE__GPIO_2_14 IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL)
100
101#define MX25_PAD_CS0__CS0 IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL)
102#define MX25_PAD_CS0__GPIO_4_2 IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL)
103
104#define MX25_PAD_CS1__CS1 IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL)
105#define MX25_PAD_CS1__GPIO_4_3 IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL)
106
107#define MX25_PAD_CS4__CS4 IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL)
108#define MX25_PAD_CS4__UART5_CTS IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL)
109#define MX25_PAD_CS4__GPIO_3_20 IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL)
110
111#define MX25_PAD_CS5__CS5 IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL)
112#define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL)
113#define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL)
114
115#define MX25_PAD_NF_CE0__NF_CE0 IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTL)
116#define MX25_PAD_NF_CE0__GPIO_3_22 IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL)
117
118#define MX25_PAD_ECB__ECB IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL)
119#define MX25_PAD_ECB__UART5_TXD_MUX IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL)
120#define MX25_PAD_ECB__GPIO_3_23 IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL)
121
122#define MX25_PAD_LBA__LBA IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL)
123#define MX25_PAD_LBA__UART5_RXD_MUX IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL)
124#define MX25_PAD_LBA__GPIO_3_24 IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL)
125
126#define MX25_PAD_BCLK__BCLK IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL)
127#define MX25_PAD_BCLK__GPIO_4_4 IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL)
128
129#define MX25_PAD_RW__RW IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL)
130#define MX25_PAD_RW__AUD4_TXFS IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL)
131#define MX25_PAD_RW__GPIO_3_25 IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL)
132
133#define MX25_PAD_NFWE_B__NFWE_B IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL)
134#define MX25_PAD_NFWE_B__GPIO_3_26 IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL)
135
136#define MX25_PAD_NFRE_B__NFRE_B IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL)
137#define MX25_PAD_NFRE_B__GPIO_3_27 IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL)
138
139#define MX25_PAD_NFALE__NFALE IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL)
140#define MX25_PAD_NFALE__GPIO_3_28 IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL)
141
142#define MX25_PAD_NFCLE__NFCLE IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL)
143#define MX25_PAD_NFCLE__GPIO_3_29 IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL)
144
145#define MX25_PAD_NFWP_B__NFWP_B IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL)
146#define MX25_PAD_NFWP_B__GPIO_3_30 IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL)
147
148#define MX25_PAD_NFRB__NFRB IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE)
149#define MX25_PAD_NFRB__GPIO_3_31 IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL)
150
151#define MX25_PAD_D15__D15 IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
152#define MX25_PAD_D15__LD16 IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, NO_PAD_CTRL)
153#define MX25_PAD_D15__GPIO_4_5 IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
154
155#define MX25_PAD_D14__D14 IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
156#define MX25_PAD_D14__LD17 IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, NO_PAD_CTRL)
157#define MX25_PAD_D14__GPIO_4_6 IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
158
159#define MX25_PAD_D13__D13 IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
160#define MX25_PAD_D13__LD18 IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, NO_PAD_CTRL)
161#define MX25_PAD_D13__GPIO_4_7 IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
162
163#define MX25_PAD_D12__D12 IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
164#define MX25_PAD_D12__GPIO_4_8 IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL)
165
166#define MX25_PAD_D11__D11 IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL)
167#define MX25_PAD_D11__GPIO_4_9 IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL)
168
169#define MX25_PAD_D10__D10 IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL)
170#define MX25_PAD_D10__GPIO_4_10 IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL)
171#define MX25_PAD_D10__USBOTG_OC IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP)
172
173#define MX25_PAD_D9__D9 IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL)
174#define MX25_PAD_D9__GPIO_4_11 IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL)
175#define MX25_PAD_D9__USBH2_PWR IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE)
176
177#define MX25_PAD_D8__D8 IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL)
178#define MX25_PAD_D8__GPIO_4_12 IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL)
179#define MX25_PAD_D8__USBH2_OC IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP)
180
181#define MX25_PAD_D7__D7 IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL)
182#define MX25_PAD_D7__GPIO_4_13 IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL)
183
184#define MX25_PAD_D6__D6 IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL)
185#define MX25_PAD_D6__GPIO_4_14 IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL)
186
187#define MX25_PAD_D5__D5 IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL)
188#define MX25_PAD_D5__GPIO_4_15 IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL)
189
190#define MX25_PAD_D4__D4 IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL)
191#define MX25_PAD_D4__GPIO_4_16 IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL)
192
193#define MX25_PAD_D3__D3 IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL)
194#define MX25_PAD_D3__GPIO_4_17 IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL)
195
196#define MX25_PAD_D2__D2 IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL)
197#define MX25_PAD_D2__GPIO_4_18 IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL)
198
199#define MX25_PAD_D1__D1 IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL)
200#define MX25_PAD_D1__GPIO_4_19 IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL)
201
202#define MX25_PAD_D0__D0 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
203#define MX25_PAD_D0__GPIO_4_20 IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
204
205#define MX25_PAD_LD0__LD0 IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, NO_PAD_CTRL)
206#define MX25_PAD_LD0__CSI_D0 IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL)
207#define MX25_PAD_LD0__GPIO_2_15 IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL)
208
209#define MX25_PAD_LD1__LD1 IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, NO_PAD_CTRL)
210#define MX25_PAD_LD1__CSI_D1 IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL)
211#define MX25_PAD_LD1__GPIO_2_16 IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL)
212
213#define MX25_PAD_LD2__LD2 IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, NO_PAD_CTRL)
214#define MX25_PAD_LD2__GPIO_2_17 IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL)
215
216#define MX25_PAD_LD3__LD3 IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, NO_PAD_CTRL)
217#define MX25_PAD_LD3__GPIO_2_18 IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL)
218
219#define MX25_PAD_LD4__LD4 IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, NO_PAD_CTRL)
220#define MX25_PAD_LD4__GPIO_2_19 IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL)
221
222#define MX25_PAD_LD5__LD5 IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, NO_PAD_CTRL)
223#define MX25_PAD_LD5__GPIO_1_19 IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL)
224
225#define MX25_PAD_LD6__LD6 IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, NO_PAD_CTRL)
226#define MX25_PAD_LD6__GPIO_1_20 IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL)
227
228#define MX25_PAD_LD7__LD7 IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, NO_PAD_CTRL)
229#define MX25_PAD_LD7__GPIO_1_21 IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
230
231#define MX25_PAD_LD8__LD8 IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL)
232#define MX25_PAD_LD8__FEC_TX_ERR IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTL)
233
234#define MX25_PAD_LD9__LD9 IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL)
235#define MX25_PAD_LD9__FEC_COL IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTL)
236
237#define MX25_PAD_LD10__LD10 IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL)
238#define MX25_PAD_LD10__FEC_RX_ER IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTL)
239
240#define MX25_PAD_LD11__LD11 IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL)
241#define MX25_PAD_LD11__FEC_RDATA2 IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTL)
242
243#define MX25_PAD_LD12__LD12 IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL)
244#define MX25_PAD_LD12__FEC_RDATA3 IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTL)
245
246#define MX25_PAD_LD13__LD13 IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL)
247#define MX25_PAD_LD13__FEC_TDATA2 IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTL)
248
249#define MX25_PAD_LD14__LD14 IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL)
250#define MX25_PAD_LD14__FEC_TDATA3 IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTL)
251
252#define MX25_PAD_LD15__LD15 IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL)
253#define MX25_PAD_LD15__FEC_RX_CLK IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTL)
254
255#define MX25_PAD_HSYNC__HSYNC IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
256#define MX25_PAD_HSYNC__GPIO_1_22 IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL)
257
258#define MX25_PAD_VSYNC__VSYNC IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL)
259#define MX25_PAD_VSYNC__GPIO_1_23 IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL)
260
261#define MX25_PAD_LSCLK__LSCLK IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL)
262#define MX25_PAD_LSCLK__GPIO_1_24 IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL)
263
264#define MX25_PAD_OE_ACD__OE_ACD IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL)
265#define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
266
267#define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
268#define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTL)
269
270#define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
271#define MX25_PAD_PWM__GPIO_1_26 IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL)
272#define MX25_PAD_PWM__USBH2_OC IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP)
273
274#define MX25_PAD_CSI_D2__CSI_D2 IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL)
275#define MX25_PAD_CSI_D2__UART5_RXD_MUX IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL)
276#define MX25_PAD_CSI_D2__GPIO_1_27 IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL)
277
278#define MX25_PAD_CSI_D3__CSI_D3 IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL)
279#define MX25_PAD_CSI_D3__GPIO_1_28 IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL)
280
281#define MX25_PAD_CSI_D4__CSI_D4 IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL)
282#define MX25_PAD_CSI_D4__UART5_RTS IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL)
283#define MX25_PAD_CSI_D4__GPIO_1_29 IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL)
284
285#define MX25_PAD_CSI_D5__CSI_D5 IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL)
286#define MX25_PAD_CSI_D5__GPIO_1_30 IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL)
287
288#define MX25_PAD_CSI_D6__CSI_D6 IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL)
289#define MX25_PAD_CSI_D6__GPIO_1_31 IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL)
290
291#define MX25_PAD_CSI_D7__CSI_D7 IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL)
292#define MX25_PAD_CSI_D7__GPIO_1_6 IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL)
293
294#define MX25_PAD_CSI_D8__CSI_D8 IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL)
295#define MX25_PAD_CSI_D8__GPIO_1_7 IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL)
296
297#define MX25_PAD_CSI_D9__CSI_D9 IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL)
298#define MX25_PAD_CSI_D9__GPIO_4_21 IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL)
299
300#define MX25_PAD_CSI_MCLK__CSI_MCLK IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL)
301#define MX25_PAD_CSI_MCLK__GPIO_1_8 IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL)
302
303#define MX25_PAD_CSI_VSYNC__CSI_VSYNC IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL)
304#define MX25_PAD_CSI_VSYNC__GPIO_1_9 IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL)
305
306#define MX25_PAD_CSI_HSYNC__CSI_HSYNC IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL)
307#define MX25_PAD_CSI_HSYNC__GPIO_1_10 IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL)
308
309#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL)
310#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL)
311
312#define MX25_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL)
313#define MX25_PAD_I2C1_CLK__GPIO_1_12 IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL)
314
315#define MX25_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL)
316#define MX25_PAD_I2C1_DAT__GPIO_1_13 IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL)
317
318#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL)
319#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL)
320
321#define MX25_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL)
322#define MX25_PAD_CSPI1_MISO__GPIO_1_15 IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL)
323
324#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL)
325#define MX25_PAD_CSPI1_SS0__GPIO_1_16 IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL)
326
327#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL)
328#define MX25_PAD_CSPI1_SS1__GPIO_1_17 IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL)
329
330#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL)
331#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL)
332
333#define MX25_PAD_CSPI1_RDY__CSPI1_RDY IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE)
334#define MX25_PAD_CSPI1_RDY__GPIO_2_22 IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL)
335
336#define MX25_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN)
337#define MX25_PAD_UART1_RXD__GPIO_4_22 IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL)
338
339#define MX25_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL)
340#define MX25_PAD_UART1_TXD__GPIO_4_23 IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL)
341
342#define MX25_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
343#define MX25_PAD_UART1_RTS__CSI_D0 IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL)
344#define MX25_PAD_UART1_RTS__GPIO_4_24 IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL)
345
346#define MX25_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
347#define MX25_PAD_UART1_CTS__CSI_D1 IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL)
348#define MX25_PAD_UART1_CTS__GPIO_4_25 IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL)
349
350#define MX25_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL)
351#define MX25_PAD_UART2_RXD__GPIO_4_26 IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL)
352
353#define MX25_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL)
354#define MX25_PAD_UART2_TXD__GPIO_4_27 IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL)
355
356#define MX25_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL)
357#define MX25_PAD_UART2_RTS__FEC_COL IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTL)
358#define MX25_PAD_UART2_RTS__GPIO_4_28 IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL)
359
360#define MX25_PAD_UART2_CTS__FEC_RX_ER IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTL)
361#define MX25_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL)
362#define MX25_PAD_UART2_CTS__GPIO_4_29 IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL)
363
364#define MX25_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
365#define MX25_PAD_SD1_CMD__FEC_RDATA2 IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTL)
366#define MX25_PAD_SD1_CMD__GPIO_2_23 IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL)
367
368#define MX25_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
369#define MX25_PAD_SD1_CLK__FEC_RDATA3 IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTL)
370#define MX25_PAD_SD1_CLK__GPIO_2_24 IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL)
371
372#define MX25_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
373#define MX25_PAD_SD1_DATA0__GPIO_2_25 IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL)
374
375#define MX25_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
376#define MX25_PAD_SD1_DATA1__AUD7_RXD IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL)
377#define MX25_PAD_SD1_DATA1__GPIO_2_26 IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL)
378
379#define MX25_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
380#define MX25_PAD_SD1_DATA2__FEC_RX_CLK IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTL)
381#define MX25_PAD_SD1_DATA2__GPIO_2_27 IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL)
382
383#define MX25_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
384#define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTL)
385#define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
386
387#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, PAD_CTL_PKE)
388#define MX25_PAD_KPP_ROW0__GPIO_2_29 IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL)
389
390#define MX25_PAD_KPP_ROW1__KPP_ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, PAD_CTL_PKE)
391#define MX25_PAD_KPP_ROW1__GPIO_2_30 IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL)
392
393#define MX25_PAD_KPP_ROW2__KPP_ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, PAD_CTL_PKE)
394#define MX25_PAD_KPP_ROW2__CSI_D0 IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL)
395#define MX25_PAD_KPP_ROW2__GPIO_2_31 IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL)
396
397#define MX25_PAD_KPP_ROW3__KPP_ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, PAD_CTL_PKE)
398#define MX25_PAD_KPP_ROW3__CSI_LD1 IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL)
399#define MX25_PAD_KPP_ROW3__GPIO_3_0 IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
400
401#define MX25_PAD_KPP_COL0__KPP_COL0 IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
402#define MX25_PAD_KPP_COL0__GPIO_3_1 IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
403
404#define MX25_PAD_KPP_COL1__KPP_COL1 IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
405#define MX25_PAD_KPP_COL1__GPIO_3_2 IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
406
407#define MX25_PAD_KPP_COL2__KPP_COL2 IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
408#define MX25_PAD_KPP_COL2__GPIO_3_3 IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
409
410#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
411#define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
412
413#define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTL)
414#define MX25_PAD_FEC_MDC__AUD4_TXD IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL)
415#define MX25_PAD_FEC_MDC__GPIO_3_5 IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL)
416
417#define MX25_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP)
418#define MX25_PAD_FEC_MDIO__AUD4_RXD IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL)
419#define MX25_PAD_FEC_MDIO__GPIO_3_6 IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL)
420
421#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTL)
422#define MX25_PAD_FEC_TDATA0__GPIO_3_7 IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL)
423
424#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTL)
425#define MX25_PAD_FEC_TDATA1__AUD4_TXFS IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL)
426#define MX25_PAD_FEC_TDATA1__GPIO_3_8 IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL)
427
428#define MX25_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTL)
429#define MX25_PAD_FEC_TX_EN__GPIO_3_9 IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL)
430
431#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL)
432#define MX25_PAD_FEC_RDATA0__GPIO_3_10 IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL)
433
434#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL)
435#define MX25_PAD_FEC_RDATA1__GPIO_3_11 IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL)
436
437#define MX25_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL)
438#define MX25_PAD_FEC_RX_DV__CAN2_RX IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP)
439#define MX25_PAD_FEC_RX_DV__GPIO_3_12 IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL)
440
441#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN)
442#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL)
443
444#define MX25_PAD_RTCK__RTCK IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL)
445#define MX25_PAD_RTCK__OWIRE IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL)
446#define MX25_PAD_RTCK__GPIO_3_14 IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL)
447
448#define MX25_PAD_DE_B__DE_B IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL)
449#define MX25_PAD_DE_B__GPIO_2_20 IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL)
450
451#define MX25_PAD_TDO__TDO IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL)
452
453#define MX25_PAD_GPIO_A__GPIO_A IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL)
454#define MX25_PAD_GPIO_A__CAN1_TX IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
455#define MX25_PAD_GPIO_A__USBOTG_PWR IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE)
456
457#define MX25_PAD_GPIO_B__GPIO_B IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL)
458#define MX25_PAD_GPIO_B__CAN1_RX IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K)
459#define MX25_PAD_GPIO_B__USBOTG_OC IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP)
460
461#define MX25_PAD_GPIO_C__GPIO_C IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL)
462#define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
463
464#define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
465#define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
466
467#define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
468#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
469
470#define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
471#define MX25_PAD_GPIO_F__AUD7_TXC IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL)
472
473#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL)
474#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL)
475
476#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL)
477#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL)
478
479#define MX25_PAD_VSTBY_REQ__VSTBY_REQ IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL)
480#define MX25_PAD_VSTBY_REQ__AUD7_TXFS IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL)
481#define MX25_PAD_VSTBY_REQ__GPIO_3_17 IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL)
482#define MX25_PAD_VSTBY_ACK__VSTBY_ACK IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL)
483#define MX25_PAD_VSTBY_ACK__GPIO_3_18 IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL)
484
485#define MX25_PAD_POWER_FAIL__POWER_FAIL IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL)
486#define MX25_PAD_POWER_FAIL__AUD7_RXD IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL)
487#define MX25_PAD_POWER_FAIL__GPIO_3_19 IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL)
488
489#define MX25_PAD_CLKO__CLKO IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL)
490#define MX25_PAD_CLKO__GPIO_2_21 IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL)
491
492#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL)
493#define MX25_PAD_BOOT_MODE0__GPIO_4_30 IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL)
494#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL)
495#define MX25_PAD_BOOT_MODE1__GPIO_4_31 IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL)
496
497#define MX25_PAD_CTL_GRP_DVS_MISC IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL)
498#define MX25_PAD_CTL_GRP_DSE_FEC IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL)
499#define MX25_PAD_CTL_GRP_DVS_JTAG IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL)
500#define MX25_PAD_CTL_GRP_DSE_NFC IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL)
501#define MX25_PAD_CTL_GRP_DSE_CSI IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL)
502#define MX25_PAD_CTL_GRP_DSE_WEIM IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL)
503#define MX25_PAD_CTL_GRP_DSE_DDR IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL)
504#define MX25_PAD_CTL_GRP_DVS_CRM IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL)
505#define MX25_PAD_CTL_GRP_DSE_KPP IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL)
506#define MX25_PAD_CTL_GRP_DSE_SDHC1 IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL)
507#define MX25_PAD_CTL_GRP_DSE_LCD IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL)
508#define MX25_PAD_CTL_GRP_DSE_UART IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL)
509#define MX25_PAD_CTL_GRP_DVS_NFC IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL)
510#define MX25_PAD_CTL_GRP_DVS_CSI IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL)
511#define MX25_PAD_CTL_GRP_DSE_CSPI1 IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL)
512#define MX25_PAD_CTL_GRP_DDRTYPE IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL)
513#define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL)
514#define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL)
515
516#endif // __ASSEMBLY__
517#endif // __IOMUX_MX25_H__
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index 2eb182f73876..446f86763816 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -635,6 +635,19 @@ enum iomux_pins {
635#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) 635#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC)
636#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) 636#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC)
637#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) 637#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC)
638#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1)
639#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1)
640#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1)
641#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1)
642#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1)
643#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1)
644#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1)
645#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)
646#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)
647#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)
648#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)
649#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)
650#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)
638#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) 651#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
639#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) 652#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
640#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) 653#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
@@ -669,6 +682,18 @@ enum iomux_pins {
669#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) 682#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
670#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) 683#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
671#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) 684#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
685#define MX31_PIN_GPIO1_0__GPIO1_0 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO)
686#define MX31_PIN_SVEN0__GPIO2_0 IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO)
687#define MX31_PIN_STX0__GPIO2_1 IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO)
688#define MX31_PIN_SRX0__GPIO2_2 IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO)
689#define MX31_PIN_SIMPD0__GPIO2_3 IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO)
690#define MX31_PIN_DTR_DCE1__GPIO2_8 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO)
691#define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO)
692#define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO)
693#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO)
694#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO)
695#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO)
696
672 697
673/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 698/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
674 * cspi1_ss1*/ 699 * cspi1_ss1*/
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
new file mode 100644
index 000000000000..9f13061192c8
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
@@ -0,0 +1,287 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 * Copyright (C) 2009 by Dmitriy Taychenachev <dimichxp@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __MACH_IOMUX_MXC91231_H__
22#define __MACH_IOMUX_MXC91231_H__
23
24/*
25 * various IOMUX output functions
26 */
27
28#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */
29#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */
30#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */
31#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */
32#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */
33#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */
34#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */
35#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */
36#define IOMUX_ICONFIG_NONE 0 /* not configured for input */
37#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */
38#define IOMUX_ICONFIG_FUNC 2 /* used as function */
39#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */
40#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */
41
42#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
43#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
44#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
45#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
46
47/*
48 * setups a single pin:
49 * - reserves the pin so that it is not claimed by another driver
50 * - setups the iomux according to the configuration
51 * - if the pin is configured as a GPIO, we claim it throug kernel gpiolib
52 */
53int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label);
54/*
55 * setups mutliple pins
56 * convenient way to call the above function with tables
57 */
58int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
59 const char *label);
60
61/*
62 * releases a single pin:
63 * - make it available for a future use by another driver
64 * - frees the GPIO if the pin was configured as GPIO
65 * - DOES NOT reconfigure the IOMUX in its reset state
66 */
67void mxc_iomux_release_pin(const unsigned int pin_mode);
68/*
69 * releases multiple pins
70 * convenvient way to call the above function with tables
71 */
72void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count);
73
74#define MUX_SIDE_AP (0)
75#define MUX_SIDE_SP (1)
76
77#define MUX_SIDE_SHIFT (26)
78#define MUX_SIDE_MASK (0x1 << MUX_SIDE_SHIFT)
79
80#define MUX_GPIO_PORT_SHIFT (23)
81#define MUX_GPIO_PORT_MASK (0x7 << MUX_GPIO_PORT_SHIFT)
82
83#define MUX_GPIO_PIN_SHIFT (20)
84#define MUX_GPIO_PIN_MASK (0x1f << MUX_GPIO_PIN_SHIFT)
85
86#define MUX_REG_SHIFT (15)
87#define MUX_REG_MASK (0x1f << MUX_REG_SHIFT)
88
89#define MUX_FIELD_SHIFT (13)
90#define MUX_FIELD_MASK (0x3 << MUX_FIELD_SHIFT)
91
92#define MUX_PADGRP_SHIFT (8)
93#define MUX_PADGRP_MASK (0x1f << MUX_PADGRP_SHIFT)
94
95#define MUX_PIN_MASK (0xffffff << 8)
96
97#define GPIO_PORT_MAX (3)
98
99#define IOMUX_PIN(side, gport, gpin, ctlreg, ctlfield, padgrp) \
100 (((side) << MUX_SIDE_SHIFT) | \
101 (gport << MUX_GPIO_PORT_SHIFT) | \
102 ((gpin) << MUX_GPIO_PIN_SHIFT) | \
103 ((ctlreg) << MUX_REG_SHIFT) | \
104 ((ctlfield) << MUX_FIELD_SHIFT) | \
105 ((padgrp) << MUX_PADGRP_SHIFT))
106
107#define MUX_MODE_OUT_SHIFT (4)
108#define MUX_MODE_IN_SHIFT (0)
109#define MUX_MODE_SHIFT (0)
110#define MUX_MODE_MASK (0xff << MUX_MODE_SHIFT)
111
112#define IOMUX_MODE(pin, mode) \
113 (pin | (mode << MUX_MODE_SHIFT))
114
115enum iomux_pins {
116 /* AP Side pins */
117 MXC91231_PIN_AP_CLE = IOMUX_PIN(0, 0, 0, 0, 0, 24),
118 MXC91231_PIN_AP_ALE = IOMUX_PIN(0, 0, 1, 0, 1, 24),
119 MXC91231_PIN_AP_CE_B = IOMUX_PIN(0, 0, 2, 0, 2, 24),
120 MXC91231_PIN_AP_RE_B = IOMUX_PIN(0, 0, 3, 0, 3, 24),
121 MXC91231_PIN_AP_WE_B = IOMUX_PIN(0, 0, 4, 1, 0, 24),
122 MXC91231_PIN_AP_WP_B = IOMUX_PIN(0, 0, 5, 1, 1, 24),
123 MXC91231_PIN_AP_BSY_B = IOMUX_PIN(0, 0, 6, 1, 2, 24),
124 MXC91231_PIN_AP_U1_TXD = IOMUX_PIN(0, 0, 7, 1, 3, 28),
125 MXC91231_PIN_AP_U1_RXD = IOMUX_PIN(0, 0, 8, 2, 0, 28),
126 MXC91231_PIN_AP_U1_RTS_B = IOMUX_PIN(0, 0, 9, 2, 1, 28),
127 MXC91231_PIN_AP_U1_CTS_B = IOMUX_PIN(0, 0, 10, 2, 2, 28),
128 MXC91231_PIN_AP_AD1_TXD = IOMUX_PIN(0, 0, 11, 2, 3, 9),
129 MXC91231_PIN_AP_AD1_RXD = IOMUX_PIN(0, 0, 12, 3, 0, 9),
130 MXC91231_PIN_AP_AD1_TXC = IOMUX_PIN(0, 0, 13, 3, 1, 9),
131 MXC91231_PIN_AP_AD1_TXFS = IOMUX_PIN(0, 0, 14, 3, 2, 9),
132 MXC91231_PIN_AP_AD2_TXD = IOMUX_PIN(0, 0, 15, 3, 3, 9),
133 MXC91231_PIN_AP_AD2_RXD = IOMUX_PIN(0, 0, 16, 4, 0, 9),
134 MXC91231_PIN_AP_AD2_TXC = IOMUX_PIN(0, 0, 17, 4, 1, 9),
135 MXC91231_PIN_AP_AD2_TXFS = IOMUX_PIN(0, 0, 18, 4, 2, 9),
136 MXC91231_PIN_AP_OWDAT = IOMUX_PIN(0, 0, 19, 4, 3, 28),
137 MXC91231_PIN_AP_IPU_LD17 = IOMUX_PIN(0, 0, 20, 5, 0, 28),
138 MXC91231_PIN_AP_IPU_D3_VSYNC = IOMUX_PIN(0, 0, 21, 5, 1, 28),
139 MXC91231_PIN_AP_IPU_D3_HSYNC = IOMUX_PIN(0, 0, 22, 5, 2, 28),
140 MXC91231_PIN_AP_IPU_D3_CLK = IOMUX_PIN(0, 0, 23, 5, 3, 28),
141 MXC91231_PIN_AP_IPU_D3_DRDY = IOMUX_PIN(0, 0, 24, 6, 0, 28),
142 MXC91231_PIN_AP_IPU_D3_CONTR = IOMUX_PIN(0, 0, 25, 6, 1, 28),
143 MXC91231_PIN_AP_IPU_D0_CS = IOMUX_PIN(0, 0, 26, 6, 2, 28),
144 MXC91231_PIN_AP_IPU_LD16 = IOMUX_PIN(0, 0, 27, 6, 3, 28),
145 MXC91231_PIN_AP_IPU_D2_CS = IOMUX_PIN(0, 0, 28, 7, 0, 28),
146 MXC91231_PIN_AP_IPU_PAR_RS = IOMUX_PIN(0, 0, 29, 7, 1, 28),
147 MXC91231_PIN_AP_IPU_D3_PS = IOMUX_PIN(0, 0, 30, 7, 2, 28),
148 MXC91231_PIN_AP_IPU_D3_CLS = IOMUX_PIN(0, 0, 31, 7, 3, 28),
149 MXC91231_PIN_AP_IPU_RD = IOMUX_PIN(0, 1, 0, 8, 0, 28),
150 MXC91231_PIN_AP_IPU_WR = IOMUX_PIN(0, 1, 1, 8, 1, 28),
151 MXC91231_PIN_AP_IPU_LD0 = IOMUX_PIN(0, 7, 0, 8, 2, 28),
152 MXC91231_PIN_AP_IPU_LD1 = IOMUX_PIN(0, 7, 0, 8, 3, 28),
153 MXC91231_PIN_AP_IPU_LD2 = IOMUX_PIN(0, 7, 0, 9, 0, 28),
154 MXC91231_PIN_AP_IPU_LD3 = IOMUX_PIN(0, 1, 2, 9, 1, 28),
155 MXC91231_PIN_AP_IPU_LD4 = IOMUX_PIN(0, 1, 3, 9, 2, 28),
156 MXC91231_PIN_AP_IPU_LD5 = IOMUX_PIN(0, 1, 4, 9, 3, 28),
157 MXC91231_PIN_AP_IPU_LD6 = IOMUX_PIN(0, 1, 5, 10, 0, 28),
158 MXC91231_PIN_AP_IPU_LD7 = IOMUX_PIN(0, 1, 6, 10, 1, 28),
159 MXC91231_PIN_AP_IPU_LD8 = IOMUX_PIN(0, 1, 7, 10, 2, 28),
160 MXC91231_PIN_AP_IPU_LD9 = IOMUX_PIN(0, 1, 8, 10, 3, 28),
161 MXC91231_PIN_AP_IPU_LD10 = IOMUX_PIN(0, 1, 9, 11, 0, 28),
162 MXC91231_PIN_AP_IPU_LD11 = IOMUX_PIN(0, 1, 10, 11, 1, 28),
163 MXC91231_PIN_AP_IPU_LD12 = IOMUX_PIN(0, 1, 11, 11, 2, 28),
164 MXC91231_PIN_AP_IPU_LD13 = IOMUX_PIN(0, 1, 12, 11, 3, 28),
165 MXC91231_PIN_AP_IPU_LD14 = IOMUX_PIN(0, 1, 13, 12, 0, 28),
166 MXC91231_PIN_AP_IPU_LD15 = IOMUX_PIN(0, 1, 14, 12, 1, 28),
167 MXC91231_PIN_AP_KPROW4 = IOMUX_PIN(0, 7, 0, 12, 2, 10),
168 MXC91231_PIN_AP_KPROW5 = IOMUX_PIN(0, 1, 16, 12, 3, 10),
169 MXC91231_PIN_AP_GPIO_AP_B17 = IOMUX_PIN(0, 1, 17, 13, 0, 10),
170 MXC91231_PIN_AP_GPIO_AP_B18 = IOMUX_PIN(0, 1, 18, 13, 1, 10),
171 MXC91231_PIN_AP_KPCOL3 = IOMUX_PIN(0, 1, 19, 13, 2, 11),
172 MXC91231_PIN_AP_KPCOL4 = IOMUX_PIN(0, 1, 20, 13, 3, 11),
173 MXC91231_PIN_AP_KPCOL5 = IOMUX_PIN(0, 1, 21, 14, 0, 11),
174 MXC91231_PIN_AP_GPIO_AP_B22 = IOMUX_PIN(0, 1, 22, 14, 1, 11),
175 MXC91231_PIN_AP_GPIO_AP_B23 = IOMUX_PIN(0, 1, 23, 14, 2, 11),
176 MXC91231_PIN_AP_CSI_D0 = IOMUX_PIN(0, 1, 24, 14, 3, 21),
177 MXC91231_PIN_AP_CSI_D1 = IOMUX_PIN(0, 1, 25, 15, 0, 21),
178 MXC91231_PIN_AP_CSI_D2 = IOMUX_PIN(0, 1, 26, 15, 1, 21),
179 MXC91231_PIN_AP_CSI_D3 = IOMUX_PIN(0, 1, 27, 15, 2, 21),
180 MXC91231_PIN_AP_CSI_D4 = IOMUX_PIN(0, 1, 28, 15, 3, 21),
181 MXC91231_PIN_AP_CSI_D5 = IOMUX_PIN(0, 1, 29, 16, 0, 21),
182 MXC91231_PIN_AP_CSI_D6 = IOMUX_PIN(0, 1, 30, 16, 1, 21),
183 MXC91231_PIN_AP_CSI_D7 = IOMUX_PIN(0, 1, 31, 16, 2, 21),
184 MXC91231_PIN_AP_CSI_D8 = IOMUX_PIN(0, 2, 0, 16, 3, 21),
185 MXC91231_PIN_AP_CSI_D9 = IOMUX_PIN(0, 2, 1, 17, 0, 21),
186 MXC91231_PIN_AP_CSI_MCLK = IOMUX_PIN(0, 2, 2, 17, 1, 21),
187 MXC91231_PIN_AP_CSI_VSYNC = IOMUX_PIN(0, 2, 3, 17, 2, 21),
188 MXC91231_PIN_AP_CSI_HSYNC = IOMUX_PIN(0, 2, 4, 17, 3, 21),
189 MXC91231_PIN_AP_CSI_PIXCLK = IOMUX_PIN(0, 2, 5, 18, 0, 21),
190 MXC91231_PIN_AP_I2CLK = IOMUX_PIN(0, 2, 6, 18, 1, 12),
191 MXC91231_PIN_AP_I2DAT = IOMUX_PIN(0, 2, 7, 18, 2, 12),
192 MXC91231_PIN_AP_GPIO_AP_C8 = IOMUX_PIN(0, 2, 8, 18, 3, 9),
193 MXC91231_PIN_AP_GPIO_AP_C9 = IOMUX_PIN(0, 2, 9, 19, 0, 9),
194 MXC91231_PIN_AP_GPIO_AP_C10 = IOMUX_PIN(0, 2, 10, 19, 1, 9),
195 MXC91231_PIN_AP_GPIO_AP_C11 = IOMUX_PIN(0, 2, 11, 19, 2, 9),
196 MXC91231_PIN_AP_GPIO_AP_C12 = IOMUX_PIN(0, 2, 12, 19, 3, 9),
197 MXC91231_PIN_AP_GPIO_AP_C13 = IOMUX_PIN(0, 2, 13, 20, 0, 28),
198 MXC91231_PIN_AP_GPIO_AP_C14 = IOMUX_PIN(0, 2, 14, 20, 1, 28),
199 MXC91231_PIN_AP_GPIO_AP_C15 = IOMUX_PIN(0, 2, 15, 20, 2, 9),
200 MXC91231_PIN_AP_GPIO_AP_C16 = IOMUX_PIN(0, 2, 16, 20, 3, 9),
201 MXC91231_PIN_AP_GPIO_AP_C17 = IOMUX_PIN(0, 2, 17, 21, 0, 9),
202 MXC91231_PIN_AP_ED_INT0 = IOMUX_PIN(0, 2, 18, 21, 1, 22),
203 MXC91231_PIN_AP_ED_INT1 = IOMUX_PIN(0, 2, 19, 21, 2, 22),
204 MXC91231_PIN_AP_ED_INT2 = IOMUX_PIN(0, 2, 20, 21, 3, 22),
205 MXC91231_PIN_AP_ED_INT3 = IOMUX_PIN(0, 2, 21, 22, 0, 22),
206 MXC91231_PIN_AP_ED_INT4 = IOMUX_PIN(0, 2, 22, 22, 1, 23),
207 MXC91231_PIN_AP_ED_INT5 = IOMUX_PIN(0, 2, 23, 22, 2, 23),
208 MXC91231_PIN_AP_ED_INT6 = IOMUX_PIN(0, 2, 24, 22, 3, 23),
209 MXC91231_PIN_AP_ED_INT7 = IOMUX_PIN(0, 2, 25, 23, 0, 23),
210 MXC91231_PIN_AP_U2_DSR_B = IOMUX_PIN(0, 2, 26, 23, 1, 28),
211 MXC91231_PIN_AP_U2_RI_B = IOMUX_PIN(0, 2, 27, 23, 2, 28),
212 MXC91231_PIN_AP_U2_CTS_B = IOMUX_PIN(0, 2, 28, 23, 3, 28),
213 MXC91231_PIN_AP_U2_DTR_B = IOMUX_PIN(0, 2, 29, 24, 0, 28),
214 MXC91231_PIN_AP_KPROW0 = IOMUX_PIN(0, 7, 0, 24, 1, 10),
215 MXC91231_PIN_AP_KPROW1 = IOMUX_PIN(0, 1, 15, 24, 2, 10),
216 MXC91231_PIN_AP_KPROW2 = IOMUX_PIN(0, 7, 0, 24, 3, 10),
217 MXC91231_PIN_AP_KPROW3 = IOMUX_PIN(0, 7, 0, 25, 0, 10),
218 MXC91231_PIN_AP_KPCOL0 = IOMUX_PIN(0, 7, 0, 25, 1, 11),
219 MXC91231_PIN_AP_KPCOL1 = IOMUX_PIN(0, 7, 0, 25, 2, 11),
220 MXC91231_PIN_AP_KPCOL2 = IOMUX_PIN(0, 7, 0, 25, 3, 11),
221
222 /* Shared pins */
223 MXC91231_PIN_SP_U3_TXD = IOMUX_PIN(1, 3, 0, 0, 0, 28),
224 MXC91231_PIN_SP_U3_RXD = IOMUX_PIN(1, 3, 1, 0, 1, 28),
225 MXC91231_PIN_SP_U3_RTS_B = IOMUX_PIN(1, 3, 2, 0, 2, 28),
226 MXC91231_PIN_SP_U3_CTS_B = IOMUX_PIN(1, 3, 3, 0, 3, 28),
227 MXC91231_PIN_SP_USB_TXOE_B = IOMUX_PIN(1, 3, 4, 1, 0, 28),
228 MXC91231_PIN_SP_USB_DAT_VP = IOMUX_PIN(1, 3, 5, 1, 1, 28),
229 MXC91231_PIN_SP_USB_SE0_VM = IOMUX_PIN(1, 3, 6, 1, 2, 28),
230 MXC91231_PIN_SP_USB_RXD = IOMUX_PIN(1, 3, 7, 1, 3, 28),
231 MXC91231_PIN_SP_UH2_TXOE_B = IOMUX_PIN(1, 3, 8, 2, 0, 28),
232 MXC91231_PIN_SP_UH2_SPEED = IOMUX_PIN(1, 3, 9, 2, 1, 28),
233 MXC91231_PIN_SP_UH2_SUSPEN = IOMUX_PIN(1, 3, 10, 2, 2, 28),
234 MXC91231_PIN_SP_UH2_TXDP = IOMUX_PIN(1, 3, 11, 2, 3, 28),
235 MXC91231_PIN_SP_UH2_RXDP = IOMUX_PIN(1, 3, 12, 3, 0, 28),
236 MXC91231_PIN_SP_UH2_RXDM = IOMUX_PIN(1, 3, 13, 3, 1, 28),
237 MXC91231_PIN_SP_UH2_OVR = IOMUX_PIN(1, 3, 14, 3, 2, 28),
238 MXC91231_PIN_SP_UH2_PWR = IOMUX_PIN(1, 3, 15, 3, 3, 28),
239 MXC91231_PIN_SP_SD1_DAT0 = IOMUX_PIN(1, 3, 16, 4, 0, 25),
240 MXC91231_PIN_SP_SD1_DAT1 = IOMUX_PIN(1, 3, 17, 4, 1, 25),
241 MXC91231_PIN_SP_SD1_DAT2 = IOMUX_PIN(1, 3, 18, 4, 2, 25),
242 MXC91231_PIN_SP_SD1_DAT3 = IOMUX_PIN(1, 3, 19, 4, 3, 25),
243 MXC91231_PIN_SP_SD1_CMD = IOMUX_PIN(1, 3, 20, 5, 0, 25),
244 MXC91231_PIN_SP_SD1_CLK = IOMUX_PIN(1, 3, 21, 5, 1, 25),
245 MXC91231_PIN_SP_SD2_DAT0 = IOMUX_PIN(1, 3, 22, 5, 2, 26),
246 MXC91231_PIN_SP_SD2_DAT1 = IOMUX_PIN(1, 3, 23, 5, 3, 26),
247 MXC91231_PIN_SP_SD2_DAT2 = IOMUX_PIN(1, 3, 24, 6, 0, 26),
248 MXC91231_PIN_SP_SD2_DAT3 = IOMUX_PIN(1, 3, 25, 6, 1, 26),
249 MXC91231_PIN_SP_GPIO_SP_A26 = IOMUX_PIN(1, 3, 26, 6, 2, 28),
250 MXC91231_PIN_SP_SPI1_CLK = IOMUX_PIN(1, 3, 27, 6, 3, 13),
251 MXC91231_PIN_SP_SPI1_MOSI = IOMUX_PIN(1, 3, 28, 7, 0, 13),
252 MXC91231_PIN_SP_SPI1_MISO = IOMUX_PIN(1, 3, 29, 7, 1, 13),
253 MXC91231_PIN_SP_SPI1_SS0 = IOMUX_PIN(1, 3, 30, 7, 2, 13),
254 MXC91231_PIN_SP_SPI1_SS1 = IOMUX_PIN(1, 3, 31, 7, 3, 13),
255 MXC91231_PIN_SP_SD2_CMD = IOMUX_PIN(1, 7, 0, 8, 0, 26),
256 MXC91231_PIN_SP_SD2_CLK = IOMUX_PIN(1, 7, 0, 8, 1, 26),
257 MXC91231_PIN_SP_SIM1_RST_B = IOMUX_PIN(1, 2, 30, 8, 2, 28),
258 MXC91231_PIN_SP_SIM1_SVEN = IOMUX_PIN(1, 7, 0, 8, 3, 28),
259 MXC91231_PIN_SP_SIM1_CLK = IOMUX_PIN(1, 7, 0, 9, 0, 28),
260 MXC91231_PIN_SP_SIM1_TRXD = IOMUX_PIN(1, 7, 0, 9, 1, 28),
261 MXC91231_PIN_SP_SIM1_PD = IOMUX_PIN(1, 2, 31, 9, 2, 28),
262 MXC91231_PIN_SP_UH2_TXDM = IOMUX_PIN(1, 7, 0, 9, 3, 28),
263 MXC91231_PIN_SP_UH2_RXD = IOMUX_PIN(1, 7, 0, 10, 0, 28),
264};
265
266#define PIN_AP_MAX (104)
267#define PIN_SP_MAX (41)
268
269#define PIN_MAX (PIN_AP_MAX + PIN_SP_MAX)
270
271/*
272 * Convenience values for use with mxc_iomux_mode()
273 *
274 * Format here is MXC91231_PIN_(pin name)__(function)
275 */
276
277#define MXC91231_PIN_SP_USB_DAT_VP__USB_DAT_VP \
278 IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_FUNC)
279#define MXC91231_PIN_SP_USB_SE0_VM__USB_SE0_VM \
280 IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_FUNC)
281#define MXC91231_PIN_SP_USB_DAT_VP__RXD2 \
282 IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_ALT1)
283#define MXC91231_PIN_SP_USB_SE0_VM__TXD2 \
284 IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_ALT1)
285
286
287#endif /* __MACH_IOMUX_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 7cd84547658f..a0fa40265468 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -68,28 +68,24 @@ struct pad_desc {
68/* 68/*
69 * Use to set PAD control 69 * Use to set PAD control
70 */ 70 */
71#define PAD_CTL_DRIVE_VOLTAGE_3_3_V 0
72#define PAD_CTL_DRIVE_VOLTAGE_1_8_V 1
73 71
74#define PAD_CTL_NO_HYSTERESIS 0 72#define PAD_CTL_DVS (1 << 13)
75#define PAD_CTL_HYSTERESIS 1 73#define PAD_CTL_HYS (1 << 8)
76 74
77#define PAD_CTL_PULL_DISABLED 0x0 75#define PAD_CTL_PKE (1 << 7)
78#define PAD_CTL_PULL_KEEPER 0xa 76#define PAD_CTL_PUE (1 << 6)
79#define PAD_CTL_PULL_DOWN_100K 0xc 77#define PAD_CTL_PUS_100K_DOWN (0 << 4)
80#define PAD_CTL_PULL_UP_47K 0xd 78#define PAD_CTL_PUS_47K_UP (1 << 4)
81#define PAD_CTL_PULL_UP_100K 0xe 79#define PAD_CTL_PUS_100K_UP (2 << 4)
82#define PAD_CTL_PULL_UP_22K 0xf 80#define PAD_CTL_PUS_22K_UP (3 << 4)
83 81
84#define PAD_CTL_OUTPUT_CMOS 0 82#define PAD_CTL_ODE (1 << 3)
85#define PAD_CTL_OUTPUT_OPEN_DRAIN 1
86 83
87#define PAD_CTL_DRIVE_STRENGTH_NORM 0 84#define PAD_CTL_DSE_STANDARD (0 << 1)
88#define PAD_CTL_DRIVE_STRENGTH_HIGH 1 85#define PAD_CTL_DSE_HIGH (1 << 1)
89#define PAD_CTL_DRIVE_STRENGTH_MAX 2 86#define PAD_CTL_DSE_MAX (2 << 1)
90 87
91#define PAD_CTL_SLEW_RATE_SLOW 0 88#define PAD_CTL_SRE_FAST (1 << 0)
92#define PAD_CTL_SLEW_RATE_FAST 1
93 89
94/* 90/*
95 * setups a single pad: 91 * setups a single pad:
@@ -117,5 +113,10 @@ void mxc_iomux_v3_release_pad(struct pad_desc *pad);
117 */ 113 */
118void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count); 114void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count);
119 115
116/*
117 * Initialise the iomux controller
118 */
119void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
120
120#endif /* __MACH_IOMUX_V3_H__*/ 121#endif /* __MACH_IOMUX_V3_H__*/
121 122
diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h
index 171f8adc1109..6d49f8ae3259 100644
--- a/arch/arm/plat-mxc/include/mach/iomux.h
+++ b/arch/arm/plat-mxc/include/mach/iomux.h
@@ -49,6 +49,9 @@
49#ifdef CONFIG_ARCH_MX2 49#ifdef CONFIG_ARCH_MX2
50# define GPIO_PORT_MAX 5 50# define GPIO_PORT_MAX 5
51#endif 51#endif
52#ifdef CONFIG_ARCH_MX25
53# define GPIO_PORT_MAX 3
54#endif
52 55
53#ifndef GPIO_PORT_MAX 56#ifndef GPIO_PORT_MAX
54# error "GPIO config port count unknown!" 57# error "GPIO config port count unknown!"
@@ -107,6 +110,9 @@
107#include <mach/iomux-mx27.h> 110#include <mach/iomux-mx27.h>
108#endif 111#endif
109#endif 112#endif
113#ifdef CONFIG_ARCH_MX25
114#include <mach/iomux-mx25.h>
115#endif
110 116
111 117
112/* decode irq number to use with IMR(x), ISR(x) and friends */ 118/* decode irq number to use with IMR(x), ISR(x) and friends */
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 518a36504b88..ead9d592168d 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -24,6 +24,10 @@
24#define MXC_GPIO_IRQS (32 * 6) 24#define MXC_GPIO_IRQS (32 * 6)
25#elif defined CONFIG_ARCH_MX3 25#elif defined CONFIG_ARCH_MX3
26#define MXC_GPIO_IRQS (32 * 3) 26#define MXC_GPIO_IRQS (32 * 3)
27#elif defined CONFIG_ARCH_MX25
28#define MXC_GPIO_IRQS (32 * 4)
29#elif defined CONFIG_ARCH_MXC91231
30#define MXC_GPIO_IRQS (32 * 4)
27#endif 31#endif
28 32
29/* 33/*
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 6065e00176ed..d3afafdcc0e5 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -22,6 +22,10 @@
22#endif 22#endif
23#elif defined CONFIG_ARCH_MX3 23#elif defined CONFIG_ARCH_MX3
24#define PHYS_OFFSET UL(0x80000000) 24#define PHYS_OFFSET UL(0x80000000)
25#elif defined CONFIG_ARCH_MX25
26#define PHYS_OFFSET UL(0x80000000)
27#elif defined CONFIG_ARCH_MXC91231
28#define PHYS_OFFSET UL(0x90000000)
25#endif 29#endif
26 30
27#if defined(CONFIG_MX1_VIDEO) 31#if defined(CONFIG_MX1_VIDEO)
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 1000bf330bcd..1b2890a5c452 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -12,10 +12,6 @@
12#ifndef __ASM_ARCH_MXC_MX1_H__ 12#ifndef __ASM_ARCH_MXC_MX1_H__
13#define __ASM_ARCH_MXC_MX1_H__ 13#define __ASM_ARCH_MXC_MX1_H__
14 14
15#ifndef __ASM_ARCH_MXC_HARDWARE_H__
16#error "Do not include directly."
17#endif
18
19#include <mach/vmalloc.h> 15#include <mach/vmalloc.h>
20 16
21/* 17/*
@@ -138,20 +134,6 @@
138#define GPIO_INT_PORTD 62 134#define GPIO_INT_PORTD 62
139#define WDT_INT 63 135#define WDT_INT 63
140 136
141/* gpio and gpio based interrupt handling */
142#define GPIO_DR 0x1C
143#define GPIO_GDIR 0x00
144#define GPIO_PSR 0x24
145#define GPIO_ICR1 0x28
146#define GPIO_ICR2 0x2C
147#define GPIO_IMR 0x30
148#define GPIO_ISR 0x34
149#define GPIO_INT_LOW_LEV 0x3
150#define GPIO_INT_HIGH_LEV 0x2
151#define GPIO_INT_RISE_EDGE 0x0
152#define GPIO_INT_FALL_EDGE 0x1
153#define GPIO_INT_NONE 0x4
154
155/* DMA */ 137/* DMA */
156#define DMA_REQ_UART3_T 2 138#define DMA_REQ_UART3_T 2
157#define DMA_REQ_UART3_R 3 139#define DMA_REQ_UART3_R 3
@@ -179,8 +161,4 @@
179#define DMA_REQ_UART1_T 30 161#define DMA_REQ_UART1_T 30
180#define DMA_REQ_UART1_R 31 162#define DMA_REQ_UART1_R 31
181 163
182/* mandatory for CONFIG_DEBUG_LL */
183#define MXC_LL_UART_PADDR UART1_BASE_ADDR
184#define MXC_LL_UART_VADDR IO_ADDRESS(UART1_BASE_ADDR)
185
186#endif /* __ASM_ARCH_MXC_MX1_H__ */ 164#endif /* __ASM_ARCH_MXC_MX1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index 8b070a041a99..21112c695ec5 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -25,11 +25,6 @@
25#ifndef __ASM_ARCH_MXC_MX21_H__ 25#ifndef __ASM_ARCH_MXC_MX21_H__
26#define __ASM_ARCH_MXC_MX21_H__ 26#define __ASM_ARCH_MXC_MX21_H__
27 27
28#ifndef __ASM_ARCH_MXC_HARDWARE_H__
29#error "Do not include directly."
30#endif
31
32
33/* Memory regions and CS */ 28/* Memory regions and CS */
34#define SDRAM_BASE_ADDR 0xC0000000 29#define SDRAM_BASE_ADDR 0xC0000000
35#define CSD1_BASE_ADDR 0xC4000000 30#define CSD1_BASE_ADDR 0xC4000000
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
new file mode 100644
index 000000000000..ec64bd9a8ab1
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -0,0 +1,44 @@
1#ifndef __MACH_MX25_H__
2#define __MACH_MX25_H__
3
4#define MX25_AIPS1_BASE_ADDR 0x43F00000
5#define MX25_AIPS1_BASE_ADDR_VIRT 0xFC000000
6#define MX25_AIPS1_SIZE SZ_1M
7#define MX25_AIPS2_BASE_ADDR 0x53F00000
8#define MX25_AIPS2_BASE_ADDR_VIRT 0xFC200000
9#define MX25_AIPS2_SIZE SZ_1M
10#define MX25_AVIC_BASE_ADDR 0x68000000
11#define MX25_AVIC_BASE_ADDR_VIRT 0xFC400000
12#define MX25_AVIC_SIZE SZ_1M
13
14#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
15
16#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
17#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
18#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
19
20#define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000)
21#define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000)
22#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000)
23#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000)
24
25#define MX25_AIPS1_IO_ADDRESS(x) \
26 (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
27#define MX25_AIPS2_IO_ADDRESS(x) \
28 (((x) - MX25_AIPS2_BASE_ADDR) + MX25_AIPS2_BASE_ADDR_VIRT)
29#define MX25_AVIC_IO_ADDRESS(x) \
30 (((x) - MX25_AVIC_BASE_ADDR) + MX25_AVIC_BASE_ADDR_VIRT)
31
32#define __in_range(addr, name) ((addr) >= name##_BASE_ADDR && (addr) < name##_BASE_ADDR + name##_SIZE)
33
34#define MX25_IO_ADDRESS(x) \
35 (void __force __iomem *) \
36 (__in_range(x, MX25_AIPS1) ? MX25_AIPS1_IO_ADDRESS(x) : \
37 __in_range(x, MX25_AIPS2) ? MX25_AIPS2_IO_ADDRESS(x) : \
38 __in_range(x, MX25_AVIC) ? MX25_AVIC_IO_ADDRESS(x) : \
39 0xDEADBEEF)
40
41#define UART1_BASE_ADDR 0x43f90000
42#define UART2_BASE_ADDR 0x43f94000
43
44#endif /* __MACH_MX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 6e93f2c0b7bb..dc3ad9aa952a 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -24,10 +24,6 @@
24#ifndef __ASM_ARCH_MXC_MX27_H__ 24#ifndef __ASM_ARCH_MXC_MX27_H__
25#define __ASM_ARCH_MXC_MX27_H__ 25#define __ASM_ARCH_MXC_MX27_H__
26 26
27#ifndef __ASM_ARCH_MXC_HARDWARE_H__
28#error "Do not include directly."
29#endif
30
31/* IRAM */ 27/* IRAM */
32#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */ 28#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */
33 29
@@ -120,7 +116,4 @@ extern int mx27_revision(void);
120 116
121/* Mandatory defines used globally */ 117/* Mandatory defines used globally */
122 118
123/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
124#define ARCH_NR_GPIOS (192 + 16)
125
126#endif /* __ASM_ARCH_MXC_MX27_H__ */ 119#endif /* __ASM_ARCH_MXC_MX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index fc40d3ab8c5b..db5d921e0fe6 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -23,10 +23,6 @@
23#ifndef __ASM_ARCH_MXC_MX2x_H__ 23#ifndef __ASM_ARCH_MXC_MX2x_H__
24#define __ASM_ARCH_MXC_MX2x_H__ 24#define __ASM_ARCH_MXC_MX2x_H__
25 25
26#ifndef __ASM_ARCH_MXC_HARDWARE_H__
27#error "Do not include directly."
28#endif
29
30/* The following addresses are common between i.MX21 and i.MX27 */ 26/* The following addresses are common between i.MX21 and i.MX27 */
31 27
32/* Register offests */ 28/* Register offests */
@@ -154,20 +150,6 @@
154#define MXC_INT_GPIO 8 150#define MXC_INT_GPIO 8
155#define MXC_INT_CSPI3 6 151#define MXC_INT_CSPI3 6
156 152
157/* gpio and gpio based interrupt handling */
158#define GPIO_DR 0x1C
159#define GPIO_GDIR 0x00
160#define GPIO_PSR 0x24
161#define GPIO_ICR1 0x28
162#define GPIO_ICR2 0x2C
163#define GPIO_IMR 0x30
164#define GPIO_ISR 0x34
165#define GPIO_INT_LOW_LEV 0x3
166#define GPIO_INT_HIGH_LEV 0x2
167#define GPIO_INT_RISE_EDGE 0x0
168#define GPIO_INT_FALL_EDGE 0x1
169#define GPIO_INT_NONE 0x4
170
171/* fixed DMA request numbers */ 153/* fixed DMA request numbers */
172#define DMA_REQ_CSI_RX 31 154#define DMA_REQ_CSI_RX 31
173#define DMA_REQ_CSI_STAT 30 155#define DMA_REQ_CSI_STAT 30
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index 0b06941b6139..14ac0dcc82f4 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -4,7 +4,7 @@
4#define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ 4#define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */
5#define MX31_IRAM_SIZE SZ_16K 5#define MX31_IRAM_SIZE SZ_16K
6 6
7#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) 7#define MX31_OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
8#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) 8#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
9#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) 9#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
10#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) 10#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 6465fefb42e3..ab4cfec6c8ab 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -5,6 +5,7 @@
5#define MX35_IRAM_SIZE SZ_128K 5#define MX35_IRAM_SIZE SZ_128K
6 6
7#define MXC_FEC_BASE_ADDR 0x50038000 7#define MXC_FEC_BASE_ADDR 0x50038000
8#define MX35_OTG_BASE_ADDR 0x53ff4000
8#define MX35_NFC_BASE_ADDR 0xBB000000 9#define MX35_NFC_BASE_ADDR 0xBB000000
9 10
10/* 11/*
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index b559a4bb5769..009f4440276b 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -11,10 +11,6 @@
11#ifndef __ASM_ARCH_MXC_MX31_H__ 11#ifndef __ASM_ARCH_MXC_MX31_H__
12#define __ASM_ARCH_MXC_MX31_H__ 12#define __ASM_ARCH_MXC_MX31_H__
13 13
14#ifndef __ASM_ARCH_MXC_HARDWARE_H__
15#error "Do not include directly."
16#endif
17
18/* 14/*
19 * MX31 memory map: 15 * MX31 memory map:
20 * 16 *
@@ -263,25 +259,8 @@
263#define SYSTEM_REV_MIN CHIP_REV_1_0 259#define SYSTEM_REV_MIN CHIP_REV_1_0
264#define SYSTEM_REV_NUM 3 260#define SYSTEM_REV_NUM 3
265 261
266/* gpio and gpio based interrupt handling */
267#define GPIO_DR 0x00
268#define GPIO_GDIR 0x04
269#define GPIO_PSR 0x08
270#define GPIO_ICR1 0x0C
271#define GPIO_ICR2 0x10
272#define GPIO_IMR 0x14
273#define GPIO_ISR 0x18
274#define GPIO_INT_LOW_LEV 0x0
275#define GPIO_INT_HIGH_LEV 0x1
276#define GPIO_INT_RISE_EDGE 0x2
277#define GPIO_INT_FALL_EDGE 0x3
278#define GPIO_INT_NONE 0x4
279
280/* Mandatory defines used globally */ 262/* Mandatory defines used globally */
281 263
282/* this CPU supports up to 96 GPIOs */
283#define ARCH_NR_GPIOS 96
284
285#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 264#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
286 265
287extern unsigned int system_rev; 266extern unsigned int system_rev;
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 5fa2a07f4eaf..51990536b845 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -26,9 +26,11 @@
26 26
27#define MXC_CPU_MX1 1 27#define MXC_CPU_MX1 1
28#define MXC_CPU_MX21 21 28#define MXC_CPU_MX21 21
29#define MXC_CPU_MX25 25
29#define MXC_CPU_MX27 27 30#define MXC_CPU_MX27 27
30#define MXC_CPU_MX31 31 31#define MXC_CPU_MX31 31
31#define MXC_CPU_MX35 35 32#define MXC_CPU_MX35 35
33#define MXC_CPU_MXC91231 91231
32 34
33#ifndef __ASSEMBLY__ 35#ifndef __ASSEMBLY__
34extern unsigned int __mxc_cpu_type; 36extern unsigned int __mxc_cpu_type;
@@ -58,6 +60,18 @@ extern unsigned int __mxc_cpu_type;
58# define cpu_is_mx21() (0) 60# define cpu_is_mx21() (0)
59#endif 61#endif
60 62
63#ifdef CONFIG_ARCH_MX25
64# ifdef mxc_cpu_type
65# undef mxc_cpu_type
66# define mxc_cpu_type __mxc_cpu_type
67# else
68# define mxc_cpu_type MXC_CPU_MX25
69# endif
70# define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25)
71#else
72# define cpu_is_mx25() (0)
73#endif
74
61#ifdef CONFIG_MACH_MX27 75#ifdef CONFIG_MACH_MX27
62# ifdef mxc_cpu_type 76# ifdef mxc_cpu_type
63# undef mxc_cpu_type 77# undef mxc_cpu_type
@@ -94,13 +108,25 @@ extern unsigned int __mxc_cpu_type;
94# define cpu_is_mx35() (0) 108# define cpu_is_mx35() (0)
95#endif 109#endif
96 110
111#ifdef CONFIG_ARCH_MXC91231
112# ifdef mxc_cpu_type
113# undef mxc_cpu_type
114# define mxc_cpu_type __mxc_cpu_type
115# else
116# define mxc_cpu_type MXC_CPU_MXC91231
117# endif
118# define cpu_is_mxc91231() (mxc_cpu_type == MXC_CPU_MXC91231)
119#else
120# define cpu_is_mxc91231() (0)
121#endif
122
97#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) 123#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
98#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10) 124#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10)
99#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4) 125#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4)
100#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8) 126#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8)
101#endif 127#endif
102 128
103#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35()) 129#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231())
104#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) 130#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
105 131
106#endif /* __ASM_ARCH_MXC_H__ */ 132#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
new file mode 100644
index 000000000000..81484d1ef232
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -0,0 +1,315 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * - Platform specific register memory map
4 *
5 * Copyright 2005-2007 Motorola, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __MACH_MXC91231_H__
22#define __MACH_MXC91231_H__
23
24/*
25 * L2CC
26 */
27#define MXC91231_L2CC_BASE_ADDR 0x30000000
28#define MXC91231_L2CC_BASE_ADDR_VIRT 0xF9000000
29#define MXC91231_L2CC_SIZE SZ_64K
30
31/*
32 * AIPS 1
33 */
34#define MXC91231_AIPS1_BASE_ADDR 0x43F00000
35#define MXC91231_AIPS1_BASE_ADDR_VIRT 0xFC000000
36#define MXC91231_AIPS1_SIZE SZ_1M
37
38#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR
39#define MXC91231_MAX_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x04000)
40#define MXC91231_EVTMON_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x08000)
41#define MXC91231_CLKCTL_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x0C000)
42#define MXC91231_ETB_SLOT4_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x10000)
43#define MXC91231_ETB_SLOT5_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x14000)
44#define MXC91231_ECT_CTIO_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x18000)
45#define MXC91231_I2C_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x80000)
46#define MXC91231_MU_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x88000)
47#define MXC91231_UART1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x90000)
48#define MXC91231_UART2_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x94000)
49#define MXC91231_DSM_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x98000)
50#define MXC91231_OWIRE_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x9C000)
51#define MXC91231_SSI1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA0000)
52#define MXC91231_KPP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA8000)
53#define MXC91231_IOMUX_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xAC000)
54#define MXC91231_CTI_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xB8000)
55
56/*
57 * AIPS 2
58 */
59#define MXC91231_AIPS2_BASE_ADDR 0x53F00000
60#define MXC91231_AIPS2_BASE_ADDR_VIRT 0xFC100000
61#define MXC91231_AIPS2_SIZE SZ_1M
62
63#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000)
64#define MXC91231_GPT1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x90000)
65#define MXC91231_EPIT1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x94000)
66#define MXC91231_SCC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xAC000)
67#define MXC91231_RNGA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xB0000)
68#define MXC91231_IPU_CTRL_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC0000)
69#define MXC91231_AUDMUX_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC4000)
70#define MXC91231_EDIO_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC8000)
71#define MXC91231_GPIO1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xCC000)
72#define MXC91231_GPIO2_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD0000)
73#define MXC91231_SDMA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD4000)
74#define MXC91231_RTC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD8000)
75#define MXC91231_WDOG1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xDC000)
76#define MXC91231_PWM_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE0000)
77#define MXC91231_GPIO3_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE4000)
78#define MXC91231_WDOG2_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE8000)
79#define MXC91231_RTIC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xEC000)
80#define MXC91231_LPMC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xF0000)
81
82/*
83 * SPBA global module 0
84 */
85#define MXC91231_SPBA0_BASE_ADDR 0x50000000
86#define MXC91231_SPBA0_BASE_ADDR_VIRT 0xFC200000
87#define MXC91231_SPBA0_SIZE SZ_1M
88
89#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000)
90#define MXC91231_MMC_SDHC2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x08000)
91#define MXC91231_UART3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x0C000)
92#define MXC91231_CSPI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x10000)
93#define MXC91231_SSI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x14000)
94#define MXC91231_SIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x18000)
95#define MXC91231_IIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x1C000)
96#define MXC91231_CTI_SDMA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x20000)
97#define MXC91231_USBOTG_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x24000)
98#define MXC91231_USBOTG_DATA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x28000)
99#define MXC91231_CSPI1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x30000)
100#define MXC91231_SPBA_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x3C000)
101#define MXC91231_IOMUX_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x40000)
102#define MXC91231_CRM_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x44000)
103#define MXC91231_CRM_AP_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x48000)
104#define MXC91231_PLL0_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x4C000)
105#define MXC91231_PLL1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x50000)
106#define MXC91231_PLL2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x54000)
107#define MXC91231_GPIO4_SH_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x58000)
108#define MXC91231_HAC_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
109#define MXC91231_SAHARA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
110#define MXC91231_PLL3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x60000)
111
112/*
113 * SPBA global module 1
114 */
115#define MXC91231_SPBA1_BASE_ADDR 0x52000000
116#define MXC91231_SPBA1_BASE_ADDR_VIRT 0xFC300000
117#define MXC91231_SPBA1_SIZE SZ_1M
118
119#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000)
120#define MXC91231_EL1T_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x38000)
121
122/*!
123 * Defines for SPBA modules
124 */
125#define MXC91231_SPBA_SDHC1 0x04
126#define MXC91231_SPBA_SDHC2 0x08
127#define MXC91231_SPBA_UART3 0x0C
128#define MXC91231_SPBA_CSPI2 0x10
129#define MXC91231_SPBA_SSI2 0x14
130#define MXC91231_SPBA_SIM 0x18
131#define MXC91231_SPBA_IIM 0x1C
132#define MXC91231_SPBA_CTI_SDMA 0x20
133#define MXC91231_SPBA_USBOTG_CTRL_REGS 0x24
134#define MXC91231_SPBA_USBOTG_DATA_REGS 0x28
135#define MXC91231_SPBA_CSPI1 0x30
136#define MXC91231_SPBA_MQSPI 0x34
137#define MXC91231_SPBA_EL1T 0x38
138#define MXC91231_SPBA_IOMUX 0x40
139#define MXC91231_SPBA_CRM_COM 0x44
140#define MXC91231_SPBA_CRM_AP 0x48
141#define MXC91231_SPBA_PLL0 0x4C
142#define MXC91231_SPBA_PLL1 0x50
143#define MXC91231_SPBA_PLL2 0x54
144#define MXC91231_SPBA_GPIO4 0x58
145#define MXC91231_SPBA_SAHARA 0x5C
146
147/*
148 * ROMP and AVIC
149 */
150#define MXC91231_ROMP_BASE_ADDR 0x60000000
151#define MXC91231_ROMP_BASE_ADDR_VIRT 0xFC400000
152#define MXC91231_ROMP_SIZE SZ_64K
153
154#define MXC91231_AVIC_BASE_ADDR 0x68000000
155#define MXC91231_AVIC_BASE_ADDR_VIRT 0xFC410000
156#define MXC91231_AVIC_SIZE SZ_64K
157
158/*
159 * NAND, SDRAM, WEIM, M3IF, EMI controllers
160 */
161#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000
162#define MXC91231_X_MEMC_BASE_ADDR_VIRT 0xFC420000
163#define MXC91231_X_MEMC_SIZE SZ_64K
164
165#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000)
166#define MXC91231_ESDCTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x1000)
167#define MXC91231_WEIM_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x2000)
168#define MXC91231_M3IF_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x3000)
169#define MXC91231_EMI_CTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x4000)
170
171/*
172 * Memory regions and CS
173 * CPLD is connected on CS4
174 * CS5 is TP1021 or it is not connected
175 * */
176#define MXC91231_FB_RAM_BASE_ADDR 0x78000000
177#define MXC91231_FB_RAM_SIZE SZ_256K
178#define MXC91231_CSD0_BASE_ADDR 0x80000000
179#define MXC91231_CSD1_BASE_ADDR 0x90000000
180#define MXC91231_CS0_BASE_ADDR 0xA0000000
181#define MXC91231_CS1_BASE_ADDR 0xA8000000
182#define MXC91231_CS2_BASE_ADDR 0xB0000000
183#define MXC91231_CS3_BASE_ADDR 0xB2000000
184#define MXC91231_CS4_BASE_ADDR 0xB4000000
185#define MXC91231_CS5_BASE_ADDR 0xB6000000
186
187/* Is given address belongs to the specified memory region? */
188#define ADDRESS_IN_REGION(addr, start, size) \
189 (((addr) >= (start)) && ((addr) < (start)+(size)))
190
191/* Is given address belongs to the specified named `module'? */
192#define MXC91231_IS_MODULE(addr, module) \
193 ADDRESS_IN_REGION(addr, MXC91231_ ## module ## _BASE_ADDR, \
194 MXC91231_ ## module ## _SIZE)
195/*
196 * This macro defines the physical to virtual address mapping for all the
197 * peripheral modules. It is used by passing in the physical address as x
198 * and returning the virtual address. If the physical address is not mapped,
199 * it returns 0xDEADBEEF
200 */
201
202#define MXC91231_IO_ADDRESS(x) \
203 (void __iomem *) \
204 (MXC91231_IS_MODULE(x, L2CC) ? MXC91231_L2CC_IO_ADDRESS(x) : \
205 MXC91231_IS_MODULE(x, AIPS1) ? MXC91231_AIPS1_IO_ADDRESS(x) : \
206 MXC91231_IS_MODULE(x, AIPS2) ? MXC91231_AIPS2_IO_ADDRESS(x) : \
207 MXC91231_IS_MODULE(x, SPBA0) ? MXC91231_SPBA0_IO_ADDRESS(x) : \
208 MXC91231_IS_MODULE(x, SPBA1) ? MXC91231_SPBA1_IO_ADDRESS(x) : \
209 MXC91231_IS_MODULE(x, ROMP) ? MXC91231_ROMP_IO_ADDRESS(x) : \
210 MXC91231_IS_MODULE(x, AVIC) ? MXC91231_AVIC_IO_ADDRESS(x) : \
211 MXC91231_IS_MODULE(x, X_MEMC) ? MXC91231_X_MEMC_IO_ADDRESS(x) : \
212 0xDEADBEEF)
213
214
215/*
216 * define the address mapping macros: in physical address order
217 */
218#define MXC91231_L2CC_IO_ADDRESS(x) \
219 (((x) - MXC91231_L2CC_BASE_ADDR) + MXC91231_L2CC_BASE_ADDR_VIRT)
220
221#define MXC91231_AIPS1_IO_ADDRESS(x) \
222 (((x) - MXC91231_AIPS1_BASE_ADDR) + MXC91231_AIPS1_BASE_ADDR_VIRT)
223
224#define MXC91231_SPBA0_IO_ADDRESS(x) \
225 (((x) - MXC91231_SPBA0_BASE_ADDR) + MXC91231_SPBA0_BASE_ADDR_VIRT)
226
227#define MXC91231_SPBA1_IO_ADDRESS(x) \
228 (((x) - MXC91231_SPBA1_BASE_ADDR) + MXC91231_SPBA1_BASE_ADDR_VIRT)
229
230#define MXC91231_AIPS2_IO_ADDRESS(x) \
231 (((x) - MXC91231_AIPS2_BASE_ADDR) + MXC91231_AIPS2_BASE_ADDR_VIRT)
232
233#define MXC91231_ROMP_IO_ADDRESS(x) \
234 (((x) - MXC91231_ROMP_BASE_ADDR) + MXC91231_ROMP_BASE_ADDR_VIRT)
235
236#define MXC91231_AVIC_IO_ADDRESS(x) \
237 (((x) - MXC91231_AVIC_BASE_ADDR) + MXC91231_AVIC_BASE_ADDR_VIRT)
238
239#define MXC91231_X_MEMC_IO_ADDRESS(x) \
240 (((x) - MXC91231_X_MEMC_BASE_ADDR) + MXC91231_X_MEMC_BASE_ADDR_VIRT)
241
242/*
243 * Interrupt numbers
244 */
245#define MXC91231_INT_GPIO3 0
246#define MXC91231_INT_EL1T_CI 1
247#define MXC91231_INT_EL1T_RFCI 2
248#define MXC91231_INT_EL1T_RFI 3
249#define MXC91231_INT_EL1T_MCU 4
250#define MXC91231_INT_EL1T_IPI 5
251#define MXC91231_INT_MU_GEN 6
252#define MXC91231_INT_GPIO4 7
253#define MXC91231_INT_MMC_SDHC2 8
254#define MXC91231_INT_MMC_SDHC1 9
255#define MXC91231_INT_I2C 10
256#define MXC91231_INT_SSI2 11
257#define MXC91231_INT_SSI1 12
258#define MXC91231_INT_CSPI2 13
259#define MXC91231_INT_CSPI1 14
260#define MXC91231_INT_RTIC 15
261#define MXC91231_INT_SAHARA 15
262#define MXC91231_INT_HAC 15
263#define MXC91231_INT_UART3_RX 16
264#define MXC91231_INT_UART3_TX 17
265#define MXC91231_INT_UART3_MINT 18
266#define MXC91231_INT_ECT 19
267#define MXC91231_INT_SIM_IPB 20
268#define MXC91231_INT_SIM_DATA 21
269#define MXC91231_INT_RNGA 22
270#define MXC91231_INT_DSM_AP 23
271#define MXC91231_INT_KPP 24
272#define MXC91231_INT_RTC 25
273#define MXC91231_INT_PWM 26
274#define MXC91231_INT_GEMK_AP 27
275#define MXC91231_INT_EPIT 28
276#define MXC91231_INT_GPT 29
277#define MXC91231_INT_UART2_RX 30
278#define MXC91231_INT_UART2_TX 31
279#define MXC91231_INT_UART2_MINT 32
280#define MXC91231_INT_NANDFC 33
281#define MXC91231_INT_SDMA 34
282#define MXC91231_INT_USB_WAKEUP 35
283#define MXC91231_INT_USB_SOF 36
284#define MXC91231_INT_PMU_EVTMON 37
285#define MXC91231_INT_USB_FUNC 38
286#define MXC91231_INT_USB_DMA 39
287#define MXC91231_INT_USB_CTRL 40
288#define MXC91231_INT_IPU_ERR 41
289#define MXC91231_INT_IPU_SYN 42
290#define MXC91231_INT_UART1_RX 43
291#define MXC91231_INT_UART1_TX 44
292#define MXC91231_INT_UART1_MINT 45
293#define MXC91231_INT_IIM 46
294#define MXC91231_INT_MU_RX_OR 47
295#define MXC91231_INT_MU_TX_OR 48
296#define MXC91231_INT_SCC_SCM 49
297#define MXC91231_INT_SCC_SMN 50
298#define MXC91231_INT_GPIO2 51
299#define MXC91231_INT_GPIO1 52
300#define MXC91231_INT_MQSPI1 53
301#define MXC91231_INT_MQSPI2 54
302#define MXC91231_INT_WDOG2 55
303#define MXC91231_INT_EXT_INT7 56
304#define MXC91231_INT_EXT_INT6 57
305#define MXC91231_INT_EXT_INT5 58
306#define MXC91231_INT_EXT_INT4 59
307#define MXC91231_INT_EXT_INT3 60
308#define MXC91231_INT_EXT_INT2 61
309#define MXC91231_INT_EXT_INT1 62
310#define MXC91231_INT_EXT_INT0 63
311
312#define MXC91231_MAX_INT_LINES 63
313#define MXC91231_MAX_EXT_LINES 8
314
315#endif /* __MACH_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index e56241af870e..ef00199568de 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -21,8 +21,18 @@
21#ifndef __ASM_ARCH_MXC_SYSTEM_H__ 21#ifndef __ASM_ARCH_MXC_SYSTEM_H__
22#define __ASM_ARCH_MXC_SYSTEM_H__ 22#define __ASM_ARCH_MXC_SYSTEM_H__
23 23
24#include <mach/hardware.h>
25#include <mach/common.h>
26
24static inline void arch_idle(void) 27static inline void arch_idle(void)
25{ 28{
29#ifdef CONFIG_ARCH_MXC91231
30 if (cpu_is_mxc91231()) {
31 /* Need this to set DSM low-power mode */
32 mxc91231_prepare_idle();
33 }
34#endif
35
26 cpu_do_idle(); 36 cpu_do_idle();
27} 37}
28 38
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 07b4a73c9d2f..527a6c24788e 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -26,6 +26,10 @@
26#define CLOCK_TICK_RATE 13300000 26#define CLOCK_TICK_RATE 13300000
27#elif defined CONFIG_ARCH_MX3 27#elif defined CONFIG_ARCH_MX3
28#define CLOCK_TICK_RATE 16625000 28#define CLOCK_TICK_RATE 16625000
29#elif defined CONFIG_ARCH_MX25
30#define CLOCK_TICK_RATE 16000000
31#elif defined CONFIG_ARCH_MXC91231
32#define CLOCK_TICK_RATE 13000000
29#endif 33#endif
30 34
31#endif /* __ASM_ARCH_MXC_TIMEX_H__ */ 35#endif /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index de6fe0365982..082a3908256b 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -26,8 +26,11 @@
26#define __MXC_BOOT_UNCOMPRESS 26#define __MXC_BOOT_UNCOMPRESS
27 27
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29#include <asm/mach-types.h>
29 30
30#define UART(x) (*(volatile unsigned long *)(serial_port + (x))) 31static unsigned long uart_base;
32
33#define UART(x) (*(volatile unsigned long *)(uart_base + (x)))
31 34
32#define USR2 0x98 35#define USR2 0x98
33#define USR2_TXFE (1<<14) 36#define USR2_TXFE (1<<14)
@@ -46,19 +49,10 @@
46 49
47static void putc(int ch) 50static void putc(int ch)
48{ 51{
49 static unsigned long serial_port = 0; 52 if (!uart_base)
50 53 return;
51 if (unlikely(serial_port == 0)) { 54 if (!(UART(UCR1) & UCR1_UARTEN))
52 do { 55 return;
53 serial_port = UART1_BASE_ADDR;
54 if (UART(UCR1) & UCR1_UARTEN)
55 break;
56 serial_port = UART2_BASE_ADDR;
57 if (UART(UCR1) & UCR1_UARTEN)
58 break;
59 return;
60 } while (0);
61 }
62 56
63 while (!(UART(USR2) & USR2_TXFE)) 57 while (!(UART(USR2) & USR2_TXFE))
64 barrier(); 58 barrier();
@@ -68,11 +62,49 @@ static void putc(int ch)
68 62
69#define flush() do { } while (0) 63#define flush() do { } while (0)
70 64
71/* 65#define MX1_UART1_BASE_ADDR 0x00206000
72 * nothing to do 66#define MX25_UART1_BASE_ADDR 0x43f90000
73 */ 67#define MX2X_UART1_BASE_ADDR 0x1000a000
74#define arch_decomp_setup() 68#define MX3X_UART1_BASE_ADDR 0x43F90000
69#define MX3X_UART2_BASE_ADDR 0x43F94000
70
71static __inline__ void __arch_decomp_setup(unsigned long arch_id)
72{
73 switch (arch_id) {
74 case MACH_TYPE_MX1ADS:
75 case MACH_TYPE_SCB9328:
76 uart_base = MX1_UART1_BASE_ADDR;
77 break;
78 case MACH_TYPE_MX25_3DS:
79 uart_base = MX25_UART1_BASE_ADDR;
80 break;
81 case MACH_TYPE_IMX27LITE:
82 case MACH_TYPE_MX27_3DS:
83 case MACH_TYPE_MX27ADS:
84 case MACH_TYPE_PCM038:
85 case MACH_TYPE_MX21ADS:
86 uart_base = MX2X_UART1_BASE_ADDR;
87 break;
88 case MACH_TYPE_MX31LITE:
89 case MACH_TYPE_ARMADILLO5X0:
90 case MACH_TYPE_MX31MOBOARD:
91 case MACH_TYPE_QONG:
92 case MACH_TYPE_MX31_3DS:
93 case MACH_TYPE_PCM037:
94 case MACH_TYPE_MX31ADS:
95 case MACH_TYPE_MX35_3DS:
96 case MACH_TYPE_PCM043:
97 uart_base = MX3X_UART1_BASE_ADDR;
98 break;
99 case MACH_TYPE_MAGX_ZN5:
100 uart_base = MX3X_UART2_BASE_ADDR;
101 break;
102 default:
103 break;
104 }
105}
75 106
107#define arch_decomp_setup() __arch_decomp_setup(arch_id)
76#define arch_decomp_wdog() 108#define arch_decomp_wdog()
77 109
78#endif /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */ 110#endif /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c
index 77a078f9513f..851ca99bf1b1 100644
--- a/arch/arm/plat-mxc/iomux-v3.c
+++ b/arch/arm/plat-mxc/iomux-v3.c
@@ -29,7 +29,7 @@
29#include <asm/mach/map.h> 29#include <asm/mach/map.h>
30#include <mach/iomux-v3.h> 30#include <mach/iomux-v3.h>
31 31
32#define IOMUX_BASE IO_ADDRESS(IOMUXC_BASE_ADDR) 32static void __iomem *base;
33 33
34static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG]; 34static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG];
35 35
@@ -45,14 +45,14 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad)
45 if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map)) 45 if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map))
46 return -EBUSY; 46 return -EBUSY;
47 if (pad->mux_ctrl_ofs) 47 if (pad->mux_ctrl_ofs)
48 __raw_writel(pad->mux_mode, IOMUX_BASE + pad->mux_ctrl_ofs); 48 __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs);
49 49
50 if (pad->select_input_ofs) 50 if (pad->select_input_ofs)
51 __raw_writel(pad->select_input, 51 __raw_writel(pad->select_input,
52 IOMUX_BASE + pad->select_input_ofs); 52 base + pad->select_input_ofs);
53 53
54 if (!(pad->pad_ctrl & NO_PAD_CTRL)) 54 if (!(pad->pad_ctrl & NO_PAD_CTRL) && pad->pad_ctrl_ofs)
55 __raw_writel(pad->pad_ctrl, IOMUX_BASE + pad->pad_ctrl_ofs); 55 __raw_writel(pad->pad_ctrl, base + pad->pad_ctrl_ofs);
56 return 0; 56 return 0;
57} 57}
58EXPORT_SYMBOL(mxc_iomux_v3_setup_pad); 58EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
@@ -96,3 +96,8 @@ void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count)
96 } 96 }
97} 97}
98EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads); 98EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads);
99
100void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
101{
102 base = iomux_v3_base;
103}
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 8aee76304f8f..778ddfe57d89 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -44,7 +44,7 @@
44#define AVIC_FIPNDH 0x60 /* fast int pending high */ 44#define AVIC_FIPNDH 0x60 /* fast int pending high */
45#define AVIC_FIPNDL 0x64 /* fast int pending low */ 45#define AVIC_FIPNDL 0x64 /* fast int pending low */
46 46
47static void __iomem *avic_base; 47void __iomem *avic_base;
48 48
49int imx_irq_set_priority(unsigned char irq, unsigned char prio) 49int imx_irq_set_priority(unsigned char irq, unsigned char prio)
50{ 50{
@@ -113,11 +113,11 @@ static struct irq_chip mxc_avic_chip = {
113 * interrupts. It registers the interrupt enable and disable functions 113 * interrupts. It registers the interrupt enable and disable functions
114 * to the kernel for each interrupt source. 114 * to the kernel for each interrupt source.
115 */ 115 */
116void __init mxc_init_irq(void) 116void __init mxc_init_irq(void __iomem *irqbase)
117{ 117{
118 int i; 118 int i;
119 119
120 avic_base = IO_ADDRESS(AVIC_BASE_ADDR); 120 avic_base = irqbase;
121 121
122 /* put the AVIC into the reset value with 122 /* put the AVIC into the reset value with
123 * all interrupts disabled 123 * all interrupts disabled
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
index ae34198a79dd..5cdbd605ac05 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/arch/arm/plat-mxc/pwm.c
@@ -32,6 +32,7 @@
32#define MX3_PWMPR 0x10 /* PWM Period Register */ 32#define MX3_PWMPR 0x10 /* PWM Period Register */
33#define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) 33#define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
34#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16) 34#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
35#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
35#define MX3_PWMCR_EN (1 << 0) 36#define MX3_PWMCR_EN (1 << 0)
36 37
37 38
@@ -55,9 +56,11 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
55 if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) 56 if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
56 return -EINVAL; 57 return -EINVAL;
57 58
58 if (cpu_is_mx27() || cpu_is_mx3()) { 59 if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx25()) {
59 unsigned long long c; 60 unsigned long long c;
60 unsigned long period_cycles, duty_cycles, prescale; 61 unsigned long period_cycles, duty_cycles, prescale;
62 u32 cr;
63
61 c = clk_get_rate(pwm->clk); 64 c = clk_get_rate(pwm->clk);
62 c = c * period_ns; 65 c = c * period_ns;
63 do_div(c, 1000000000); 66 do_div(c, 1000000000);
@@ -72,9 +75,15 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
72 75
73 writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR); 76 writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR);
74 writel(period_cycles, pwm->mmio_base + MX3_PWMPR); 77 writel(period_cycles, pwm->mmio_base + MX3_PWMPR);
75 writel(MX3_PWMCR_PRESCALER(prescale - 1) | 78
76 MX3_PWMCR_CLKSRC_IPG_HIGH | MX3_PWMCR_EN, 79 cr = MX3_PWMCR_PRESCALER(prescale) | MX3_PWMCR_EN;
77 pwm->mmio_base + MX3_PWMCR); 80
81 if (cpu_is_mx25())
82 cr |= MX3_PWMCR_CLKSRC_IPG;
83 else
84 cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
85
86 writel(cr, pwm->mmio_base + MX3_PWMCR);
78 } else if (cpu_is_mx1() || cpu_is_mx21()) { 87 } else if (cpu_is_mx1() || cpu_is_mx21()) {
79 /* The PWM subsystem allows for exact frequencies. However, 88 /* The PWM subsystem allows for exact frequencies. However,
80 * I cannot connect a scope on my device to the PWM line and 89 * I cannot connect a scope on my device to the PWM line and
@@ -118,6 +127,8 @@ EXPORT_SYMBOL(pwm_enable);
118 127
119void pwm_disable(struct pwm_device *pwm) 128void pwm_disable(struct pwm_device *pwm)
120{ 129{
130 writel(0, pwm->mmio_base + MX3_PWMCR);
131
121 if (pwm->clk_enabled) { 132 if (pwm->clk_enabled) {
122 clk_disable(pwm->clk); 133 clk_disable(pwm->clk);
123 pwm->clk_enabled = 0; 134 pwm->clk_enabled = 0;
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 79c37577c916..97f42799fa58 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -27,32 +27,38 @@
27#include <linux/delay.h> 27#include <linux/delay.h>
28 28
29#include <mach/hardware.h> 29#include <mach/hardware.h>
30#include <mach/common.h>
30#include <asm/proc-fns.h> 31#include <asm/proc-fns.h>
31#include <asm/system.h> 32#include <asm/system.h>
32 33
33#ifdef CONFIG_ARCH_MX1 34static void __iomem *wdog_base;
34#define WDOG_WCR_REG IO_ADDRESS(WDT_BASE_ADDR)
35#define WDOG_WCR_ENABLE (1 << 0)
36#else
37#define WDOG_WCR_REG IO_ADDRESS(WDOG_BASE_ADDR)
38#define WDOG_WCR_ENABLE (1 << 2)
39#endif
40 35
41/* 36/*
42 * Reset the system. It is called by machine_restart(). 37 * Reset the system. It is called by machine_restart().
43 */ 38 */
44void arch_reset(char mode, const char *cmd) 39void arch_reset(char mode, const char *cmd)
45{ 40{
46 if (!cpu_is_mx1()) { 41 unsigned int wcr_enable;
42
43#ifdef CONFIG_ARCH_MXC91231
44 if (cpu_is_mxc91231()) {
45 mxc91231_arch_reset(mode, cmd);
46 return;
47 }
48#endif
49 if (cpu_is_mx1()) {
50 wcr_enable = (1 << 0);
51 } else {
47 struct clk *clk; 52 struct clk *clk;
48 53
49 clk = clk_get_sys("imx-wdt.0", NULL); 54 clk = clk_get_sys("imx-wdt.0", NULL);
50 if (!IS_ERR(clk)) 55 if (!IS_ERR(clk))
51 clk_enable(clk); 56 clk_enable(clk);
57 wcr_enable = (1 << 2);
52 } 58 }
53 59
54 /* Assert SRS signal */ 60 /* Assert SRS signal */
55 __raw_writew(WDOG_WCR_ENABLE, WDOG_WCR_REG); 61 __raw_writew(wcr_enable, wdog_base);
56 62
57 /* wait for reset to assert... */ 63 /* wait for reset to assert... */
58 mdelay(500); 64 mdelay(500);
@@ -65,3 +71,8 @@ void arch_reset(char mode, const char *cmd)
65 /* we'll take a jump through zero as a poor second */ 71 /* we'll take a jump through zero as a poor second */
66 cpu_reset(0); 72 cpu_reset(0);
67} 73}
74
75void mxc_arch_reset_init(void __iomem *base)
76{
77 wdog_base = base;
78}
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 88fb3a57e029..844567ee35fe 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -47,7 +47,7 @@
47#define MX2_TSTAT_CAPT (1 << 1) 47#define MX2_TSTAT_CAPT (1 << 1)
48#define MX2_TSTAT_COMP (1 << 0) 48#define MX2_TSTAT_COMP (1 << 0)
49 49
50/* MX31, MX35 */ 50/* MX31, MX35, MX25, MXC91231 */
51#define MX3_TCTL_WAITEN (1 << 3) 51#define MX3_TCTL_WAITEN (1 << 3)
52#define MX3_TCTL_CLK_IPG (1 << 6) 52#define MX3_TCTL_CLK_IPG (1 << 6)
53#define MX3_TCTL_FRR (1 << 9) 53#define MX3_TCTL_FRR (1 << 9)
@@ -66,7 +66,7 @@ static inline void gpt_irq_disable(void)
66{ 66{
67 unsigned int tmp; 67 unsigned int tmp;
68 68
69 if (cpu_is_mx3()) 69 if (cpu_is_mx3() || cpu_is_mx25())
70 __raw_writel(0, timer_base + MX3_IR); 70 __raw_writel(0, timer_base + MX3_IR);
71 else { 71 else {
72 tmp = __raw_readl(timer_base + MXC_TCTL); 72 tmp = __raw_readl(timer_base + MXC_TCTL);
@@ -76,7 +76,7 @@ static inline void gpt_irq_disable(void)
76 76
77static inline void gpt_irq_enable(void) 77static inline void gpt_irq_enable(void)
78{ 78{
79 if (cpu_is_mx3()) 79 if (cpu_is_mx3() || cpu_is_mx25())
80 __raw_writel(1<<0, timer_base + MX3_IR); 80 __raw_writel(1<<0, timer_base + MX3_IR);
81 else { 81 else {
82 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, 82 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
@@ -90,7 +90,7 @@ static void gpt_irq_acknowledge(void)
90 __raw_writel(0, timer_base + MX1_2_TSTAT); 90 __raw_writel(0, timer_base + MX1_2_TSTAT);
91 if (cpu_is_mx2()) 91 if (cpu_is_mx2())
92 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT); 92 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT);
93 if (cpu_is_mx3()) 93 if (cpu_is_mx3() || cpu_is_mx25())
94 __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT); 94 __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT);
95} 95}
96 96
@@ -117,7 +117,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
117{ 117{
118 unsigned int c = clk_get_rate(timer_clk); 118 unsigned int c = clk_get_rate(timer_clk);
119 119
120 if (cpu_is_mx3()) 120 if (cpu_is_mx3() || cpu_is_mx25())
121 clocksource_mxc.read = mx3_get_cycles; 121 clocksource_mxc.read = mx3_get_cycles;
122 122
123 clocksource_mxc.mult = clocksource_hz2mult(c, 123 clocksource_mxc.mult = clocksource_hz2mult(c,
@@ -180,7 +180,7 @@ static void mxc_set_mode(enum clock_event_mode mode,
180 180
181 if (mode != clockevent_mode) { 181 if (mode != clockevent_mode) {
182 /* Set event time into far-far future */ 182 /* Set event time into far-far future */
183 if (cpu_is_mx3()) 183 if (cpu_is_mx3() || cpu_is_mx25())
184 __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3, 184 __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3,
185 timer_base + MX3_TCMP); 185 timer_base + MX3_TCMP);
186 else 186 else
@@ -233,7 +233,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
233 struct clock_event_device *evt = &clockevent_mxc; 233 struct clock_event_device *evt = &clockevent_mxc;
234 uint32_t tstat; 234 uint32_t tstat;
235 235
236 if (cpu_is_mx3()) 236 if (cpu_is_mx3() || cpu_is_mx25())
237 tstat = __raw_readl(timer_base + MX3_TSTAT); 237 tstat = __raw_readl(timer_base + MX3_TSTAT);
238 else 238 else
239 tstat = __raw_readl(timer_base + MX1_2_TSTAT); 239 tstat = __raw_readl(timer_base + MX1_2_TSTAT);
@@ -264,7 +264,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
264{ 264{
265 unsigned int c = clk_get_rate(timer_clk); 265 unsigned int c = clk_get_rate(timer_clk);
266 266
267 if (cpu_is_mx3()) 267 if (cpu_is_mx3() || cpu_is_mx25())
268 clockevent_mxc.set_next_event = mx3_set_next_event; 268 clockevent_mxc.set_next_event = mx3_set_next_event;
269 269
270 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, 270 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
@@ -281,30 +281,13 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
281 return 0; 281 return 0;
282} 282}
283 283
284void __init mxc_timer_init(struct clk *timer_clk) 284void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
285{ 285{
286 uint32_t tctl_val; 286 uint32_t tctl_val;
287 int irq;
288 287
289 clk_enable(timer_clk); 288 clk_enable(timer_clk);
290 289
291 if (cpu_is_mx1()) { 290 timer_base = base;
292#ifdef CONFIG_ARCH_MX1
293 timer_base = IO_ADDRESS(TIM1_BASE_ADDR);
294 irq = TIM1_INT;
295#endif
296 } else if (cpu_is_mx2()) {
297#ifdef CONFIG_ARCH_MX2
298 timer_base = IO_ADDRESS(GPT1_BASE_ADDR);
299 irq = MXC_INT_GPT1;
300#endif
301 } else if (cpu_is_mx3()) {
302#ifdef CONFIG_ARCH_MX3
303 timer_base = IO_ADDRESS(GPT1_BASE_ADDR);
304 irq = MXC_INT_GPT;
305#endif
306 } else
307 BUG();
308 291
309 /* 292 /*
310 * Initialise to a known state (all timers off, and timing reset) 293 * Initialise to a known state (all timers off, and timing reset)
@@ -313,7 +296,7 @@ void __init mxc_timer_init(struct clk *timer_clk)
313 __raw_writel(0, timer_base + MXC_TCTL); 296 __raw_writel(0, timer_base + MXC_TCTL);
314 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ 297 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
315 298
316 if (cpu_is_mx3()) 299 if (cpu_is_mx3() || cpu_is_mx25())
317 tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; 300 tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN;
318 else 301 else
319 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; 302 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 06:24:38 -0500