aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-mxc
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r--arch/arm/plat-mxc/Kconfig30
-rw-r--r--arch/arm/plat-mxc/Makefile8
-rw-r--r--arch/arm/plat-mxc/audmux-v1.c14
-rw-r--r--arch/arm/plat-mxc/audmux-v2.c9
-rw-r--r--arch/arm/plat-mxc/clock.c1
-rw-r--r--arch/arm/plat-mxc/dma-mx1-mx2.c207
-rw-r--r--arch/arm/plat-mxc/ehci.c122
-rw-r--r--arch/arm/plat-mxc/gpio.c30
-rw-r--r--arch/arm/plat-mxc/include/mach/board-kzmarm11.h18
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31ads.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31moboard.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/clock.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S12
-rw-r--r--arch/arm/plat-mxc/include/mach/entry-macro.S34
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h9
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx1.h313
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx21.h210
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx25.h24
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx27.h372
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx2x.h425
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx3.h76
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx35.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx51.h326
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v1.h103
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v3.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux.h128
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h20
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h54
-rw-r--r--arch/arm/plat-mxc/include/mach/mtd-xip.h34
-rw-r--r--arch/arm/plat-mxc/include/mach/mx1.h395
-rw-r--r--arch/arm/plat-mxc/include/mach/mx21.h13
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h36
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h32
-rw-r--r--arch/arm/plat-mxc/include/mach/mx2x.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/mx31.h33
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h13
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3x.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/mx51.h454
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h20
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc91231.h58
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_ehci.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/ssi.h18
-rw-r--r--arch/arm/plat-mxc/include/mach/timex.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h3
-rw-r--r--arch/arm/plat-mxc/iomux-mx1-mx2.c157
-rw-r--r--arch/arm/plat-mxc/iomux-v1.c238
-rw-r--r--arch/arm/plat-mxc/time.c41
-rw-r--r--arch/arm/plat-mxc/tzic.c172
49 files changed, 2853 insertions, 1457 deletions
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 8b0a1ee039fa..7f7ad6f289bd 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -9,38 +9,43 @@ choice
9config ARCH_MX1 9config ARCH_MX1
10 bool "MX1-based" 10 bool "MX1-based"
11 select CPU_ARM920T 11 select CPU_ARM920T
12 select COMMON_CLKDEV 12 select IMX_HAVE_IOMUX_V1
13 help 13 help
14 This enables support for systems based on the Freescale i.MX1 family 14 This enables support for systems based on the Freescale i.MX1 family
15 15
16config ARCH_MX2 16config ARCH_MX2
17 bool "MX2-based" 17 bool "MX2-based"
18 select CPU_ARM926T 18 select CPU_ARM926T
19 select COMMON_CLKDEV 19 select IMX_HAVE_IOMUX_V1
20 help 20 help
21 This enables support for systems based on the Freescale i.MX2 family 21 This enables support for systems based on the Freescale i.MX2 family
22 22
23config ARCH_MX25 23config ARCH_MX25
24 bool "MX25-based" 24 bool "MX25-based"
25 select CPU_ARM926T 25 select CPU_ARM926T
26 select COMMON_CLKDEV 26 select ARCH_MXC_IOMUX_V3
27 select HAVE_FB_IMX
27 help 28 help
28 This enables support for systems based on the Freescale i.MX25 family 29 This enables support for systems based on the Freescale i.MX25 family
29 30
30config ARCH_MX3 31config ARCH_MX3
31 bool "MX3-based" 32 bool "MX3-based"
32 select CPU_V6 33 select CPU_V6
33 select COMMON_CLKDEV
34 help 34 help
35 This enables support for systems based on the Freescale i.MX3 family 35 This enables support for systems based on the Freescale i.MX3 family
36 36
37config ARCH_MXC91231 37config ARCH_MXC91231
38 bool "MXC91231-based" 38 bool "MXC91231-based"
39 select CPU_V6 39 select CPU_V6
40 select COMMON_CLKDEV
41 help 40 help
42 This enables support for systems based on the Freescale MXC91231 family 41 This enables support for systems based on the Freescale MXC91231 family
43 42
43config ARCH_MX5
44 bool "MX5-based"
45 select CPU_V7
46 help
47 This enables support for systems based on the Freescale i.MX51 family
48
44endchoice 49endchoice
45 50
46source "arch/arm/mach-mx1/Kconfig" 51source "arch/arm/mach-mx1/Kconfig"
@@ -48,12 +53,12 @@ source "arch/arm/mach-mx2/Kconfig"
48source "arch/arm/mach-mx3/Kconfig" 53source "arch/arm/mach-mx3/Kconfig"
49source "arch/arm/mach-mx25/Kconfig" 54source "arch/arm/mach-mx25/Kconfig"
50source "arch/arm/mach-mxc91231/Kconfig" 55source "arch/arm/mach-mxc91231/Kconfig"
56source "arch/arm/mach-mx5/Kconfig"
51 57
52endmenu 58endmenu
53 59
54config MXC_IRQ_PRIOR 60config MXC_IRQ_PRIOR
55 bool "Use IRQ priority" 61 bool "Use IRQ priority"
56 depends on ARCH_MXC
57 help 62 help
58 Select this if you want to use prioritized IRQ handling. 63 Select this if you want to use prioritized IRQ handling.
59 This feature prevents higher priority ISR to be interrupted 64 This feature prevents higher priority ISR to be interrupted
@@ -62,9 +67,16 @@ config MXC_IRQ_PRIOR
62 requirements for timing. 67 requirements for timing.
63 Say N here, unless you have a specialized requirement. 68 Say N here, unless you have a specialized requirement.
64 69
70config MXC_TZIC
71 bool "Enable TrustZone Interrupt Controller"
72 depends on ARCH_MX51
73 help
74 This will be automatically selected for all processors
75 containing this interrupt controller.
76 Say N here only if you are really sure.
77
65config MXC_PWM 78config MXC_PWM
66 tristate "Enable PWM driver" 79 tristate "Enable PWM driver"
67 depends on ARCH_MXC
68 select HAVE_PWM 80 select HAVE_PWM
69 help 81 help
70 Enable support for the i.MX PWM controller(s). 82 Enable support for the i.MX PWM controller(s).
@@ -74,7 +86,9 @@ config MXC_ULPI
74 86
75config ARCH_HAS_RNGA 87config ARCH_HAS_RNGA
76 bool 88 bool
77 depends on ARCH_MXC 89
90config IMX_HAVE_IOMUX_V1
91 bool
78 92
79config ARCH_MXC_IOMUX_V3 93config ARCH_MXC_IOMUX_V3
80 bool 94 bool
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 996cbac6932c..a72a5e4ca20e 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -5,8 +5,12 @@
5# Common support 5# Common support
6obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o 6obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
7 7
8obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o 8# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)
9obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o 9obj-$(CONFIG_MXC_TZIC) += tzic.o
10
11obj-$(CONFIG_ARCH_MX1) += dma-mx1-mx2.o
12obj-$(CONFIG_ARCH_MX2) += dma-mx1-mx2.o
13obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
10obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o 14obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
11obj-$(CONFIG_MXC_PWM) += pwm.o 15obj-$(CONFIG_MXC_PWM) += pwm.o
12obj-$(CONFIG_USB_EHCI_MXC) += ehci.o 16obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c
index da6387dcdf21..b62917ca3f95 100644
--- a/arch/arm/plat-mxc/audmux-v1.c
+++ b/arch/arm/plat-mxc/audmux-v1.c
@@ -50,8 +50,18 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port);
50 50
51static int mxc_audmux_v1_init(void) 51static int mxc_audmux_v1_init(void)
52{ 52{
53 if (cpu_is_mx27() || cpu_is_mx21()) 53#ifdef CONFIG_MACH_MX21
54 audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR); 54 if (cpu_is_mx21())
55 audmux_base = MX21_IO_ADDRESS(MX21_AUDMUX_BASE_ADDR);
56 else
57#endif
58#ifdef CONFIG_MACH_MX27
59 if (cpu_is_mx27())
60 audmux_base = MX27_IO_ADDRESS(MX27_AUDMUX_BASE_ADDR);
61 else
62#endif
63 (void)0;
64
55 return 0; 65 return 0;
56} 66}
57 67
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index b06954a84436..d983cd6c788c 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -190,7 +190,10 @@ static int mxc_audmux_v2_init(void)
190{ 190{
191 int ret; 191 int ret;
192 192
193 if (cpu_is_mx35()) { 193 if (cpu_is_mx31())
194 audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
195
196 else if (cpu_is_mx35()) {
194 audmux_clk = clk_get(NULL, "audmux"); 197 audmux_clk = clk_get(NULL, "audmux");
195 if (IS_ERR(audmux_clk)) { 198 if (IS_ERR(audmux_clk)) {
196 ret = PTR_ERR(audmux_clk); 199 ret = PTR_ERR(audmux_clk);
@@ -198,11 +201,9 @@ static int mxc_audmux_v2_init(void)
198 ret); 201 ret);
199 return ret; 202 return ret;
200 } 203 }
204 audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
201 } 205 }
202 206
203 if (cpu_is_mx31() || cpu_is_mx35())
204 audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR);
205
206 audmux_debugfs_init(); 207 audmux_debugfs_init();
207 208
208 return 0; 209 return 0;
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 9e8fbd57495c..323ff8ccc877 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -56,6 +56,7 @@ static void __clk_disable(struct clk *clk)
56 __clk_disable(clk->parent); 56 __clk_disable(clk->parent);
57 __clk_disable(clk->secondary); 57 __clk_disable(clk->secondary);
58 58
59 WARN_ON(!clk->usecount);
59 if (!(--clk->usecount) && clk->disable) 60 if (!(--clk->usecount) && clk->disable)
60 clk->disable(clk); 61 clk->disable(clk);
61} 62}
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c
index 9c1b3f9c4f4d..e16014b0d13c 100644
--- a/arch/arm/plat-mxc/dma-mx1-mx2.c
+++ b/arch/arm/plat-mxc/dma-mx1-mx2.c
@@ -128,6 +128,18 @@ struct imx_dma_channel {
128 int hw_chaining; 128 int hw_chaining;
129}; 129};
130 130
131static void __iomem *imx_dmav1_baseaddr;
132
133static void imx_dmav1_writel(unsigned val, unsigned offset)
134{
135 __raw_writel(val, imx_dmav1_baseaddr + offset);
136}
137
138static unsigned imx_dmav1_readl(unsigned offset)
139{
140 return __raw_readl(imx_dmav1_baseaddr + offset);
141}
142
131static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; 143static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
132 144
133static struct clk *dma_clk; 145static struct clk *dma_clk;
@@ -140,7 +152,6 @@ static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
140 return 0; 152 return 0;
141} 153}
142 154
143
144/* 155/*
145 * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation 156 * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
146 */ 157 */
@@ -160,17 +171,17 @@ static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
160 imxdma->resbytes -= now; 171 imxdma->resbytes -= now;
161 172
162 if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ) 173 if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
163 __raw_writel(sg->dma_address, DMA_BASE + DMA_DAR(channel)); 174 imx_dmav1_writel(sg->dma_address, DMA_DAR(channel));
164 else 175 else
165 __raw_writel(sg->dma_address, DMA_BASE + DMA_SAR(channel)); 176 imx_dmav1_writel(sg->dma_address, DMA_SAR(channel));
166 177
167 __raw_writel(now, DMA_BASE + DMA_CNTR(channel)); 178 imx_dmav1_writel(now, DMA_CNTR(channel));
168 179
169 pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, " 180 pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
170 "size 0x%08x\n", channel, 181 "size 0x%08x\n", channel,
171 __raw_readl(DMA_BASE + DMA_DAR(channel)), 182 imx_dmav1_readl(DMA_DAR(channel)),
172 __raw_readl(DMA_BASE + DMA_SAR(channel)), 183 imx_dmav1_readl(DMA_SAR(channel)),
173 __raw_readl(DMA_BASE + DMA_CNTR(channel))); 184 imx_dmav1_readl(DMA_CNTR(channel)));
174 185
175 return now; 186 return now;
176} 187}
@@ -218,27 +229,26 @@ imx_dma_setup_single(int channel, dma_addr_t dma_address,
218 channel, __func__, (unsigned int)dma_address, 229 channel, __func__, (unsigned int)dma_address,
219 dma_length, dev_addr); 230 dma_length, dev_addr);
220 231
221 __raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel)); 232 imx_dmav1_writel(dev_addr, DMA_SAR(channel));
222 __raw_writel(dma_address, DMA_BASE + DMA_DAR(channel)); 233 imx_dmav1_writel(dma_address, DMA_DAR(channel));
223 __raw_writel(imxdma->ccr_from_device, 234 imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
224 DMA_BASE + DMA_CCR(channel));
225 } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { 235 } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
226 pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d " 236 pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
227 "dev_addr=0x%08x for write\n", 237 "dev_addr=0x%08x for write\n",
228 channel, __func__, (unsigned int)dma_address, 238 channel, __func__, (unsigned int)dma_address,
229 dma_length, dev_addr); 239 dma_length, dev_addr);
230 240
231 __raw_writel(dma_address, DMA_BASE + DMA_SAR(channel)); 241 imx_dmav1_writel(dma_address, DMA_SAR(channel));
232 __raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel)); 242 imx_dmav1_writel(dev_addr, DMA_DAR(channel));
233 __raw_writel(imxdma->ccr_to_device, 243 imx_dmav1_writel(imxdma->ccr_to_device,
234 DMA_BASE + DMA_CCR(channel)); 244 DMA_CCR(channel));
235 } else { 245 } else {
236 printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n", 246 printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
237 channel); 247 channel);
238 return -EINVAL; 248 return -EINVAL;
239 } 249 }
240 250
241 __raw_writel(dma_length, DMA_BASE + DMA_CNTR(channel)); 251 imx_dmav1_writel(dma_length, DMA_CNTR(channel));
242 252
243 return 0; 253 return 0;
244} 254}
@@ -316,17 +326,15 @@ imx_dma_setup_sg(int channel,
316 "dev_addr=0x%08x for read\n", 326 "dev_addr=0x%08x for read\n",
317 channel, __func__, sg, sgcount, dma_length, dev_addr); 327 channel, __func__, sg, sgcount, dma_length, dev_addr);
318 328
319 __raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel)); 329 imx_dmav1_writel(dev_addr, DMA_SAR(channel));
320 __raw_writel(imxdma->ccr_from_device, 330 imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
321 DMA_BASE + DMA_CCR(channel));
322 } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { 331 } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
323 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d " 332 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
324 "dev_addr=0x%08x for write\n", 333 "dev_addr=0x%08x for write\n",
325 channel, __func__, sg, sgcount, dma_length, dev_addr); 334 channel, __func__, sg, sgcount, dma_length, dev_addr);
326 335
327 __raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel)); 336 imx_dmav1_writel(dev_addr, DMA_DAR(channel));
328 __raw_writel(imxdma->ccr_to_device, 337 imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel));
329 DMA_BASE + DMA_CCR(channel));
330 } else { 338 } else {
331 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n", 339 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
332 channel); 340 channel);
@@ -360,7 +368,7 @@ imx_dma_config_channel(int channel, unsigned int config_port,
360 imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq; 368 imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
361 imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq; 369 imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
362 370
363 __raw_writel(dmareq, DMA_BASE + DMA_RSSR(channel)); 371 imx_dmav1_writel(dmareq, DMA_RSSR(channel));
364 372
365 return 0; 373 return 0;
366} 374}
@@ -368,7 +376,7 @@ EXPORT_SYMBOL(imx_dma_config_channel);
368 376
369void imx_dma_config_burstlen(int channel, unsigned int burstlen) 377void imx_dma_config_burstlen(int channel, unsigned int burstlen)
370{ 378{
371 __raw_writel(burstlen, DMA_BASE + DMA_BLR(channel)); 379 imx_dmav1_writel(burstlen, DMA_BLR(channel));
372} 380}
373EXPORT_SYMBOL(imx_dma_config_burstlen); 381EXPORT_SYMBOL(imx_dma_config_burstlen);
374 382
@@ -398,7 +406,7 @@ imx_dma_setup_handlers(int channel,
398 } 406 }
399 407
400 local_irq_save(flags); 408 local_irq_save(flags);
401 __raw_writel(1 << channel, DMA_BASE + DMA_DISR); 409 imx_dmav1_writel(1 << channel, DMA_DISR);
402 imxdma->irq_handler = irq_handler; 410 imxdma->irq_handler = irq_handler;
403 imxdma->err_handler = err_handler; 411 imxdma->err_handler = err_handler;
404 imxdma->data = data; 412 imxdma->data = data;
@@ -462,22 +470,21 @@ void imx_dma_enable(int channel)
462 470
463 local_irq_save(flags); 471 local_irq_save(flags);
464 472
465 __raw_writel(1 << channel, DMA_BASE + DMA_DISR); 473 imx_dmav1_writel(1 << channel, DMA_DISR);
466 __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) & ~(1 << channel), 474 imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
467 DMA_BASE + DMA_DIMR); 475 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
468 __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) | CCR_CEN | 476 CCR_ACRPT, DMA_CCR(channel));
469 CCR_ACRPT,
470 DMA_BASE + DMA_CCR(channel));
471 477
472#ifdef CONFIG_ARCH_MX2 478#ifdef CONFIG_ARCH_MX2
473 if (imxdma->sg && imx_dma_hw_chain(imxdma)) { 479 if ((cpu_is_mx21() || cpu_is_mx27()) &&
480 imxdma->sg && imx_dma_hw_chain(imxdma)) {
474 imxdma->sg = sg_next(imxdma->sg); 481 imxdma->sg = sg_next(imxdma->sg);
475 if (imxdma->sg) { 482 if (imxdma->sg) {
476 u32 tmp; 483 u32 tmp;
477 imx_dma_sg_next(channel, imxdma->sg); 484 imx_dma_sg_next(channel, imxdma->sg);
478 tmp = __raw_readl(DMA_BASE + DMA_CCR(channel)); 485 tmp = imx_dmav1_readl(DMA_CCR(channel));
479 __raw_writel(tmp | CCR_RPT | CCR_ACRPT, 486 imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
480 DMA_BASE + DMA_CCR(channel)); 487 DMA_CCR(channel));
481 } 488 }
482 } 489 }
483#endif 490#endif
@@ -502,11 +509,10 @@ void imx_dma_disable(int channel)
502 del_timer(&imxdma->watchdog); 509 del_timer(&imxdma->watchdog);
503 510
504 local_irq_save(flags); 511 local_irq_save(flags);
505 __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) | (1 << channel), 512 imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
506 DMA_BASE + DMA_DIMR); 513 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
507 __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) & ~CCR_CEN, 514 DMA_CCR(channel));
508 DMA_BASE + DMA_CCR(channel)); 515 imx_dmav1_writel(1 << channel, DMA_DISR);
509 __raw_writel(1 << channel, DMA_BASE + DMA_DISR);
510 imxdma->in_use = 0; 516 imxdma->in_use = 0;
511 local_irq_restore(flags); 517 local_irq_restore(flags);
512} 518}
@@ -517,7 +523,7 @@ static void imx_dma_watchdog(unsigned long chno)
517{ 523{
518 struct imx_dma_channel *imxdma = &imx_dma_channels[chno]; 524 struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
519 525
520 __raw_writel(0, DMA_BASE + DMA_CCR(chno)); 526 imx_dmav1_writel(0, DMA_CCR(chno));
521 imxdma->in_use = 0; 527 imxdma->in_use = 0;
522 imxdma->sg = NULL; 528 imxdma->sg = NULL;
523 529
@@ -533,17 +539,17 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id)
533 unsigned int err_mask; 539 unsigned int err_mask;
534 int errcode; 540 int errcode;
535 541
536 disr = __raw_readl(DMA_BASE + DMA_DISR); 542 disr = imx_dmav1_readl(DMA_DISR);
537 543
538 err_mask = __raw_readl(DMA_BASE + DMA_DBTOSR) | 544 err_mask = imx_dmav1_readl(DMA_DBTOSR) |
539 __raw_readl(DMA_BASE + DMA_DRTOSR) | 545 imx_dmav1_readl(DMA_DRTOSR) |
540 __raw_readl(DMA_BASE + DMA_DSESR) | 546 imx_dmav1_readl(DMA_DSESR) |
541 __raw_readl(DMA_BASE + DMA_DBOSR); 547 imx_dmav1_readl(DMA_DBOSR);
542 548
543 if (!err_mask) 549 if (!err_mask)
544 return IRQ_HANDLED; 550 return IRQ_HANDLED;
545 551
546 __raw_writel(disr & err_mask, DMA_BASE + DMA_DISR); 552 imx_dmav1_writel(disr & err_mask, DMA_DISR);
547 553
548 for (i = 0; i < IMX_DMA_CHANNELS; i++) { 554 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
549 if (!(err_mask & (1 << i))) 555 if (!(err_mask & (1 << i)))
@@ -551,20 +557,20 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id)
551 imxdma = &imx_dma_channels[i]; 557 imxdma = &imx_dma_channels[i];
552 errcode = 0; 558 errcode = 0;
553 559
554 if (__raw_readl(DMA_BASE + DMA_DBTOSR) & (1 << i)) { 560 if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
555 __raw_writel(1 << i, DMA_BASE + DMA_DBTOSR); 561 imx_dmav1_writel(1 << i, DMA_DBTOSR);
556 errcode |= IMX_DMA_ERR_BURST; 562 errcode |= IMX_DMA_ERR_BURST;
557 } 563 }
558 if (__raw_readl(DMA_BASE + DMA_DRTOSR) & (1 << i)) { 564 if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
559 __raw_writel(1 << i, DMA_BASE + DMA_DRTOSR); 565 imx_dmav1_writel(1 << i, DMA_DRTOSR);
560 errcode |= IMX_DMA_ERR_REQUEST; 566 errcode |= IMX_DMA_ERR_REQUEST;
561 } 567 }
562 if (__raw_readl(DMA_BASE + DMA_DSESR) & (1 << i)) { 568 if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
563 __raw_writel(1 << i, DMA_BASE + DMA_DSESR); 569 imx_dmav1_writel(1 << i, DMA_DSESR);
564 errcode |= IMX_DMA_ERR_TRANSFER; 570 errcode |= IMX_DMA_ERR_TRANSFER;
565 } 571 }
566 if (__raw_readl(DMA_BASE + DMA_DBOSR) & (1 << i)) { 572 if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
567 __raw_writel(1 << i, DMA_BASE + DMA_DBOSR); 573 imx_dmav1_writel(1 << i, DMA_DBOSR);
568 errcode |= IMX_DMA_ERR_BUFFER; 574 errcode |= IMX_DMA_ERR_BUFFER;
569 } 575 }
570 if (imxdma->name && imxdma->err_handler) { 576 if (imxdma->name && imxdma->err_handler) {
@@ -607,7 +613,7 @@ static void dma_irq_handle_channel(int chno)
607 if (imxdma->sg) { 613 if (imxdma->sg) {
608 imx_dma_sg_next(chno, imxdma->sg); 614 imx_dma_sg_next(chno, imxdma->sg);
609 615
610 tmp = __raw_readl(DMA_BASE + DMA_CCR(chno)); 616 tmp = imx_dmav1_readl(DMA_CCR(chno));
611 617
612 if (imx_dma_hw_chain(imxdma)) { 618 if (imx_dma_hw_chain(imxdma)) {
613 /* FIXME: The timeout should probably be 619 /* FIXME: The timeout should probably be
@@ -617,15 +623,13 @@ static void dma_irq_handle_channel(int chno)
617 jiffies + msecs_to_jiffies(500)); 623 jiffies + msecs_to_jiffies(500));
618 624
619 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; 625 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
620 __raw_writel(tmp, DMA_BASE + 626 imx_dmav1_writel(tmp, DMA_CCR(chno));
621 DMA_CCR(chno));
622 } else { 627 } else {
623 __raw_writel(tmp & ~CCR_CEN, DMA_BASE + 628 imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
624 DMA_CCR(chno));
625 tmp |= CCR_CEN; 629 tmp |= CCR_CEN;
626 } 630 }
627 631
628 __raw_writel(tmp, DMA_BASE + DMA_CCR(chno)); 632 imx_dmav1_writel(tmp, DMA_CCR(chno));
629 633
630 if (imxdma->prog_handler) 634 if (imxdma->prog_handler)
631 imxdma->prog_handler(chno, imxdma->data, 635 imxdma->prog_handler(chno, imxdma->data,
@@ -640,7 +644,7 @@ static void dma_irq_handle_channel(int chno)
640 } 644 }
641 } 645 }
642 646
643 __raw_writel(0, DMA_BASE + DMA_CCR(chno)); 647 imx_dmav1_writel(0, DMA_CCR(chno));
644 imxdma->in_use = 0; 648 imxdma->in_use = 0;
645 if (imxdma->irq_handler) 649 if (imxdma->irq_handler)
646 imxdma->irq_handler(chno, imxdma->data); 650 imxdma->irq_handler(chno, imxdma->data);
@@ -651,15 +655,16 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
651 int i, disr; 655 int i, disr;
652 656
653#ifdef CONFIG_ARCH_MX2 657#ifdef CONFIG_ARCH_MX2
654 dma_err_handler(irq, dev_id); 658 if (cpu_is_mx21() || cpu_is_mx27())
659 dma_err_handler(irq, dev_id);
655#endif 660#endif
656 661
657 disr = __raw_readl(DMA_BASE + DMA_DISR); 662 disr = imx_dmav1_readl(DMA_DISR);
658 663
659 pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n", 664 pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
660 disr); 665 disr);
661 666
662 __raw_writel(disr, DMA_BASE + DMA_DISR); 667 imx_dmav1_writel(disr, DMA_DISR);
663 for (i = 0; i < IMX_DMA_CHANNELS; i++) { 668 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
664 if (disr & (1 << i)) 669 if (disr & (1 << i))
665 dma_irq_handle_channel(i); 670 dma_irq_handle_channel(i);
@@ -699,17 +704,19 @@ int imx_dma_request(int channel, const char *name)
699 local_irq_restore(flags); /* request_irq() can block */ 704 local_irq_restore(flags); /* request_irq() can block */
700 705
701#ifdef CONFIG_ARCH_MX2 706#ifdef CONFIG_ARCH_MX2
702 ret = request_irq(MXC_INT_DMACH0 + channel, dma_irq_handler, 0, "DMA", 707 if (cpu_is_mx21() || cpu_is_mx27()) {
703 NULL); 708 ret = request_irq(MX2x_INT_DMACH0 + channel,
704 if (ret) { 709 dma_irq_handler, 0, "DMA", NULL);
705 imxdma->name = NULL; 710 if (ret) {
706 printk(KERN_CRIT "Can't register IRQ %d for DMA channel %d\n", 711 imxdma->name = NULL;
707 MXC_INT_DMACH0 + channel, channel); 712 pr_crit("Can't register IRQ %d for DMA channel %d\n",
708 return ret; 713 MX2x_INT_DMACH0 + channel, channel);
714 return ret;
715 }
716 init_timer(&imxdma->watchdog);
717 imxdma->watchdog.function = &imx_dma_watchdog;
718 imxdma->watchdog.data = channel;
709 } 719 }
710 init_timer(&imxdma->watchdog);
711 imxdma->watchdog.function = &imx_dma_watchdog;
712 imxdma->watchdog.data = channel;
713#endif 720#endif
714 721
715 return ret; 722 return ret;
@@ -738,7 +745,8 @@ void imx_dma_free(int channel)
738 imxdma->name = NULL; 745 imxdma->name = NULL;
739 746
740#ifdef CONFIG_ARCH_MX2 747#ifdef CONFIG_ARCH_MX2
741 free_irq(MXC_INT_DMACH0 + channel, NULL); 748 if (cpu_is_mx21() || cpu_is_mx27())
749 free_irq(MX2x_INT_DMACH0 + channel, NULL);
742#endif 750#endif
743 751
744 local_irq_restore(flags); 752 local_irq_restore(flags);
@@ -796,34 +804,53 @@ static int __init imx_dma_init(void)
796 int ret = 0; 804 int ret = 0;
797 int i; 805 int i;
798 806
807#ifdef CONFIG_ARCH_MX1
808 if (cpu_is_mx1())
809 imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
810 else
811#endif
812#ifdef CONFIG_MACH_MX21
813 if (cpu_is_mx21())
814 imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
815 else
816#endif
817#ifdef CONFIG_MACH_MX27
818 if (cpu_is_mx27())
819 imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
820 else
821#endif
822 BUG();
823
799 dma_clk = clk_get(NULL, "dma"); 824 dma_clk = clk_get(NULL, "dma");
800 clk_enable(dma_clk); 825 clk_enable(dma_clk);
801 826
802 /* reset DMA module */ 827 /* reset DMA module */
803 __raw_writel(DCR_DRST, DMA_BASE + DMA_DCR); 828 imx_dmav1_writel(DCR_DRST, DMA_DCR);
804 829
805#ifdef CONFIG_ARCH_MX1 830#ifdef CONFIG_ARCH_MX1
806 ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL); 831 if (cpu_is_mx1()) {
807 if (ret) { 832 ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
808 printk(KERN_CRIT "Wow! Can't register IRQ for DMA\n"); 833 if (ret) {
809 return ret; 834 pr_crit("Wow! Can't register IRQ for DMA\n");
810 } 835 return ret;
836 }
811 837
812 ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL); 838 ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL);
813 if (ret) { 839 if (ret) {
814 printk(KERN_CRIT "Wow! Can't register ERRIRQ for DMA\n"); 840 pr_crit("Wow! Can't register ERRIRQ for DMA\n");
815 free_irq(DMA_INT, NULL); 841 free_irq(MX1_DMA_INT, NULL);
816 return ret; 842 return ret;
843 }
817 } 844 }
818#endif 845#endif
819 /* enable DMA module */ 846 /* enable DMA module */
820 __raw_writel(DCR_DEN, DMA_BASE + DMA_DCR); 847 imx_dmav1_writel(DCR_DEN, DMA_DCR);
821 848
822 /* clear all interrupts */ 849 /* clear all interrupts */
823 __raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DISR); 850 imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
824 851
825 /* disable interrupts */ 852 /* disable interrupts */
826 __raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DIMR); 853 imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
827 854
828 for (i = 0; i < IMX_DMA_CHANNELS; i++) { 855 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
829 imx_dma_channels[i].sg = NULL; 856 imx_dma_channels[i].sg = NULL;
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 41599be882e8..cb0b63874482 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -25,25 +25,37 @@
25#define USBCTRL_OTGBASE_OFFSET 0x600 25#define USBCTRL_OTGBASE_OFFSET 0x600
26 26
27#define MX31_OTG_SIC_SHIFT 29 27#define MX31_OTG_SIC_SHIFT 29
28#define MX31_OTG_SIC_MASK (0xf << MX31_OTG_SIC_SHIFT) 28#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
29#define MX31_OTG_PM_BIT (1 << 24) 29#define MX31_OTG_PM_BIT (1 << 24)
30 30
31#define MX31_H2_SIC_SHIFT 21 31#define MX31_H2_SIC_SHIFT 21
32#define MX31_H2_SIC_MASK (0xf << MX31_H2_SIC_SHIFT) 32#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
33#define MX31_H2_PM_BIT (1 << 16) 33#define MX31_H2_PM_BIT (1 << 16)
34#define MX31_H2_DT_BIT (1 << 5) 34#define MX31_H2_DT_BIT (1 << 5)
35 35
36#define MX31_H1_SIC_SHIFT 13 36#define MX31_H1_SIC_SHIFT 13
37#define MX31_H1_SIC_MASK (0xf << MX31_H1_SIC_SHIFT) 37#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
38#define MX31_H1_PM_BIT (1 << 8) 38#define MX31_H1_PM_BIT (1 << 8)
39#define MX31_H1_DT_BIT (1 << 4) 39#define MX31_H1_DT_BIT (1 << 4)
40 40
41#define MX35_OTG_SIC_SHIFT 29
42#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
43#define MX35_OTG_PM_BIT (1 << 24)
44
45#define MX35_H1_SIC_SHIFT 21
46#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
47#define MX35_H1_PM_BIT (1 << 8)
48#define MX35_H1_IPPUE_UP_BIT (1 << 7)
49#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
50#define MX35_H1_TLL_BIT (1 << 5)
51#define MX35_H1_USBTE_BIT (1 << 4)
52
41int mxc_set_usbcontrol(int port, unsigned int flags) 53int mxc_set_usbcontrol(int port, unsigned int flags)
42{ 54{
43 unsigned int v; 55 unsigned int v;
44 56#ifdef CONFIG_ARCH_MX3
45 if (cpu_is_mx31()) { 57 if (cpu_is_mx31()) {
46 v = readl(IO_ADDRESS(MX31_OTG_BASE_ADDR + 58 v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
47 USBCTRL_OTGBASE_OFFSET)); 59 USBCTRL_OTGBASE_OFFSET));
48 60
49 switch (port) { 61 switch (port) {
@@ -51,15 +63,15 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
51 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); 63 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
52 v |= (flags & MXC_EHCI_INTERFACE_MASK) 64 v |= (flags & MXC_EHCI_INTERFACE_MASK)
53 << MX31_OTG_SIC_SHIFT; 65 << MX31_OTG_SIC_SHIFT;
54 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 66 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
55 v |= MX31_OTG_PM_BIT; 67 v |= MX31_OTG_PM_BIT;
56 68
57 break; 69 break;
58 case 1: /* H1 port */ 70 case 1: /* H1 port */
59 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT); 71 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
60 v |= (flags & MXC_EHCI_INTERFACE_MASK) 72 v |= (flags & MXC_EHCI_INTERFACE_MASK)
61 << MX31_H1_SIC_SHIFT; 73 << MX31_H1_SIC_SHIFT;
62 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 74 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
63 v |= MX31_H1_PM_BIT; 75 v |= MX31_H1_PM_BIT;
64 76
65 if (!(flags & MXC_EHCI_TTL_ENABLED)) 77 if (!(flags & MXC_EHCI_TTL_ENABLED))
@@ -67,7 +79,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
67 79
68 break; 80 break;
69 case 2: /* H2 port */ 81 case 2: /* H2 port */
70 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT); 82 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
71 v |= (flags & MXC_EHCI_INTERFACE_MASK) 83 v |= (flags & MXC_EHCI_INTERFACE_MASK)
72 << MX31_H2_SIC_SHIFT; 84 << MX31_H2_SIC_SHIFT;
73 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) 85 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
@@ -77,13 +89,103 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
77 v |= MX31_H2_DT_BIT; 89 v |= MX31_H2_DT_BIT;
78 90
79 break; 91 break;
92 default:
93 return -EINVAL;
80 } 94 }
81 95
82 writel(v, IO_ADDRESS(MX31_OTG_BASE_ADDR + 96 writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
83 USBCTRL_OTGBASE_OFFSET)); 97 USBCTRL_OTGBASE_OFFSET));
84 return 0; 98 return 0;
85 } 99 }
86 100
101 if (cpu_is_mx35()) {
102 v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
103 USBCTRL_OTGBASE_OFFSET));
104
105 switch (port) {
106 case 0: /* OTG port */
107 v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
108 v |= (flags & MXC_EHCI_INTERFACE_MASK)
109 << MX35_OTG_SIC_SHIFT;
110 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
111 v |= MX35_OTG_PM_BIT;
112
113 break;
114 case 1: /* H1 port */
115 v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
116 MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
117 v |= (flags & MXC_EHCI_INTERFACE_MASK)
118 << MX35_H1_SIC_SHIFT;
119 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
120 v |= MX35_H1_PM_BIT;
121
122 if (!(flags & MXC_EHCI_TTL_ENABLED))
123 v |= MX35_H1_TLL_BIT;
124
125 if (flags & MXC_EHCI_INTERNAL_PHY)
126 v |= MX35_H1_USBTE_BIT;
127
128 if (flags & MXC_EHCI_IPPUE_DOWN)
129 v |= MX35_H1_IPPUE_DOWN_BIT;
130
131 if (flags & MXC_EHCI_IPPUE_UP)
132 v |= MX35_H1_IPPUE_UP_BIT;
133
134 break;
135 default:
136 return -EINVAL;
137 }
138
139 writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
140 USBCTRL_OTGBASE_OFFSET));
141 return 0;
142 }
143#endif /* CONFIG_ARCH_MX3 */
144#ifdef CONFIG_MACH_MX27
145 if (cpu_is_mx27()) {
146 /* On i.MX27 we can use the i.MX31 USBCTRL bits, they
147 * are identical
148 */
149 v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR +
150 USBCTRL_OTGBASE_OFFSET));
151 switch (port) {
152 case 0: /* OTG port */
153 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
154 v |= (flags & MXC_EHCI_INTERFACE_MASK)
155 << MX31_OTG_SIC_SHIFT;
156 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
157 v |= MX31_OTG_PM_BIT;
158 break;
159 case 1: /* H1 port */
160 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
161 v |= (flags & MXC_EHCI_INTERFACE_MASK)
162 << MX31_H1_SIC_SHIFT;
163 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
164 v |= MX31_H1_PM_BIT;
165
166 if (!(flags & MXC_EHCI_TTL_ENABLED))
167 v |= MX31_H1_DT_BIT;
168
169 break;
170 case 2: /* H2 port */
171 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
172 v |= (flags & MXC_EHCI_INTERFACE_MASK)
173 << MX31_H2_SIC_SHIFT;
174 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
175 v |= MX31_H2_PM_BIT;
176
177 if (!(flags & MXC_EHCI_TTL_ENABLED))
178 v |= MX31_H2_DT_BIT;
179
180 break;
181 default:
182 return -EINVAL;
183 }
184 writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR +
185 USBCTRL_OTGBASE_OFFSET));
186 return 0;
187 }
188#endif /* CONFIG_MACH_MX27 */
87 printk(KERN_WARNING 189 printk(KERN_WARNING
88 "%s() unable to setup USBCONTROL for this CPU\n", __func__); 190 "%s() unable to setup USBCONTROL for this CPU\n", __func__);
89 return -EINVAL; 191 return -EINVAL;
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index d65ebe303b9f..70b23893f094 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -140,16 +140,13 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
140 val = __raw_readl(reg); 140 val = __raw_readl(reg);
141 edge = (val >> (bit << 1)) & 3; 141 edge = (val >> (bit << 1)) & 3;
142 val &= ~(0x3 << (bit << 1)); 142 val &= ~(0x3 << (bit << 1));
143 switch (edge) { 143 if (edge == GPIO_INT_HIGH_LEV) {
144 case GPIO_INT_HIGH_LEV:
145 edge = GPIO_INT_LOW_LEV; 144 edge = GPIO_INT_LOW_LEV;
146 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 145 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
147 break; 146 } else if (edge == GPIO_INT_LOW_LEV) {
148 case GPIO_INT_LOW_LEV:
149 edge = GPIO_INT_HIGH_LEV; 147 edge = GPIO_INT_HIGH_LEV;
150 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 148 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
151 break; 149 } else {
152 default:
153 pr_err("mxc: invalid configuration for GPIO %d: %x\n", 150 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
154 gpio, edge); 151 gpio, edge);
155 return; 152 return;
@@ -157,25 +154,20 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
157 __raw_writel(val | (edge << (bit << 1)), reg); 154 __raw_writel(val | (edge << (bit << 1)), reg);
158} 155}
159 156
160/* handle n interrupts in one status register */ 157/* handle 32 interrupts in one status register */
161static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 158static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
162{ 159{
163 u32 gpio_irq_no; 160 u32 gpio_irq_no_base = port->virtual_irq_start;
164 161
165 gpio_irq_no = port->virtual_irq_start; 162 while (irq_stat != 0) {
166 for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) { 163 int irqoffset = fls(irq_stat) - 1;
167 u32 gpio = irq_to_gpio(gpio_irq_no);
168
169 if ((irq_stat & 1) == 0)
170 continue;
171 164
172 BUG_ON(!(irq_desc[gpio_irq_no].handle_irq)); 165 if (port->both_edges & (1 << irqoffset))
166 mxc_flip_edge(port, irqoffset);
173 167
174 if (port->both_edges & (1 << (gpio & 31))) 168 generic_handle_irq(gpio_irq_no_base + irqoffset);
175 mxc_flip_edge(port, gpio);
176 169
177 irq_desc[gpio_irq_no].handle_irq(gpio_irq_no, 170 irq_stat &= ~(1 << irqoffset);
178 &irq_desc[gpio_irq_no]);
179 } 171 }
180} 172}
181 173
diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
index 05ff2f31ef1f..93cc66f104c7 100644
--- a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
+++ b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
@@ -21,19 +21,19 @@
21/* 21/*
22 * KZM-ARM11-01 Board Control Registers on FPGA 22 * KZM-ARM11-01 Board Control Registers on FPGA
23 */ 23 */
24#define KZM_ARM11_CTL1 (CS4_BASE_ADDR + 0x1000) 24#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000)
25#define KZM_ARM11_CTL2 (CS4_BASE_ADDR + 0x1001) 25#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001)
26#define KZM_ARM11_RSW1 (CS4_BASE_ADDR + 0x1002) 26#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002)
27#define KZM_ARM11_BACK_LIGHT (CS4_BASE_ADDR + 0x1004) 27#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004)
28#define KZM_ARM11_FPGA_REV (CS4_BASE_ADDR + 0x1008) 28#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008)
29#define KZM_ARM11_7SEG_LED (CS4_BASE_ADDR + 0x1010) 29#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010)
30#define KZM_ARM11_LEDS (CS4_BASE_ADDR + 0x1020) 30#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020)
31#define KZM_ARM11_DIPSW2 (CS4_BASE_ADDR + 0x1003) 31#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003)
32 32
33/* 33/*
34 * External UART for touch panel on FPGA 34 * External UART for touch panel on FPGA
35 */ 35 */
36#define KZM_ARM11_16550 (CS4_BASE_ADDR + 0x1050) 36#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
37 37
38#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */ 38#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */
39 39
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
index 2cbfa35e82ff..095a199591c6 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -14,7 +14,7 @@
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15 15
16/* Base address of PBC controller */ 16/* Base address of PBC controller */
17#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) 17#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
18/* Offsets for the PBC Controller register */ 18/* Offsets for the PBC Controller register */
19 19
20/* PBC Board status register offset */ 20/* PBC Board status register offset */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
index d5be6b5a6acf..fc5fec9b55f0 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -25,6 +25,7 @@ enum mx31moboard_boards {
25 MX31NOBOARD = 0, 25 MX31NOBOARD = 0,
26 MX31DEVBOARD = 1, 26 MX31DEVBOARD = 1,
27 MX31MARXBOT = 2, 27 MX31MARXBOT = 2,
28 MX31SMARTBOT = 3,
28}; 29};
29 30
30/* 31/*
@@ -34,6 +35,7 @@ enum mx31moboard_boards {
34 35
35extern void mx31moboard_devboard_init(void); 36extern void mx31moboard_devboard_init(void);
36extern void mx31moboard_marxbot_init(void); 37extern void mx31moboard_marxbot_init(void);
38extern void mx31moboard_smartbot_init(void);
37 39
38#endif 40#endif
39 41
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
index 43a82d0c534d..753a5988d85c 100644
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ b/arch/arm/plat-mxc/include/mach/clock.h
@@ -26,13 +26,6 @@
26struct module; 26struct module;
27 27
28struct clk { 28struct clk {
29#ifndef CONFIG_COMMON_CLKDEV
30 /* As soon as i.MX1 and i.MX31 switched to clkdev, this
31 * block can go away */
32 struct list_head node;
33 struct module *owner;
34 const char *name;
35#endif
36 int id; 29 int id;
37 /* Source clock this clk depends on */ 30 /* Source clock this clk depends on */
38 struct clk *parent; 31 struct clk *parent;
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 4bf1068ffad9..2941472582d2 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -20,14 +20,17 @@ extern void mx25_map_io(void);
20extern void mx27_map_io(void); 20extern void mx27_map_io(void);
21extern void mx31_map_io(void); 21extern void mx31_map_io(void);
22extern void mx35_map_io(void); 22extern void mx35_map_io(void);
23extern void mx51_map_io(void);
23extern void mxc91231_map_io(void); 24extern void mxc91231_map_io(void);
24extern void mxc_init_irq(void __iomem *); 25extern void mxc_init_irq(void __iomem *);
26extern void tzic_init_irq(void __iomem *);
25extern void mx1_init_irq(void); 27extern void mx1_init_irq(void);
26extern void mx21_init_irq(void); 28extern void mx21_init_irq(void);
27extern void mx25_init_irq(void); 29extern void mx25_init_irq(void);
28extern void mx27_init_irq(void); 30extern void mx27_init_irq(void);
29extern void mx31_init_irq(void); 31extern void mx31_init_irq(void);
30extern void mx35_init_irq(void); 32extern void mx35_init_irq(void);
33extern void mx51_init_irq(void);
31extern void mxc91231_init_irq(void); 34extern void mxc91231_init_irq(void);
32extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); 35extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
33extern int mx1_clocks_init(unsigned long fref); 36extern int mx1_clocks_init(unsigned long fref);
@@ -36,6 +39,8 @@ extern int mx25_clocks_init(void);
36extern int mx27_clocks_init(unsigned long fref); 39extern int mx27_clocks_init(unsigned long fref);
37extern int mx31_clocks_init(unsigned long fref); 40extern int mx31_clocks_init(unsigned long fref);
38extern int mx35_clocks_init(void); 41extern int mx35_clocks_init(void);
42extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
43 unsigned long ckih1, unsigned long ckih2);
39extern int mxc91231_clocks_init(unsigned long fref); 44extern int mxc91231_clocks_init(unsigned long fref);
40extern int mxc_register_gpios(void); 45extern int mxc_register_gpios(void);
41extern int mxc_register_device(struct platform_device *pdev, void *data); 46extern int mxc_register_device(struct platform_device *pdev, void *data);
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 15b2b148a105..133d66bfb533 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -10,6 +10,7 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 * 11 *
12 */ 12 */
13#define IMX_NEEDS_DEPRECATED_SYMBOLS
13 14
14#ifdef CONFIG_ARCH_MX1 15#ifdef CONFIG_ARCH_MX1
15#include <mach/mx1.h> 16#include <mach/mx1.h>
@@ -44,13 +45,22 @@
44#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) 45#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
45#endif 46#endif
46 47
48#ifdef CONFIG_ARCH_MX5
49#ifdef UART_PADDR
50#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
51#endif
52#include <mach/mx51.h>
53#define UART_PADDR MX51_UART1_BASE_ADDR
54#define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR)
55#endif
56
47#ifdef CONFIG_ARCH_MXC91231 57#ifdef CONFIG_ARCH_MXC91231
48#ifdef UART_PADDR 58#ifdef UART_PADDR
49#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 59#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
50#endif 60#endif
51#include <mach/mxc91231.h> 61#include <mach/mxc91231.h>
52#define UART_PADDR MXC91231_UART2_BASE_ADDR 62#define UART_PADDR MXC91231_UART2_BASE_ADDR
53#define UART_VADDR MXC91231_AIPS1_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) 63#define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR)
54#endif 64#endif
55 .macro addruart,rx 65 .macro addruart,rx
56 mrc p15, 0, \rx, c1, c0 66 mrc p15, 0, \rx, c1, c0
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index 7cf290efe768..aeb08697726b 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> 2 * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
4 */ 4 */
5 5
6/* 6/*
@@ -18,11 +18,16 @@
18 .endm 18 .endm
19 19
20 .macro get_irqnr_preamble, base, tmp 20 .macro get_irqnr_preamble, base, tmp
21#ifndef CONFIG_MXC_TZIC
21 ldr \base, =avic_base 22 ldr \base, =avic_base
22 ldr \base, [\base] 23 ldr \base, [\base]
23#ifdef CONFIG_MXC_IRQ_PRIOR 24#ifdef CONFIG_MXC_IRQ_PRIOR
24 ldr r4, [\base, #AVIC_NIMASK] 25 ldr r4, [\base, #AVIC_NIMASK]
25#endif 26#endif
27#elif defined CONFIG_MXC_TZIC
28 ldr \base, =tzic_base
29 ldr \base, [\base]
30#endif /* CONFIG_MXC_TZIC */
26 .endm 31 .endm
27 32
28 .macro arch_ret_to_user, tmp1, tmp2 33 .macro arch_ret_to_user, tmp1, tmp2
@@ -32,6 +37,7 @@
32 @ and returns its number in irqnr 37 @ and returns its number in irqnr
33 @ and returns if an interrupt occured in irqstat 38 @ and returns if an interrupt occured in irqstat
34 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 39 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
40#ifndef CONFIG_MXC_TZIC
35 @ Load offset & priority of the highest priority 41 @ Load offset & priority of the highest priority
36 @ interrupt pending from AVIC_NIVECSR 42 @ interrupt pending from AVIC_NIVECSR
37 ldr \irqstat, [\base, #0x40] 43 ldr \irqstat, [\base, #0x40]
@@ -45,6 +51,32 @@
45 strne \tmp, [\base, #AVIC_NIMASK] 51 strne \tmp, [\base, #AVIC_NIMASK]
46 streq r4, [\base, #AVIC_NIMASK] 52 streq r4, [\base, #AVIC_NIMASK]
47#endif 53#endif
54#elif defined CONFIG_MXC_TZIC
55 @ Load offset & priority of the highest priority
56 @ interrupt pending.
57 @ 0xD80 is HIPND0 register
58 mov \irqnr, #0
59 mov \irqstat, #0x0D80
601000:
61 ldr \tmp, [\irqstat, \base]
62 cmp \tmp, #0
63 bne 1001f
64 addeq \irqnr, \irqnr, #32
65 addeq \irqstat, \irqstat, #4
66 cmp \irqnr, #128
67 blo 1000b
68 b 2001f
691001: mov \irqstat, #1
701002: tst \tmp, \irqstat
71 bne 2002f
72 movs \tmp, \tmp, lsr #1
73 addne \irqnr, \irqnr, #1
74 bne 1002b
752001:
76 mov \irqnr, #0
772002:
78 movs \irqnr, \irqnr
79#endif
48 .endm 80 .endm
49 81
50 @ irq priority table (not used) 82 @ irq priority table (not used)
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 78db75475f69..ebadf4ac43fc 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -22,6 +22,15 @@
22 22
23#include <asm/sizes.h> 23#include <asm/sizes.h>
24 24
25#define IMX_IO_ADDRESS(addr, module) \
26 ((void __force __iomem *) \
27 (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\
28 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0))
29
30#ifdef CONFIG_ARCH_MX5
31#include <mach/mx51.h>
32#endif
33
25#ifdef CONFIG_ARCH_MX3 34#ifdef CONFIG_ARCH_MX3
26#include <mach/mx3x.h> 35#include <mach/mx3x.h>
27#include <mach/mx31.h> 36#include <mach/mx31.h>
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1.h b/arch/arm/plat-mxc/include/mach/iomux-mx1.h
index bf23305c19cc..6b1507cf378e 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx1.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx1.h
@@ -1,166 +1,155 @@
1/* 1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> 2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3* 3 *
4* This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5* modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
6* as published by the Free Software Foundation; either version 2 6 * as published by the Free Software Foundation; either version 2
7* of the License, or (at your option) any later version. 7 * of the License, or (at your option) any later version.
8* This program is distributed in the hope that it will be useful, 8 * This program is distributed in the hope that it will be useful,
9* but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11* GNU General Public License for more details. 11 * GNU General Public License for more details.
12* 12 *
13* You should have received a copy of the GNU General Public License 13 * You should have received a copy of the GNU General Public License
14* along with this program; if not, write to the Free Software 14 * along with this program; if not, write to the Free Software
15* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16* MA 02110-1301, USA. 16 * MA 02110-1301, USA.
17*/ 17 */
18#ifndef __MACH_IOMUX_MX1_H__
19#define __MACH_IOMUX_MX1_H__
18 20
19#ifndef _MXC_IOMUX_MX1_H 21#include <mach/iomux-v1.h>
20#define _MXC_IOMUX_MX1_H
21 22
22#ifndef GPIO_PORTA 23#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
23#error Please include mach/iomux.h 24#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
24#endif 25#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1)
26#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1)
27#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2)
28#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3)
29#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4)
30#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5)
31#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6)
32#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7)
33#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8)
34#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9)
35#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10)
36#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11)
37#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12)
38#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13)
39#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14)
40#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
41#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
42#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
43#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
44#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
45#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
46#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
47#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21)
48#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22)
49#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23)
50#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24)
51#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
52#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25)
53#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
54#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26)
55#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
56#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27)
57#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
58#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28)
59#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
60#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29)
61#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
62#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30)
63#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
64#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31)
65#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31)
66#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
67#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8)
68#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9)
69#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9)
70#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10)
71#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10)
72#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11)
73#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11)
74#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12)
75#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12)
76#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
77#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13)
78#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14)
79#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15)
80#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16)
81#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17)
82#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18)
83#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19)
84#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20)
85#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21)
86#define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22)
87#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23)
88#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24)
89#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25)
90#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26)
91#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27)
92#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28)
93#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29)
94#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30)
95#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31)
96#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3)
97#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4)
98#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
99#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6)
100#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7)
101#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8)
102#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
103#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10)
104#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
105#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12)
106#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
107#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14)
108#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15)
109#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16)
110#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17)
111#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24)
112#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25)
113#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26)
114#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27)
115#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28)
116#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29)
117#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30)
118#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31)
119#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6)
120#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7)
121#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7)
122#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7)
123#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8)
124#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8)
125#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8)
126#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9)
127#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9)
128#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9)
129#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10)
130#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10)
131#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10)
132#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11)
133#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12)
134#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13)
135#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14)
136#define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15)
137#define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16)
138#define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
139#define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
140#define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19)
141#define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20)
142#define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21)
143#define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22)
144#define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23)
145#define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24)
146#define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
147#define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
148#define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
149#define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
150#define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
151#define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30)
152#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
153#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31)
25 154
26/* FIXME: This list is not completed. The correct directions are 155#endif /* ifndef __MACH_IOMUX_MX1_H__ */
27* missing on some (many) pins
28*/
29
30
31/* Primary GPIO pin functions */
32
33#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
34#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
35#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1)
36#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1)
37#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2)
38#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3)
39#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4)
40#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5)
41#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6)
42#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7)
43#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8)
44#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9)
45#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10)
46#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11)
47#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12)
48#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13)
49#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14)
50#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
51#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
52#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
53#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
54#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
55#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
56#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
57#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21)
58#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22)
59#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23)
60#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24)
61#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
62#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25)
63#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
64#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26)
65#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
66#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27)
67#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
68#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28)
69#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
70#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29)
71#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
72#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30)
73#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
74#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31)
75#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31)
76#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
77#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8)
78#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9)
79#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9)
80#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10)
81#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10)
82#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11)
83#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11)
84#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12)
85#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12)
86#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
87#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13)
88#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14)
89#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15)
90#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16)
91#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17)
92#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18)
93#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19)
94#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20)
95#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21)
96#define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22)
97#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23)
98#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24)
99#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25)
100#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26)
101#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27)
102#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28)
103#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29)
104#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30)
105#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31)
106#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3)
107#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4)
108#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
109#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6)
110#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7)
111#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8)
112#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
113#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10)
114#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
115#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12)
116#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
117#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14)
118#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15)
119#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16)
120#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17)
121#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24)
122#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25)
123#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26)
124#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27)
125#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28)
126#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29)
127#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30)
128#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31)
129#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6)
130#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7)
131#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7)
132#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7)
133#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8)
134#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8)
135#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8)
136#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9)
137#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9)
138#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9)
139#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10)
140#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10)
141#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10)
142#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11)
143#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12)
144#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13)
145#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14)
146#define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15)
147#define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16)
148#define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
149#define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
150#define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19)
151#define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20)
152#define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21)
153#define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22)
154#define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23)
155#define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24)
156#define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
157#define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
158#define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
159#define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
160#define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
161#define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30)
162#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
163#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31)
164
165
166#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx21.h b/arch/arm/plat-mxc/include/mach/iomux-mx21.h
index 63aaa972e275..1495dfda7834 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx21.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx21.h
@@ -1,126 +1,122 @@
1/* 1/*
2* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> 2 * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
3* 3 *
4* This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5* modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
6* as published by the Free Software Foundation; either version 2 6 * as published by the Free Software Foundation; either version 2
7* of the License, or (at your option) any later version. 7 * of the License, or (at your option) any later version.
8* This program is distributed in the hope that it will be useful, 8 * This program is distributed in the hope that it will be useful,
9* but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11* GNU General Public License for more details. 11 * GNU General Public License for more details.
12* 12 *
13* You should have received a copy of the GNU General Public License 13 * You should have received a copy of the GNU General Public License
14* along with this program; if not, write to the Free Software 14 * along with this program; if not, write to the Free Software
15* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16* MA 02110-1301, USA. 16 * MA 02110-1301, USA.
17*/ 17 */
18 18#ifndef __MACH_IOMUX_MX21_H__
19#ifndef _MXC_IOMUX_MX21_H 19#define __MACH_IOMUX_MX21_H__
20#define _MXC_IOMUX_MX21_H 20
21 21#include <mach/iomux-mx2x.h>
22#ifndef GPIO_PORTA 22#include <mach/iomux-v1.h>
23#error Please include mach/iomux.h
24#endif
25
26 23
27/* Primary GPIO pin functions */ 24/* Primary GPIO pin functions */
28 25
29#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22) 26#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22)
30#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25) 27#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25)
31#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5) 28#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5)
32#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6) 29#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6)
33#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7) 30#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7)
34#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8) 31#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8)
35#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9) 32#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9)
36#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10) 33#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10)
37#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11) 34#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11)
38#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12) 35#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12)
39#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13) 36#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13)
40#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16) 37#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16)
41#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17) 38#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17)
42#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18) 39#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18)
43#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19) 40#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19)
44#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0) 41#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0)
45#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1) 42#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1)
46#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2) 43#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2)
47#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1) 44#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1)
48#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3) 45#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3)
49#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7) 46#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7)
50#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8) 47#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8)
51#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9) 48#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9)
52#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10) 49#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10)
53#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11) 50#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11)
54#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12) 51#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12)
55#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13) 52#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13)
56#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14) 53#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14)
57#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16) 54#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16)
58 55
59/* Alternate GPIO pin functions */ 56/* Alternate GPIO pin functions */
60 57
61#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5) 58#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5)
62#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6) 59#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6)
63#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7) 60#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7)
64#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8) 61#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8)
65#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9) 62#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9)
66#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10) 63#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10)
67#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11) 64#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11)
68#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12) 65#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12)
69#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13) 66#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13)
70#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14) 67#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14)
71#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15) 68#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15)
72#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16) 69#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16)
73#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17) 70#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17)
74#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18) 71#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18)
75#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19) 72#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19)
76#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20) 73#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20)
77#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21) 74#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21)
78#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22) 75#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22)
79#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23) 76#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23)
80#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29) 77#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29)
81#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30) 78#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30)
82 79
83/* AIN GPIO pin functions */ 80/* AIN GPIO pin functions */
84 81
85#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) 82#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
86#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21) 83#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21)
87#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22) 84#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22)
88#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23) 85#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23)
89#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24) 86#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24)
90#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8) 87#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8)
91#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0) 88#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0)
92#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1) 89#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1)
93#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2) 90#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2)
94#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3) 91#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3)
95#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4) 92#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4)
96#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5) 93#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5)
97 94
98/* BIN GPIO pin functions */ 95/* BIN GPIO pin functions */
99 96
100#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) 97#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
101#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27) 98#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27)
102 99
103/* CIN GPIO pin functions */ 100/* CIN GPIO pin functions */
104 101
105#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26) 102#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26)
106 103
107/* AOUT GPIO pin functions */ 104/* AOUT GPIO pin functions */
108 105
109#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29) 106#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29)
110#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19) 107#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19)
111#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20) 108#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20)
112#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25) 109#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25)
113#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26) 110#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26)
114#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9) 111#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9)
115#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6) 112#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6)
116#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7) 113#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7)
117#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8) 114#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8)
118#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9) 115#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9)
119#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10) 116#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10)
120#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11) 117#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11)
121#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12) 118#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12)
122#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13) 119#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13)
123#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14) 120#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14)
124 121
125 122#endif /* ifndef __MACH_IOMUX_MX21_H__ */
126#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index 9af494f0ab3d..f39220d1b67a 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -7,7 +7,7 @@
7 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. 7 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
8 * and 8 * and
9 * arch/arm/plat-mxc/include/mach/iomux-mx35.h 9 * arch/arm/plat-mxc/include/mach/iomux-mx35.h
10 * Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> 10 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
11 * 11 *
12 * The code contained herein is licensed under the GNU General Public 12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License 13 * License. You may obtain a copy of the GNU General Public License
@@ -16,24 +16,11 @@
16 * http://www.opensource.org/licenses/gpl-license.html 16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html 17 * http://www.gnu.org/copyleft/gpl.html
18 */ 18 */
19#ifndef __IOMUX_MX25_H__ 19#ifndef __MACH_IOMUX_MX25_H__
20#define __IOMUX_MX25_H__ 20#define __MACH_IOMUX_MX25_H__
21 21
22#include <mach/iomux-v3.h> 22#include <mach/iomux-v3.h>
23 23
24#ifndef GPIO_PORTA
25#error Please include mach/iomux.h
26#endif
27
28/*
29 *
30 * @brief MX25 I/O Pin List
31 *
32 * @ingroup GPIO_MX25
33 */
34
35#ifndef __ASSEMBLY__
36
37/* 24/*
38 * IOMUX/PAD Bit field definitions 25 * IOMUX/PAD Bit field definitions
39 */ 26 */
@@ -462,9 +449,11 @@
462#define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP) 449#define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
463 450
464#define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL) 451#define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
452#define MX25_PAD_GPIO_E__LD16 IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, NO_PAD_CTRL)
465#define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP) 453#define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
466 454
467#define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL) 455#define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
456#define MX25_PAD_GPIO_F__LD17 IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, NO_PAD_CTRL)
468#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL) 457#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
469 458
470#define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL) 459#define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
@@ -513,5 +502,4 @@
513#define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL) 502#define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL)
514#define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL) 503#define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL)
515 504
516#endif // __ASSEMBLY__ 505#endif /* __MACH_IOMUX_MX25_H__ */
517#endif // __IOMUX_MX25_H__
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx27.h b/arch/arm/plat-mxc/include/mach/iomux-mx27.h
index 5ac158b70f61..d9f9a6e32d80 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx27.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx27.h
@@ -1,207 +1,205 @@
1/* 1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> 2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> 3 * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
4* 4 *
5* This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
6* modify it under the terms of the GNU General Public License 6 * modify it under the terms of the GNU General Public License
7* as published by the Free Software Foundation; either version 2 7 * as published by the Free Software Foundation; either version 2
8* of the License, or (at your option) any later version. 8 * of the License, or (at your option) any later version.
9* This program is distributed in the hope that it will be useful, 9 * This program is distributed in the hope that it will be useful,
10* but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12* GNU General Public License for more details. 12 * GNU General Public License for more details.
13* 13 *
14* You should have received a copy of the GNU General Public License 14 * You should have received a copy of the GNU General Public License
15* along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
16* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17* MA 02110-1301, USA. 17 * MA 02110-1301, USA.
18*/ 18 */
19 19#ifndef __MACH_IOMUX_MX27_H__
20#ifndef _MXC_IOMUX_MX27_H 20#define __MACH_IOMUX_MX27_H__
21#define _MXC_IOMUX_MX27_H 21
22 22#include <mach/iomux-mx2x.h>
23#ifndef GPIO_PORTA 23#include <mach/iomux-v1.h>
24#error Please include mach/iomux.h
25#endif
26
27 24
28/* Primary GPIO pin functions */ 25/* Primary GPIO pin functions */
29 26
30#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0) 27#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0)
31#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1) 28#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1)
32#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) 29#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2)
33#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) 30#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3)
34#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) 31#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4)
35#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22) 32#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22)
36#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25) 33#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25)
37#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) 34#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
38#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6) 35#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6)
39#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7) 36#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7)
40#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8) 37#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8)
41#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) 38#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
42#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10) 39#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10)
43#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) 40#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
44#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12) 41#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12)
45#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13) 42#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13)
46#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16) 43#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16)
47#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17) 44#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17)
48#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18) 45#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18)
49#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19) 46#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19)
50#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25) 47#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0)
51#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27) 48#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1)
52#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0) 49#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2)
53#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1) 50#define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3)
54#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2) 51#define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4)
55#define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3) 52#define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5)
56#define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4) 53#define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6)
57#define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5) 54#define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7)
58#define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6) 55#define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8)
59#define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7) 56#define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9)
60#define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8) 57#define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10)
61#define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9) 58#define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11)
62#define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10) 59#define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12)
63#define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11) 60#define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13)
64#define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12) 61#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14)
65#define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13) 62#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15)
66#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14) 63#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16)
67#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15) 64#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0)
68#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16) 65#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1)
69#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0) 66#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2)
70#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1) 67#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24)
71#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2) 68#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25)
72#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24) 69#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1)
73#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25) 70#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3)
74#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1) 71#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7)
75#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3) 72#define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8)
76#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7) 73#define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9)
77#define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8) 74#define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10)
78#define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9) 75#define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11)
79#define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10) 76#define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12)
80#define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11) 77#define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13)
81#define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12) 78#define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14)
82#define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13) 79#define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16)
83#define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14) 80#define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17)
84#define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16) 81#define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18)
85#define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17) 82#define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19)
86#define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18) 83#define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20)
87#define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19) 84#define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23)
88#define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20)
89#define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23)
90 85
91/* Alternate GPIO pin functions */ 86/* Alternate GPIO pin functions */
92 87
93#define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4) 88#define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4)
94#define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5) 89#define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5)
95#define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6) 90#define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6)
96#define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7) 91#define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7)
97#define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8) 92#define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8)
98#define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9) 93#define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9)
99#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10) 94#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10)
100#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11) 95#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11)
101#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12) 96#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12)
102#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13) 97#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13)
103#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18) 98#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18)
104#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19) 99#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19)
105#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20) 100#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20)
106#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21) 101#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21)
107#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8) 102#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8)
108#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24) 103#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24)
109#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26) 104#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25)
110#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1) 105#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26)
111#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6) 106#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27)
112#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7) 107#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1)
113#define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9) 108#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6)
114#define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2) 109#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7)
115#define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3) 110#define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9)
116#define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4) 111#define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2)
117#define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5) 112#define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3)
118#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8) 113#define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4)
119#define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10) 114#define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5)
120#define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11) 115#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8)
121#define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12) 116#define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10)
122#define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13) 117#define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11)
123#define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14) 118#define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12)
124#define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15) 119#define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13)
125#define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16) 120#define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14)
126#define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1) 121#define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15)
127#define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3) 122#define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16)
128#define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5) 123#define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1)
129#define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7) 124#define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3)
130#define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8) 125#define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5)
131#define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9) 126#define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7)
132#define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10) 127#define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8)
133#define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11) 128#define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9)
134#define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12) 129#define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10)
135#define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13) 130#define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11)
136#define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14) 131#define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12)
137#define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15) 132#define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13)
138#define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16) 133#define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14)
139#define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17) 134#define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15)
140#define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18) 135#define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16)
141#define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19) 136#define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17)
142#define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20) 137#define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18)
143#define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22) 138#define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19)
144#define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23) 139#define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20)
140#define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22)
141#define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23)
145 142
146/* AIN GPIO pin functions */ 143/* AIN GPIO pin functions */
147 144
148#define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) 145#define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
149#define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15) 146#define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15)
150#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0) 147#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0)
151#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1) 148#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1)
152#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2) 149#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2)
153#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3) 150#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3)
154#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9) 151#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9)
155#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16) 152#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16)
156#define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27) 153#define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27)
157#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23) 154#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23)
158 155
159/* BIN GPIO pin functions */ 156/* BIN GPIO pin functions */
160 157
161#define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) 158#define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
162 159
163/* CIN GPIO pin functions */ 160/* CIN GPIO pin functions */
164 161
165#define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2) 162#define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2)
166#define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3) 163#define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3)
167#define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4) 164#define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4)
168#define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5) 165#define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5)
169#define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6) 166#define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6)
170#define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7) 167#define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7)
171#define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8) 168#define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8)
172#define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9) 169#define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9)
173#define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10) 170#define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10)
174#define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11) 171#define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11)
175#define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12) 172#define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12)
176#define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13) 173#define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13)
177#define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14) 174#define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14)
178#define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15) 175#define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15)
179#define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16) 176#define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16)
180#define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23) 177#define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23)
181#define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27) 178#define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27)
182/* LCDC_TESTx on PBxx omitted, because it's not clear what they do */ 179/* LCDC_TESTx on PBxx omitted, because it's not clear what they do */
183 180
184/* AOUT GPIO pin functions */ 181/* AOUT GPIO pin functions */
185 182
186#define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14) 183#define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14)
187#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4) 184#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4)
188#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5) 185#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5)
189#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6) 186#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6)
190#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7) 187#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7)
191#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10) 188#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10)
192#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11) 189#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11)
193#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12) 190#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12)
194#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13) 191#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13)
195#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14) 192#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14)
196#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15) 193#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15)
197 194
198#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17) 195/* BOUT GPIO pin functions */
199#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18) 196
200#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19) 197#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17)
201#define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28) 198#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18)
202#define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29) 199#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19)
203#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30) 200#define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28)
204#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31) 201#define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29)
205 202#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30)
206 203#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31)
207#endif /* _MXC_GPIO_MX1_MX2_H */ 204
205#endif /* __MACH_IOMUX_MX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
index fb5ae638e79f..c4f116d214f2 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
@@ -1,237 +1,230 @@
1/* 1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> 2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> 3 * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
4* 4 *
5* This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
6* modify it under the terms of the GNU General Public License 6 * modify it under the terms of the GNU General Public License
7* as published by the Free Software Foundation; either version 2 7 * as published by the Free Software Foundation; either version 2
8* of the License, or (at your option) any later version. 8 * of the License, or (at your option) any later version.
9* This program is distributed in the hope that it will be useful, 9 * This program is distributed in the hope that it will be useful,
10* but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12* GNU General Public License for more details. 12 * GNU General Public License for more details.
13* 13 *
14* You should have received a copy of the GNU General Public License 14 * You should have received a copy of the GNU General Public License
15* along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
16* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17* MA 02110-1301, USA. 17 * MA 02110-1301, USA.
18*/ 18 */
19 19#ifndef __MACH_IOMUX_MX2x_H__
20#ifndef _MXC_IOMUX_MX2x_H 20#define __MACH_IOMUX_MX2x_H__
21#define _MXC_IOMUX_MX2x_H
22
23#ifndef GPIO_PORTA
24#error Please include mach/iomux.h
25#endif
26
27 21
28/* Primary GPIO pin functions */ 22/* Primary GPIO pin functions */
29 23
30#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5) 24#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5)
31#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6) 25#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6)
32#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7) 26#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7)
33#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8) 27#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8)
34#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9) 28#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9)
35#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10) 29#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10)
36#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11) 30#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11)
37#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12) 31#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12)
38#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13) 32#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13)
39#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14) 33#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14)
40#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) 34#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
41#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) 35#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
42#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17) 36#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17)
43#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18) 37#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18)
44#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19) 38#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19)
45#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20) 39#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20)
46#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21) 40#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21)
47#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22) 41#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22)
48#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23) 42#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23)
49#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24) 43#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24)
50#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25) 44#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25)
51#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26) 45#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26)
52#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27) 46#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27)
53#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28) 47#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28)
54#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29) 48#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29)
55#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30) 49#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30)
56#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31) 50#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31)
57#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) 51#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
58#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) 52#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
59#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) 53#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
60#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) 54#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
61#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) 55#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
62#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) 56#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
63#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10) 57#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10)
64#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11) 58#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11)
65#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12) 59#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12)
66#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13) 60#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13)
67#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14) 61#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14)
68#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15) 62#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15)
69#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16) 63#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16)
70#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17) 64#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17)
71#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18) 65#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18)
72#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19) 66#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19)
73#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20) 67#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20)
74#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21) 68#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21)
75#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23) 69#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23)
76#define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24) 70#define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24)
77#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26) 71#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26)
78#define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27) 72#define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27)
79#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28) 73#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28)
80#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29) 74#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29)
81#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30) 75#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30)
82#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31) 76#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31)
83#define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14) 77#define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14)
84#define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15) 78#define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15)
85#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20) 79#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20)
86#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21) 80#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21)
87#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22) 81#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22)
88#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23) 82#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23)
89#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24) 83#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24)
90#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25) 84#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25)
91#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26) 85#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26)
92#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27) 86#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27)
93#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28) 87#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28)
94#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29) 88#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29)
95#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30) 89#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30)
96#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) 90#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31)
97#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) 91#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
98#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) 92#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
99#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19) 93#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19)
100#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20) 94#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20)
101#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21) 95#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21)
102#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22) 96#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22)
103#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23) 97#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23)
104#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24) 98#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24)
105#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) 99#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
106#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) 100#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
107#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) 101#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
108#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) 102#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
109#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) 103#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
110#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30) 104#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30)
111#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31) 105#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31)
112#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3) 106#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3)
113#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4) 107#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4)
114#define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5) 108#define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5)
115#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6) 109#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6)
116#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7) 110#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7)
117#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8) 111#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8)
118#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9) 112#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9)
119#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10) 113#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10)
120#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11) 114#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11)
121#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12) 115#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12)
122#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13) 116#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13)
123#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14) 117#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14)
124#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15) 118#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15)
125#define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16) 119#define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16)
126#define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17) 120#define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17)
127#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) 121#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18)
128#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) 122#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19)
129#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) 123#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20)
130#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) 124#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21)
131#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) 125#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22)
132#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) 126#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23)
133#define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0) 127#define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0)
134#define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2) 128#define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2)
135#define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4) 129#define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4)
136#define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5) 130#define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5)
137#define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6) 131#define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6)
138#define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15) 132#define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15)
139#define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21) 133#define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21)
140#define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22) 134#define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22)
141 135
142/* Alternate GPIO pin functions */ 136/* Alternate GPIO pin functions */
143 137
144#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26) 138#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26)
145#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28) 139#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28)
146#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29) 140#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29)
147#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31) 141#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31)
148#define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28) 142#define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28)
149#define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29) 143#define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29)
150#define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30) 144#define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30)
151#define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31) 145#define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31)
152#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19) 146#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19)
153#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20) 147#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20)
154#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21) 148#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21)
155#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22) 149#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22)
156#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23) 150#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23)
157#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24) 151#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24)
158#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26) 152#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26)
159#define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0) 153#define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0)
160#define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1) 154#define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1)
161#define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2) 155#define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2)
162#define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3) 156#define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3)
163#define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4) 157#define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4)
164#define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6) 158#define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6)
165#define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7) 159#define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7)
166#define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16) 160#define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16)
167#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18) 161#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18)
168#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21) 162#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21)
169#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22) 163#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22)
170#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23) 164#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23)
171 165
172/* AIN GPIO pin functions */ 166/* AIN GPIO pin functions */
173 167
174#define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6) 168#define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6)
175#define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7) 169#define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7)
176#define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8) 170#define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8)
177#define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) 171#define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
178#define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11) 172#define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11)
179#define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13) 173#define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13)
180#define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15) 174#define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15)
181#define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) 175#define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
182#define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19) 176#define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19)
183#define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21) 177#define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21)
184#define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22) 178#define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22)
185#define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24) 179#define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24)
186#define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25) 180#define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25)
187#define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26) 181#define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26)
188#define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27) 182#define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27)
189#define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6) 183#define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6)
190#define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7) 184#define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7)
191#define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8) 185#define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8)
192#define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9) 186#define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9)
193#define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25) 187#define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25)
194#define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26) 188#define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26)
195#define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27) 189#define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27)
196#define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28) 190#define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28)
197#define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29) 191#define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29)
198#define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30) 192#define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30)
199#define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31) 193#define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31)
200#define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5) 194#define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5)
201#define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6) 195#define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6)
202#define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7) 196#define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7)
203#define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8) 197#define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8)
204#define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9) 198#define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9)
205#define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10) 199#define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10)
206#define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11) 200#define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11)
207#define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12) 201#define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12)
208#define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13) 202#define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13)
209#define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5) 203#define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5)
210 204
211/* BIN GPIO pin functions */ 205/* BIN GPIO pin functions */
212 206
213#define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5) 207#define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5)
214 208
215/* CIN GPIO pin functions */ 209/* CIN GPIO pin functions */
216 210
217#define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14) 211#define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14)
218#define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15) 212#define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15)
219#define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16) 213#define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16)
220#define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17) 214#define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17)
221#define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18) 215#define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18)
222#define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19) 216#define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19)
223#define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20) 217#define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20)
224#define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21) 218#define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21)
225#define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30) 219#define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30)
226#define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5) 220#define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5)
227 221
228/* AOUT GPIO pin functions */ 222/* AOUT GPIO pin functions */
229 223
230#define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29) 224#define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29)
231#define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31) 225#define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31)
232#define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8) 226#define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8)
233#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15) 227#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15)
234#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21) 228#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21)
235
236 229
237#endif 230#endif /* ifndef __MACH_IOMUX_MX2x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index e1fc6da1cd10..e51465d7b224 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -16,12 +16,10 @@
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA. 17 * MA 02110-1301, USA.
18 */ 18 */
19 19#ifndef __MACH_IOMUX_MX3_H__
20#ifndef __MACH_MX31_IOMUX_H__ 20#define __MACH_IOMUX_MX3_H__
21#define __MACH_MX31_IOMUX_H__
22 21
23#include <linux/types.h> 22#include <linux/types.h>
24
25/* 23/*
26 * various IOMUX output functions 24 * various IOMUX output functions
27 */ 25 */
@@ -34,7 +32,7 @@
34#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ 32#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */
35#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ 33#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */
36#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ 34#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */
37#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ 35#define IOMUX_ICONFIG_NONE 0 /* not configured for input */
38#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ 36#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */
39#define IOMUX_ICONFIG_FUNC 2 /* used as function */ 37#define IOMUX_ICONFIG_FUNC 2 /* used as function */
40#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ 38#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */
@@ -167,11 +165,6 @@ int mxc_iomux_mode(unsigned int pin_mode);
167 MXC_GPIO_IRQ_START) 165 MXC_GPIO_IRQ_START)
168 166
169/* 167/*
170 * The number of gpio devices among the pads
171 */
172#define GPIO_PORT_MAX 3
173
174/*
175 * This enumeration is constructed based on the Section 168 * This enumeration is constructed based on the Section
176 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated 169 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
177 * value is constructed based on the rules described above. 170 * value is constructed based on the rules described above.
@@ -633,40 +626,40 @@ enum iomux_pins {
633#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) 626#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
634#define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO) 627#define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO)
635#define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO) 628#define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO)
636#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) 629#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC)
637#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) 630#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC)
638#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) 631#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC)
639#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC) 632#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC)
640#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC) 633#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC)
641#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC) 634#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC)
642#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC) 635#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC)
643#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC) 636#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC)
644#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC) 637#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC)
645#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) 638#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC)
646#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) 639#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC)
647#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) 640#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC)
648#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1) 641#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1)
649#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1) 642#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1)
650#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1) 643#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1)
651#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1) 644#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1)
652#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1) 645#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1)
653#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1) 646#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1)
654#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1) 647#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1)
655#define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC) 648#define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC)
656#define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO) 649#define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO)
657#define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO) 650#define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO)
658#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC) 651#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)
659#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC) 652#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)
660#define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC) 653#define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC)
661#define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC) 654#define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC)
662#define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC) 655#define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC)
663#define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC) 656#define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC)
664#define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC) 657#define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC)
665#define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC) 658#define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC)
666#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC) 659#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)
667#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC) 660#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)
668#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC) 661#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)
669#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC) 662#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)
670#define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO) 663#define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO)
671#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) 664#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
672#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) 665#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
@@ -711,8 +704,8 @@ enum iomux_pins {
711#define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO) 704#define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO)
712#define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO) 705#define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO)
713#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO) 706#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO)
714#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) 707#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO)
715#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) 708#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO)
716#define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO) 709#define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO)
717#define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1) 710#define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1)
718#define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO) 711#define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO)
@@ -727,13 +720,14 @@ enum iomux_pins {
727#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC) 720#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC)
728#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC) 721#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC)
729 722
730/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 723/*
731 * cspi1_ss1*/ 724 * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0,
725 * cspi2_ss1, cspi1_ss0 cspi1_ss1
726 */
732 727
733/* 728/*
734 * This function configures the pad value for a IOMUX pin. 729 * This function configures the pad value for a IOMUX pin.
735 */ 730 */
736void mxc_iomux_set_pad(enum iomux_pins, u32); 731void mxc_iomux_set_pad(enum iomux_pins, u32);
737 732
738#endif 733#endif /* ifndef __MACH_IOMUX_MX3_H__ */
739
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
index c88d40795f7a..2a24bae1b878 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx35.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> 2 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
3 * 3 *
4 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
new file mode 100644
index 000000000000..b4f975e6a665
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -0,0 +1,326 @@
1/*
2 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#ifndef __MACH_IOMUX_MX51_H__
13#define __MACH_IOMUX_MX51_H__
14
15#include <mach/iomux-v3.h>
16
17/*
18 * various IOMUX alternate output functions (1-7)
19 */
20typedef enum iomux_config {
21 IOMUX_CONFIG_ALT0,
22 IOMUX_CONFIG_ALT1,
23 IOMUX_CONFIG_ALT2,
24 IOMUX_CONFIG_ALT3,
25 IOMUX_CONFIG_ALT4,
26 IOMUX_CONFIG_ALT5,
27 IOMUX_CONFIG_ALT6,
28 IOMUX_CONFIG_ALT7,
29 IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
30 IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */
31} iomux_pin_cfg_t;
32
33/* Pad control groupings */
34#define MX51_UART1_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_DSE_HIGH)
36#define MX51_UART2_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
37 PAD_CTL_SRE_FAST)
38#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
39 PAD_CTL_SRE_FAST)
40
41/*
42 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
43 * If <padname> or <padmode> refers to a GPIO, it is named
44 * GPIO_<unit>_<num> see also iomux-v3.h
45 */
46
47/*
48 * FIXME: This was converted using scripts from existing Freescale code to
49 * this form used upstream. Need to verify the name format.
50 */
51
52/* PAD MUX ALT INPSE PATH PADCTRL */
53
54#define MX51_PAD_GPIO_2_0__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL)
55#define MX51_PAD_GPIO_2_1__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL)
56#define MX51_PAD_GPIO_2_2__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL)
57#define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL)
58#define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL)
59#define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL)
60#define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL)
61#define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL)
62
63/* Babbage UART3 */
64#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
65#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
66#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
67#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
68
69#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL)
70#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL)
71#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL)
72#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL)
73
74#define MX51_PAD_GPIO_2_10__EIM_A16 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL)
75#define MX51_PAD_GPIO_2_11__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL)
76#define MX51_PAD_GPIO_2_12__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL)
77#define MX51_PAD_GPIO_2_13__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL)
78#define MX51_PAD_GPIO_2_14__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL)
79#define MX51_PAD_GPIO_2_15__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL)
80#define MX51_PAD_GPIO_2_16__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL)
81#define MX51_PAD_GPIO_2_17__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL)
82
83#define MX51_PAD_GPIO_2_18__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL)
84#define MX51_PAD_GPIO_2_19__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL)
85#define MX51_PAD_GPIO_2_20__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL)
86#define MX51_PAD_GPIO_2_21__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL)
87#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL)
88#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL)
89#define MX51_PAD_GPIO_2_22__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL)
90#define MX51_PAD_GPIO_2_23__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL)
91
92#define MX51_PAD_GPIO_2_24__EIM_OE IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL)
93#define MX51_PAD_GPIO_2_25__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL)
94#define MX51_PAD_GPIO_2_26__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL)
95#define MX51_PAD_GPIO_2_27__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL)
96#define MX51_PAD_GPIO_2_28__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL)
97#define MX51_PAD_GPIO_2_29__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL)
98#define MX51_PAD_GPIO_2_30__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL)
99#define MX51_PAD_GPIO_2_31__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL)
100
101#define MX51_PAD_GPIO_3_1__EIM_LBA IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
102#define MX51_PAD_GPIO_3_2__EIM_CRE IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
103#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
104#define MX51_PAD_GPIO_3_3__NANDF_WE_B IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL)
105#define MX51_PAD_GPIO_3_4__NANDF_RE_B IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL)
106#define MX51_PAD_GPIO_3_5__NANDF_ALE IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL)
107#define MX51_PAD_GPIO_3_6__NANDF_CLE IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL)
108#define MX51_PAD_GPIO_3_7__NANDF_WP_B IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL)
109#define MX51_PAD_GPIO_3_8__NANDF_RB0 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
110#define MX51_PAD_GPIO_3_9__NANDF_RB1 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
111#define MX51_PAD_GPIO_3_10__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
112#define MX51_PAD_GPIO_3_11__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
113#define MX51_PAD_GPIO_3_12__GPIO_NAND IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
114/* REVISIT: Not sure of these values
115
116 #define MX51_PAD_GPIO_1___NANDF_RB4 IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL)
117 #define MX51_PAD_GPIO_3_13__NANDF_RB5 IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
118 #define MX51_PAD_GPIO_3_15__NANDF_RB7 IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
119*/
120#define MX51_PAD_GPIO_3_14__NANDF_RB6 IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
121#define MX51_PAD_GPIO_3_16__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
122#define MX51_PAD_GPIO_3_17__NANDF_CS1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
123#define MX51_PAD_GPIO_3_18__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
124#define MX51_PAD_GPIO_3_19__NANDF_CS3 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
125#define MX51_PAD_GPIO_3_20__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
126#define MX51_PAD_GPIO_3_21__NANDF_CS5 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
127#define MX51_PAD_GPIO_3_22__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
128#define MX51_PAD_GPIO_3_23__NANDF_CS7 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
129#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
130#define MX51_PAD_GPIO_3_25__NANDF_D15 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
131#define MX51_PAD_GPIO_3_26__NANDF_D14 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
132#define MX51_PAD_GPIO_3_27__NANDF_D13 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
133#define MX51_PAD_GPIO_3_28__NANDF_D12 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
134#define MX51_PAD_GPIO_3_29__NANDF_D11 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
135#define MX51_PAD_GPIO_3_30__NANDF_D10 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
136#define MX51_PAD_GPIO_3_31__NANDF_D9 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
137#define MX51_PAD_GPIO_4_0__NANDF_D8 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL)
138#define MX51_PAD_GPIO_4_1__NANDF_D7 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
139#define MX51_PAD_GPIO_4_2__NANDF_D6 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
140#define MX51_PAD_GPIO_4_3__NANDF_D5 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL)
141#define MX51_PAD_GPIO_4_4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
142#define MX51_PAD_GPIO_4_5__NANDF_D3 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
143#define MX51_PAD_GPIO_4_6__NANDF_D2 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
144#define MX51_PAD_GPIO_4_7__NANDF_D1 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
145#define MX51_PAD_GPIO_4_8__NANDF_D0 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL)
146#define MX51_PAD_GPIO_3_12__CSI1_D8 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL)
147#define MX51_PAD_GPIO_3_13__CSI1_D9 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL)
148#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
149#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
150#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
151#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
152#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
153#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
154#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
155#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
156#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
157#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
158#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
159#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
160#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
161#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
162#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
163#define MX51_PAD_GPIO_4_9__CSI2_D12 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL)
164#define MX51_PAD_GPIO_4_10__CSI2_D13 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL)
165#define MX51_PAD_GPIO_4_11__CSI2_D14 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL)
166#define MX51_PAD_GPIO_4_12__CSI2_D15 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
167#define MX51_PAD_GPIO_4_11__CSI2_D16 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL)
168#define MX51_PAD_GPIO_4_12__CSI2_D17 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL)
169#define MX51_PAD_GPIO_4_11__CSI2_D18 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL)
170#define MX51_PAD_GPIO_4_12__CSI2_D19 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL)
171#define MX51_PAD_GPIO_4_13__CSI2_VSYNC IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL)
172#define MX51_PAD_GPIO_4_14__CSI2_HSYNC IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL)
173#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL)
174#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
175#define MX51_PAD_GPIO_4_16__I2C1_CLK IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL)
176#define MX51_PAD_GPIO_4_17__I2C1_DAT IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
177#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
178#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
179#define MX51_PAD_GPIO_4_20__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
180#define MX51_PAD_GPIO_4_21__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
181#define MX51_PAD_GPIO_4_22__CSPI1_MOSI IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
182#define MX51_PAD_GPIO_4_23__CSPI1_MISO IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
183#define MX51_PAD_GPIO_4_24__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
184#define MX51_PAD_GPIO_4_25__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
185#define MX51_PAD_GPIO_4_26__CSPI1_RDY IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
186#define MX51_PAD_GPIO_4_27__CSPI1_SCLK IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
187
188/* Babbage UART1 */
189#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
190#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
191#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
192#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL)
193
194/* Babbage UART2 */
195#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
196#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
197
198#define MX51_PAD_GPIO_1_22__UART3_RXD IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
199#define MX51_PAD_GPIO_1_23__UART3_TXD IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
200#define MX51_PAD_GPIO_1_24__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
201#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
202#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
203#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
204#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
205#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
206#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
207#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
208#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
209#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
210#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
211#define MX51_PAD_GPIO_1_25__USBH1_CLK IOMUX_PAD(0x678, 0x278, 2, 0x0, 0, NO_PAD_CTRL)
212#define MX51_PAD_GPIO_1_26__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 2, 0x0, 0, NO_PAD_CTRL)
213#define MX51_PAD_GPIO_1_27__USBH1_STP IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, NO_PAD_CTRL)
214#define MX51_PAD_GPIO_1_28__USBH1_NXT IOMUX_PAD(0x684, 0x284, 2, 0x0, 0, NO_PAD_CTRL)
215#define MX51_PAD_GPIO_1_11__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 2, 0x0, 0, NO_PAD_CTRL)
216#define MX51_PAD_GPIO_1_12__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 2, 0x0, 0, NO_PAD_CTRL)
217#define MX51_PAD_GPIO_1_13__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 2, 0x0, 0, NO_PAD_CTRL)
218#define MX51_PAD_GPIO_1_14__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 2, 0x0, 0, NO_PAD_CTRL)
219#define MX51_PAD_GPIO_1_15__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 2, 0x0, 0, NO_PAD_CTRL)
220#define MX51_PAD_GPIO_1_16__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 2, 0x0, 0, NO_PAD_CTRL)
221#define MX51_PAD_GPIO_1_17__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 2, 0x0, 0, NO_PAD_CTRL)
222#define MX51_PAD_GPIO_1_18__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 2, 0x0, 0, NO_PAD_CTRL)
223#define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
224#define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
225#define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
226#define MX51_PAD_GPIO_3_3__DI1_D0_CS IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL)
227#define MX51_PAD_GPIO_3_4__DI1_D1_CS IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL)
228#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL)
229#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL)
230#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL)
231#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL)
232#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
233#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
234#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
235#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
236#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
237#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
238#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
239#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
240#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
241#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
242#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
243#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
244#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
245#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
246#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
247#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
248#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
249#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
250#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
251#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
252#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
253#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
254#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
255#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
256#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
257#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
258#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
259#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
260#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
261#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
262#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
263#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
264#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
265#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
266#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
267#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
268#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
269#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
270#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
271#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
272#define MX51_PAD_GPIO_1_19__DISP2_DAT6 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL)
273#define MX51_PAD_GPIO_1_29__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL)
274#define MX51_PAD_GPIO_1_30__DISP2_DAT8 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL)
275#define MX51_PAD_GPIO_1_31__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL)
276#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
277#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
278#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
279#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
280#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
281#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
282#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
283#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
284#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
285#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
286#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
287#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
288#define MX51_PAD_GPIO_1_0__GPIO1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
289#define MX51_PAD_GPIO_1_1__GPIO1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
290#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
291#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
292#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
293#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
294#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
295#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
296#define MX51_PAD_GPIO_1_2__GPIO1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
297#define MX51_PAD_GPIO_1_3__GPIO1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
298#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
299#define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
300#define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
301#define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
302#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, NO_PAD_CTRL)
303#define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
304 (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS))
305#define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
306
307/* EIM */
308#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL)
309#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL)
310#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL)
311#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL)
312#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL)
313#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL)
314#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL)
315#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL)
316
317#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL)
318#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL)
319#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL)
320#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL)
321#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL)
322#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL)
323#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL)
324#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL)
325
326#endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h
new file mode 100644
index 000000000000..884f5753f279
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h
@@ -0,0 +1,103 @@
1/*
2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3 * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19#ifndef __MACH_IOMUX_V1_H__
20#define __MACH_IOMUX_V1_H__
21
22/*
23* GPIO Module and I/O Multiplexer
24* x = 0..3 for reg_A, reg_B, reg_C, reg_D
25*/
26#define MXC_DDIR(x) (0x00 + ((x) << 8))
27#define MXC_OCR1(x) (0x04 + ((x) << 8))
28#define MXC_OCR2(x) (0x08 + ((x) << 8))
29#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
30#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
31#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
32#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
33#define MXC_DR(x) (0x1c + ((x) << 8))
34#define MXC_GIUS(x) (0x20 + ((x) << 8))
35#define MXC_SSR(x) (0x24 + ((x) << 8))
36#define MXC_ICR1(x) (0x28 + ((x) << 8))
37#define MXC_ICR2(x) (0x2c + ((x) << 8))
38#define MXC_IMR(x) (0x30 + ((x) << 8))
39#define MXC_ISR(x) (0x34 + ((x) << 8))
40#define MXC_GPR(x) (0x38 + ((x) << 8))
41#define MXC_SWR(x) (0x3c + ((x) << 8))
42#define MXC_PUEN(x) (0x40 + ((x) << 8))
43
44#define MX1_NUM_GPIO_PORT 4
45#define MX21_NUM_GPIO_PORT 6
46#define MX27_NUM_GPIO_PORT 6
47
48#define GPIO_PIN_MASK 0x1f
49
50#define GPIO_PORT_SHIFT 5
51#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
52
53#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
54#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
55#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
56#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
57#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
58#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
59
60#define GPIO_OUT (1 << 8)
61#define GPIO_IN (0 << 8)
62#define GPIO_PUEN (1 << 9)
63
64#define GPIO_PF (1 << 10)
65#define GPIO_AF (1 << 11)
66
67#define GPIO_OCR_SHIFT 12
68#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
69#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
70#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
71#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
72#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
73
74#define GPIO_AOUT_SHIFT 14
75#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
76#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
77#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
78#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
79#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
80
81#define GPIO_BOUT_SHIFT 16
82#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
83#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
84#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
85#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
86#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
87
88/* decode irq number to use with IMR(x), ISR(x) and friends */
89#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
90
91#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
92#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
93#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
94#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
95#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
96#define IRQ_GPIOF(x) (IRQ_GPIOE(32) + x)
97
98extern int mxc_gpio_mode(int gpio_mode);
99extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
100 const char *label);
101extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
102
103#endif /* __MACH_IOMUX_V1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 1deda0184892..f2f73d31d5ba 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -81,11 +81,13 @@ struct pad_desc {
81 81
82#define PAD_CTL_ODE (1 << 3) 82#define PAD_CTL_ODE (1 << 3)
83 83
84#define PAD_CTL_DSE_STANDARD (0 << 1) 84#define PAD_CTL_DSE_LOW (0 << 1)
85#define PAD_CTL_DSE_HIGH (1 << 1) 85#define PAD_CTL_DSE_MED (1 << 1)
86#define PAD_CTL_DSE_MAX (2 << 1) 86#define PAD_CTL_DSE_HIGH (2 << 1)
87#define PAD_CTL_DSE_MAX (3 << 1)
87 88
88#define PAD_CTL_SRE_FAST (1 << 0) 89#define PAD_CTL_SRE_FAST (1 << 0)
90#define PAD_CTL_SRE_SLOW (0 << 0)
89 91
90/* 92/*
91 * setups a single pad in the iomuxer 93 * setups a single pad in the iomuxer
diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h
index 011cfcd8b820..3d226d7e7be2 100644
--- a/arch/arm/plat-mxc/include/mach/iomux.h
+++ b/arch/arm/plat-mxc/include/mach/iomux.h
@@ -1,102 +1,14 @@
1/* 1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> 2 * Copyright (C) 2010 Uwe Kleine-Koenig, Pengutronix
3* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> 3 *
4* 4 * This program is free software; you can redistribute it and/or modify it
5* This program is free software; you can redistribute it and/or 5 * under the terms of the GNU General Public License version 2 as published by
6* modify it under the terms of the GNU General Public License 6 * the Free Software Foundation.
7* as published by the Free Software Foundation; either version 2 7 */
8* of the License, or (at your option) any later version. 8#ifndef __MACH_IOMUX_H__
9* This program is distributed in the hope that it will be useful, 9#define __MACH_IOMUX_H__
10* but WITHOUT ANY WARRANTY; without even the implied warranty of
11* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12* GNU General Public License for more details.
13*
14* You should have received a copy of the GNU General Public License
15* along with this program; if not, write to the Free Software
16* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17* MA 02110-1301, USA.
18*/
19
20#ifndef _MXC_IOMUX_H
21#define _MXC_IOMUX_H
22
23/*
24* GPIO Module and I/O Multiplexer
25* x = 0..3 for reg_A, reg_B, reg_C, reg_D
26*/
27#define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR)
28#define MXC_DDIR(x) (0x00 + ((x) << 8))
29#define MXC_OCR1(x) (0x04 + ((x) << 8))
30#define MXC_OCR2(x) (0x08 + ((x) << 8))
31#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
32#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
33#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
34#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
35#define MXC_DR(x) (0x1c + ((x) << 8))
36#define MXC_GIUS(x) (0x20 + ((x) << 8))
37#define MXC_SSR(x) (0x24 + ((x) << 8))
38#define MXC_ICR1(x) (0x28 + ((x) << 8))
39#define MXC_ICR2(x) (0x2c + ((x) << 8))
40#define MXC_IMR(x) (0x30 + ((x) << 8))
41#define MXC_ISR(x) (0x34 + ((x) << 8))
42#define MXC_GPR(x) (0x38 + ((x) << 8))
43#define MXC_SWR(x) (0x3c + ((x) << 8))
44#define MXC_PUEN(x) (0x40 + ((x) << 8))
45
46#ifdef CONFIG_ARCH_MX1
47# define GPIO_PORT_MAX 3
48#endif
49#ifdef CONFIG_ARCH_MX2
50# define GPIO_PORT_MAX 5
51#endif
52#ifdef CONFIG_ARCH_MX25
53# define GPIO_PORT_MAX 3
54#endif
55
56#ifndef GPIO_PORT_MAX
57# error "GPIO config port count unknown!"
58#endif
59
60#define GPIO_PIN_MASK 0x1f
61
62#define GPIO_PORT_SHIFT 5
63#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
64
65#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
66#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
67#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
68#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
69#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
70#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
71
72#define GPIO_OUT (1 << 8)
73#define GPIO_IN (0 << 8)
74#define GPIO_PUEN (1 << 9)
75
76#define GPIO_PF (1 << 10)
77#define GPIO_AF (1 << 11)
78
79#define GPIO_OCR_SHIFT 12
80#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
81#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
82#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
83#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
84#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
85
86#define GPIO_AOUT_SHIFT 14
87#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
88#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
89#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
90#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
91#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
92
93#define GPIO_BOUT_SHIFT 16
94#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
95#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
96#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
97#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
98#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
99 10
11/* This file will go away, please include mach/iomux-mx... directly */
100 12
101#ifdef CONFIG_ARCH_MX1 13#ifdef CONFIG_ARCH_MX1
102#include <mach/iomux-mx1.h> 14#include <mach/iomux-mx1.h>
@@ -110,25 +22,5 @@
110#include <mach/iomux-mx27.h> 22#include <mach/iomux-mx27.h>
111#endif 23#endif
112#endif 24#endif
113#ifdef CONFIG_ARCH_MX25
114#include <mach/iomux-mx25.h>
115#endif
116 25
117 26#endif /* __MACH_IOMUX_H__ */
118/* decode irq number to use with IMR(x), ISR(x) and friends */
119#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
120
121#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
122#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
123#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
124#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
125#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
126#define IRQ_GPIOF(x) (IRQ_GPIOE(32) + x)
127
128
129extern void mxc_gpio_mode(int gpio_mode);
130extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
131 const char *label);
132extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
133
134#endif
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 0cb347645db4..86781f7b0c0c 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -12,22 +12,29 @@
12#define __ASM_ARCH_MXC_IRQS_H__ 12#define __ASM_ARCH_MXC_IRQS_H__
13 13
14/* 14/*
15 * So far all i.MX SoCs have 64 internal interrupts 15 * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
16 */ 16 */
17#ifdef CONFIG_MXC_TZIC
18#define MXC_INTERNAL_IRQS 128
19#else
17#define MXC_INTERNAL_IRQS 64 20#define MXC_INTERNAL_IRQS 64
21#endif
18 22
19#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS 23#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
20 24
21#if defined CONFIG_ARCH_MX1 25/* these are ordered by size to support multi-SoC kernels */
22#define MXC_GPIO_IRQS (32 * 4) 26#if defined CONFIG_ARCH_MX2
23#elif defined CONFIG_ARCH_MX2
24#define MXC_GPIO_IRQS (32 * 6) 27#define MXC_GPIO_IRQS (32 * 6)
25#elif defined CONFIG_ARCH_MX3 28#elif defined CONFIG_ARCH_MX1
26#define MXC_GPIO_IRQS (32 * 3) 29#define MXC_GPIO_IRQS (32 * 4)
27#elif defined CONFIG_ARCH_MX25 30#elif defined CONFIG_ARCH_MX25
28#define MXC_GPIO_IRQS (32 * 4) 31#define MXC_GPIO_IRQS (32 * 4)
32#elif defined CONFIG_ARCH_MX5
33#define MXC_GPIO_IRQS (32 * 4)
29#elif defined CONFIG_ARCH_MXC91231 34#elif defined CONFIG_ARCH_MXC91231
30#define MXC_GPIO_IRQS (32 * 4) 35#define MXC_GPIO_IRQS (32 * 4)
36#elif defined CONFIG_ARCH_MX3
37#define MXC_GPIO_IRQS (32 * 3)
31#endif 38#endif
32 39
33/* 40/*
@@ -51,6 +58,7 @@
51#else 58#else
52#define MX3_IPU_IRQS 0 59#define MX3_IPU_IRQS 0
53#endif 60#endif
61/* REVISIT: Add IPU irqs on IMX51 */
54 62
55#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) 63#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
56 64
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index d3afafdcc0e5..c4b40c35a6a1 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -11,37 +11,45 @@
11#ifndef __ASM_ARCH_MXC_MEMORY_H__ 11#ifndef __ASM_ARCH_MXC_MEMORY_H__
12#define __ASM_ARCH_MXC_MEMORY_H__ 12#define __ASM_ARCH_MXC_MEMORY_H__
13 13
14#if defined CONFIG_ARCH_MX1 14#define MX1_PHYS_OFFSET UL(0x08000000)
15#define PHYS_OFFSET UL(0x08000000) 15#define MX21_PHYS_OFFSET UL(0xc0000000)
16#elif defined CONFIG_ARCH_MX2 16#define MX25_PHYS_OFFSET UL(0x80000000)
17#ifdef CONFIG_MACH_MX21 17#define MX27_PHYS_OFFSET UL(0xa0000000)
18#define PHYS_OFFSET UL(0xC0000000) 18#define MX3x_PHYS_OFFSET UL(0x80000000)
19#endif 19#define MX51_PHYS_OFFSET UL(0x90000000)
20#ifdef CONFIG_MACH_MX27 20#define MXC91231_PHYS_OFFSET UL(0x90000000)
21#define PHYS_OFFSET UL(0xA0000000) 21
22#endif 22#if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
23#elif defined CONFIG_ARCH_MX3 23# if defined CONFIG_ARCH_MX1
24#define PHYS_OFFSET UL(0x80000000) 24# define PHYS_OFFSET MX1_PHYS_OFFSET
25#elif defined CONFIG_ARCH_MX25 25# elif defined CONFIG_MACH_MX21
26#define PHYS_OFFSET UL(0x80000000) 26# define PHYS_OFFSET MX21_PHYS_OFFSET
27#elif defined CONFIG_ARCH_MXC91231 27# elif defined CONFIG_ARCH_MX25
28#define PHYS_OFFSET UL(0x90000000) 28# define PHYS_OFFSET MX25_PHYS_OFFSET
29# elif defined CONFIG_MACH_MX27
30# define PHYS_OFFSET MX27_PHYS_OFFSET
31# elif defined CONFIG_ARCH_MX3
32# define PHYS_OFFSET MX3x_PHYS_OFFSET
33# elif defined CONFIG_ARCH_MXC91231
34# define PHYS_OFFSET MXC91231_PHYS_OFFSET
35# elif defined CONFIG_ARCH_MX5
36# define PHYS_OFFSET MX51_PHYS_OFFSET
37# endif
29#endif 38#endif
30 39
31#if defined(CONFIG_MX1_VIDEO) 40#if defined(CONFIG_MX3_VIDEO)
32/* 41/*
33 * Increase size of DMA-consistent memory region. 42 * Increase size of DMA-consistent memory region.
34 * This is required for i.MX camera driver to capture at least four VGA frames. 43 * This is required for mx3 camera driver to capture at least two QXGA frames.
35 */ 44 */
36#define CONSISTENT_DMA_SIZE SZ_4M 45#define CONSISTENT_DMA_SIZE SZ_8M
37#endif /* CONFIG_MX1_VIDEO */
38 46
39#if defined(CONFIG_MX3_VIDEO) 47#elif defined(CONFIG_MX1_VIDEO)
40/* 48/*
41 * Increase size of DMA-consistent memory region. 49 * Increase size of DMA-consistent memory region.
42 * This is required for mx3 camera driver to capture at least two QXGA frames. 50 * This is required for i.MX camera driver to capture at least four VGA frames.
43 */ 51 */
44#define CONSISTENT_DMA_SIZE SZ_8M 52#define CONSISTENT_DMA_SIZE SZ_4M
45#endif /* CONFIG_MX3_VIDEO */ 53#endif /* CONFIG_MX1_VIDEO */
46 54
47#endif /* __ASM_ARCH_MXC_MEMORY_H__ */ 55#endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mtd-xip.h b/arch/arm/plat-mxc/include/mach/mtd-xip.h
deleted file mode 100644
index 1ab1bba5688d..000000000000
--- a/arch/arm/plat-mxc/include/mach/mtd-xip.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * MTD primitives for XIP support. Architecture specific functions
3 *
4 * Do not include this file directly. It's included from linux/mtd/xip.h
5 *
6 * Copyright (C) 2008 Darius Augulis <augulis.darius@gmail.com>, Teltonika, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <mach/mxc_timer.h>
15
16#ifndef __ARCH_IMX_MTD_XIP_H__
17#define __ARCH_IMX_MTD_XIP_H__
18
19#ifdef CONFIG_ARCH_MX1
20/* AITC registers */
21#define AITC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
22#define NIPNDH (AITC_BASE + 0x58)
23#define NIPNDL (AITC_BASE + 0x5C)
24#define INTENABLEH (AITC_BASE + 0x10)
25#define INTENABLEL (AITC_BASE + 0x14)
26/* MTD macros */
27#define xip_irqpending() ((__raw_readl(INTENABLEH) & __raw_readl(NIPNDH)) \
28 || (__raw_readl(INTENABLEL) & __raw_readl(NIPNDL)))
29#define xip_currtime() (__raw_readl(TIMER_BASE + MXC_TCN))
30#define xip_elapsed_since(x) (signed)((__raw_readl(TIMER_BASE + MXC_TCN) - (x)) / 96)
31#define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (0))
32#endif /* CONFIG_ARCH_MX1 */
33
34#endif /* __ARCH_IMX_MTD_XIP_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 1b2890a5c452..5eba7e6785de 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -9,156 +9,289 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#ifndef __ASM_ARCH_MXC_MX1_H__ 12#ifndef __MACH_MX1_H__
13#define __ASM_ARCH_MXC_MX1_H__ 13#define __MACH_MX1_H__
14 14
15#include <mach/vmalloc.h> 15#include <mach/vmalloc.h>
16 16
17/* 17/*
18 * Memory map 18 * Memory map
19 */ 19 */
20#define IMX_IO_PHYS 0x00200000 20#define MX1_IO_BASE_ADDR 0x00200000
21#define IMX_IO_SIZE 0x00100000 21#define MX1_IO_SIZE SZ_1M
22#define IMX_IO_BASE VMALLOC_END 22#define MX1_IO_BASE_ADDR_VIRT VMALLOC_END
23 23
24#define IMX_CS0_PHYS 0x10000000 24#define MX1_CS0_PHYS 0x10000000
25#define IMX_CS0_SIZE 0x02000000 25#define MX1_CS0_SIZE 0x02000000
26 26
27#define IMX_CS1_PHYS 0x12000000 27#define MX1_CS1_PHYS 0x12000000
28#define IMX_CS1_SIZE 0x01000000 28#define MX1_CS1_SIZE 0x01000000
29 29
30#define IMX_CS2_PHYS 0x13000000 30#define MX1_CS2_PHYS 0x13000000
31#define IMX_CS2_SIZE 0x01000000 31#define MX1_CS2_SIZE 0x01000000
32 32
33#define IMX_CS3_PHYS 0x14000000 33#define MX1_CS3_PHYS 0x14000000
34#define IMX_CS3_SIZE 0x01000000 34#define MX1_CS3_SIZE 0x01000000
35 35
36#define IMX_CS4_PHYS 0x15000000 36#define MX1_CS4_PHYS 0x15000000
37#define IMX_CS4_SIZE 0x01000000 37#define MX1_CS4_SIZE 0x01000000
38 38
39#define IMX_CS5_PHYS 0x16000000 39#define MX1_CS5_PHYS 0x16000000
40#define IMX_CS5_SIZE 0x01000000 40#define MX1_CS5_SIZE 0x01000000
41 41
42/* 42/*
43 * Register BASEs, based on OFFSETs 43 * Register BASEs, based on OFFSETs
44 */ 44 */
45#define AIPI1_BASE_ADDR (0x00000 + IMX_IO_PHYS) 45#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR)
46#define WDT_BASE_ADDR (0x01000 + IMX_IO_PHYS) 46#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR)
47#define TIM1_BASE_ADDR (0x02000 + IMX_IO_PHYS) 47#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR)
48#define TIM2_BASE_ADDR (0x03000 + IMX_IO_PHYS) 48#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR)
49#define RTC_BASE_ADDR (0x04000 + IMX_IO_PHYS) 49#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR)
50#define LCDC_BASE_ADDR (0x05000 + IMX_IO_PHYS) 50#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR)
51#define UART1_BASE_ADDR (0x06000 + IMX_IO_PHYS) 51#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR)
52#define UART2_BASE_ADDR (0x07000 + IMX_IO_PHYS) 52#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR)
53#define PWM_BASE_ADDR (0x08000 + IMX_IO_PHYS) 53#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR)
54#define DMA_BASE_ADDR (0x09000 + IMX_IO_PHYS) 54#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR)
55#define AIPI2_BASE_ADDR (0x10000 + IMX_IO_PHYS) 55#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR)
56#define SIM_BASE_ADDR (0x11000 + IMX_IO_PHYS) 56#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR)
57#define USBD_BASE_ADDR (0x12000 + IMX_IO_PHYS) 57#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR)
58#define SPI1_BASE_ADDR (0x13000 + IMX_IO_PHYS) 58#define MX1_SPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR)
59#define MMC_BASE_ADDR (0x14000 + IMX_IO_PHYS) 59#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR)
60#define ASP_BASE_ADDR (0x15000 + IMX_IO_PHYS) 60#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR)
61#define BTA_BASE_ADDR (0x16000 + IMX_IO_PHYS) 61#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR)
62#define I2C_BASE_ADDR (0x17000 + IMX_IO_PHYS) 62#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR)
63#define SSI_BASE_ADDR (0x18000 + IMX_IO_PHYS) 63#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR)
64#define SPI2_BASE_ADDR (0x19000 + IMX_IO_PHYS) 64#define MX1_SPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR)
65#define MSHC_BASE_ADDR (0x1A000 + IMX_IO_PHYS) 65#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR)
66#define CCM_BASE_ADDR (0x1B000 + IMX_IO_PHYS) 66#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
67#define SCM_BASE_ADDR (0x1B804 + IMX_IO_PHYS) 67#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR)
68#define GPIO_BASE_ADDR (0x1C000 + IMX_IO_PHYS) 68#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
69#define EIM_BASE_ADDR (0x20000 + IMX_IO_PHYS) 69#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR)
70#define SDRAMC_BASE_ADDR (0x21000 + IMX_IO_PHYS) 70#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR)
71#define MMA_BASE_ADDR (0x22000 + IMX_IO_PHYS) 71#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR)
72#define AVIC_BASE_ADDR (0x23000 + IMX_IO_PHYS) 72#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR)
73#define CSI_BASE_ADDR (0x24000 + IMX_IO_PHYS) 73#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
74 74
75/* macro to get at IO space when running virtually */ 75/* macro to get at IO space when running virtually */
76#define IO_ADDRESS(x) ((x) - IMX_IO_PHYS + IMX_IO_BASE) 76#define MX1_IO_ADDRESS(x) ( \
77 77 IMX_IO_ADDRESS(x, MX1_IO))
78/* define macros needed for entry-macro.S */
79#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x)
80 78
81/* fixed interrput numbers */ 79/* fixed interrput numbers */
82#define INT_SOFTINT 0 80#define MX1_INT_SOFTINT 0
83#define CSI_INT 6 81#define MX1_CSI_INT 6
84#define DSPA_MAC_INT 7 82#define MX1_DSPA_MAC_INT 7
85#define DSPA_INT 8 83#define MX1_DSPA_INT 8
86#define COMP_INT 9 84#define MX1_COMP_INT 9
87#define MSHC_XINT 10 85#define MX1_MSHC_XINT 10
88#define GPIO_INT_PORTA 11 86#define MX1_GPIO_INT_PORTA 11
89#define GPIO_INT_PORTB 12 87#define MX1_GPIO_INT_PORTB 12
90#define GPIO_INT_PORTC 13 88#define MX1_GPIO_INT_PORTC 13
91#define LCDC_INT 14 89#define MX1_LCDC_INT 14
92#define SIM_INT 15 90#define MX1_SIM_INT 15
93#define SIM_DATA_INT 16 91#define MX1_SIM_DATA_INT 16
94#define RTC_INT 17 92#define MX1_RTC_INT 17
95#define RTC_SAMINT 18 93#define MX1_RTC_SAMINT 18
96#define UART2_MINT_PFERR 19 94#define MX1_UART2_MINT_PFERR 19
97#define UART2_MINT_RTS 20 95#define MX1_UART2_MINT_RTS 20
98#define UART2_MINT_DTR 21 96#define MX1_UART2_MINT_DTR 21
99#define UART2_MINT_UARTC 22 97#define MX1_UART2_MINT_UARTC 22
100#define UART2_MINT_TX 23 98#define MX1_UART2_MINT_TX 23
101#define UART2_MINT_RX 24 99#define MX1_UART2_MINT_RX 24
102#define UART1_MINT_PFERR 25 100#define MX1_UART1_MINT_PFERR 25
103#define UART1_MINT_RTS 26 101#define MX1_UART1_MINT_RTS 26
104#define UART1_MINT_DTR 27 102#define MX1_UART1_MINT_DTR 27
105#define UART1_MINT_UARTC 28 103#define MX1_UART1_MINT_UARTC 28
106#define UART1_MINT_TX 29 104#define MX1_UART1_MINT_TX 29
107#define UART1_MINT_RX 30 105#define MX1_UART1_MINT_RX 30
108#define VOICE_DAC_INT 31 106#define MX1_VOICE_DAC_INT 31
109#define VOICE_ADC_INT 32 107#define MX1_VOICE_ADC_INT 32
110#define PEN_DATA_INT 33 108#define MX1_PEN_DATA_INT 33
111#define PWM_INT 34 109#define MX1_PWM_INT 34
112#define SDHC_INT 35 110#define MX1_SDHC_INT 35
113#define I2C_INT 39 111#define MX1_I2C_INT 39
114#define CSPI_INT 41 112#define MX1_CSPI_INT 41
115#define SSI_TX_INT 42 113#define MX1_SSI_TX_INT 42
116#define SSI_TX_ERR_INT 43 114#define MX1_SSI_TX_ERR_INT 43
117#define SSI_RX_INT 44 115#define MX1_SSI_RX_INT 44
118#define SSI_RX_ERR_INT 45 116#define MX1_SSI_RX_ERR_INT 45
119#define TOUCH_INT 46 117#define MX1_TOUCH_INT 46
120#define USBD_INT0 47 118#define MX1_USBD_INT0 47
121#define USBD_INT1 48 119#define MX1_USBD_INT1 48
122#define USBD_INT2 49 120#define MX1_USBD_INT2 49
123#define USBD_INT3 50 121#define MX1_USBD_INT3 50
124#define USBD_INT4 51 122#define MX1_USBD_INT4 51
125#define USBD_INT5 52 123#define MX1_USBD_INT5 52
126#define USBD_INT6 53 124#define MX1_USBD_INT6 53
127#define BTSYS_INT 55 125#define MX1_BTSYS_INT 55
128#define BTTIM_INT 56 126#define MX1_BTTIM_INT 56
129#define BTWUI_INT 57 127#define MX1_BTWUI_INT 57
130#define TIM2_INT 58 128#define MX1_TIM2_INT 58
131#define TIM1_INT 59 129#define MX1_TIM1_INT 59
132#define DMA_ERR 60 130#define MX1_DMA_ERR 60
133#define DMA_INT 61 131#define MX1_DMA_INT 61
134#define GPIO_INT_PORTD 62 132#define MX1_GPIO_INT_PORTD 62
135#define WDT_INT 63 133#define MX1_WDT_INT 63
136 134
137/* DMA */ 135/* DMA */
138#define DMA_REQ_UART3_T 2 136#define MX1_DMA_REQ_UART3_T 2
139#define DMA_REQ_UART3_R 3 137#define MX1_DMA_REQ_UART3_R 3
140#define DMA_REQ_SSI2_T 4 138#define MX1_DMA_REQ_SSI2_T 4
141#define DMA_REQ_SSI2_R 5 139#define MX1_DMA_REQ_SSI2_R 5
142#define DMA_REQ_CSI_STAT 6 140#define MX1_DMA_REQ_CSI_STAT 6
143#define DMA_REQ_CSI_R 7 141#define MX1_DMA_REQ_CSI_R 7
144#define DMA_REQ_MSHC 8 142#define MX1_DMA_REQ_MSHC 8
145#define DMA_REQ_DSPA_DCT_DOUT 9 143#define MX1_DMA_REQ_DSPA_DCT_DOUT 9
146#define DMA_REQ_DSPA_DCT_DIN 10 144#define MX1_DMA_REQ_DSPA_DCT_DIN 10
147#define DMA_REQ_DSPA_MAC 11 145#define MX1_DMA_REQ_DSPA_MAC 11
148#define DMA_REQ_EXT 12 146#define MX1_DMA_REQ_EXT 12
149#define DMA_REQ_SDHC 13 147#define MX1_DMA_REQ_SDHC 13
150#define DMA_REQ_SPI1_R 14 148#define MX1_DMA_REQ_SPI1_R 14
151#define DMA_REQ_SPI1_T 15 149#define MX1_DMA_REQ_SPI1_T 15
152#define DMA_REQ_SSI_T 16 150#define MX1_DMA_REQ_SSI_T 16
153#define DMA_REQ_SSI_R 17 151#define MX1_DMA_REQ_SSI_R 17
154#define DMA_REQ_ASP_DAC 18 152#define MX1_DMA_REQ_ASP_DAC 18
155#define DMA_REQ_ASP_ADC 19 153#define MX1_DMA_REQ_ASP_ADC 19
156#define DMA_REQ_USP_EP(x) (20 + (x)) 154#define MX1_DMA_REQ_USP_EP(x) (20 + (x))
157#define DMA_REQ_SPI2_R 26 155#define MX1_DMA_REQ_SPI2_R 26
158#define DMA_REQ_SPI2_T 27 156#define MX1_DMA_REQ_SPI2_T 27
159#define DMA_REQ_UART2_T 28 157#define MX1_DMA_REQ_UART2_T 28
160#define DMA_REQ_UART2_R 29 158#define MX1_DMA_REQ_UART2_R 29
161#define DMA_REQ_UART1_T 30 159#define MX1_DMA_REQ_UART1_T 30
162#define DMA_REQ_UART1_R 31 160#define MX1_DMA_REQ_UART1_R 31
163 161
164#endif /* __ASM_ARCH_MXC_MX1_H__ */ 162/*
163 * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS
164 * to not break drivers/usb/gadget/imx_udc. Should go
165 * away after this driver uses the new name.
166 */
167#define USBD_INT0 MX1_USBD_INT0
168
169#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
170/* these should go away */
171#define IMX_IO_PHYS MX1_IO_BASE_ADDR
172#define IMX_IO_SIZE MX1_IO_SIZE
173#define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT
174#define IMX_CS0_PHYS MX1_CS0_PHYS
175#define IMX_CS0_SIZE MX1_CS0_SIZE
176#define IMX_CS1_PHYS MX1_CS1_PHYS
177#define IMX_CS1_SIZE MX1_CS1_SIZE
178#define IMX_CS2_PHYS MX1_CS2_PHYS
179#define IMX_CS2_SIZE MX1_CS2_SIZE
180#define IMX_CS3_PHYS MX1_CS3_PHYS
181#define IMX_CS3_SIZE MX1_CS3_SIZE
182#define IMX_CS4_PHYS MX1_CS4_PHYS
183#define IMX_CS4_SIZE MX1_CS4_SIZE
184#define IMX_CS5_PHYS MX1_CS5_PHYS
185#define IMX_CS5_SIZE MX1_CS5_SIZE
186#define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR
187#define WDT_BASE_ADDR MX1_WDT_BASE_ADDR
188#define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR
189#define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR
190#define RTC_BASE_ADDR MX1_RTC_BASE_ADDR
191#define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR
192#define UART1_BASE_ADDR MX1_UART1_BASE_ADDR
193#define UART2_BASE_ADDR MX1_UART2_BASE_ADDR
194#define PWM_BASE_ADDR MX1_PWM_BASE_ADDR
195#define DMA_BASE_ADDR MX1_DMA_BASE_ADDR
196#define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR
197#define SIM_BASE_ADDR MX1_SIM_BASE_ADDR
198#define USBD_BASE_ADDR MX1_USBD_BASE_ADDR
199#define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR
200#define MMC_BASE_ADDR MX1_MMC_BASE_ADDR
201#define ASP_BASE_ADDR MX1_ASP_BASE_ADDR
202#define BTA_BASE_ADDR MX1_BTA_BASE_ADDR
203#define I2C_BASE_ADDR MX1_I2C_BASE_ADDR
204#define SSI_BASE_ADDR MX1_SSI_BASE_ADDR
205#define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR
206#define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR
207#define CCM_BASE_ADDR MX1_CCM_BASE_ADDR
208#define SCM_BASE_ADDR MX1_SCM_BASE_ADDR
209#define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR
210#define EIM_BASE_ADDR MX1_EIM_BASE_ADDR
211#define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR
212#define MMA_BASE_ADDR MX1_MMA_BASE_ADDR
213#define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR
214#define CSI_BASE_ADDR MX1_CSI_BASE_ADDR
215#define IO_ADDRESS(x) MX1_IO_ADDRESS(x)
216#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x)
217#define INT_SOFTINT MX1_INT_SOFTINT
218#define CSI_INT MX1_CSI_INT
219#define DSPA_MAC_INT MX1_DSPA_MAC_INT
220#define DSPA_INT MX1_DSPA_INT
221#define COMP_INT MX1_COMP_INT
222#define MSHC_XINT MX1_MSHC_XINT
223#define GPIO_INT_PORTA MX1_GPIO_INT_PORTA
224#define GPIO_INT_PORTB MX1_GPIO_INT_PORTB
225#define GPIO_INT_PORTC MX1_GPIO_INT_PORTC
226#define LCDC_INT MX1_LCDC_INT
227#define SIM_INT MX1_SIM_INT
228#define SIM_DATA_INT MX1_SIM_DATA_INT
229#define RTC_INT MX1_RTC_INT
230#define RTC_SAMINT MX1_RTC_SAMINT
231#define UART2_MINT_PFERR MX1_UART2_MINT_PFERR
232#define UART2_MINT_RTS MX1_UART2_MINT_RTS
233#define UART2_MINT_DTR MX1_UART2_MINT_DTR
234#define UART2_MINT_UARTC MX1_UART2_MINT_UARTC
235#define UART2_MINT_TX MX1_UART2_MINT_TX
236#define UART2_MINT_RX MX1_UART2_MINT_RX
237#define UART1_MINT_PFERR MX1_UART1_MINT_PFERR
238#define UART1_MINT_RTS MX1_UART1_MINT_RTS
239#define UART1_MINT_DTR MX1_UART1_MINT_DTR
240#define UART1_MINT_UARTC MX1_UART1_MINT_UARTC
241#define UART1_MINT_TX MX1_UART1_MINT_TX
242#define UART1_MINT_RX MX1_UART1_MINT_RX
243#define VOICE_DAC_INT MX1_VOICE_DAC_INT
244#define VOICE_ADC_INT MX1_VOICE_ADC_INT
245#define PEN_DATA_INT MX1_PEN_DATA_INT
246#define PWM_INT MX1_PWM_INT
247#define SDHC_INT MX1_SDHC_INT
248#define I2C_INT MX1_I2C_INT
249#define CSPI_INT MX1_CSPI_INT
250#define SSI_TX_INT MX1_SSI_TX_INT
251#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT
252#define SSI_RX_INT MX1_SSI_RX_INT
253#define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT
254#define TOUCH_INT MX1_TOUCH_INT
255#define USBD_INT1 MX1_USBD_INT1
256#define USBD_INT2 MX1_USBD_INT2
257#define USBD_INT3 MX1_USBD_INT3
258#define USBD_INT4 MX1_USBD_INT4
259#define USBD_INT5 MX1_USBD_INT5
260#define USBD_INT6 MX1_USBD_INT6
261#define BTSYS_INT MX1_BTSYS_INT
262#define BTTIM_INT MX1_BTTIM_INT
263#define BTWUI_INT MX1_BTWUI_INT
264#define TIM2_INT MX1_TIM2_INT
265#define TIM1_INT MX1_TIM1_INT
266#define DMA_ERR MX1_DMA_ERR
267#define DMA_INT MX1_DMA_INT
268#define GPIO_INT_PORTD MX1_GPIO_INT_PORTD
269#define WDT_INT MX1_WDT_INT
270#define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T
271#define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R
272#define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T
273#define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R
274#define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT
275#define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R
276#define DMA_REQ_MSHC MX1_DMA_REQ_MSHC
277#define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT
278#define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN
279#define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC
280#define DMA_REQ_EXT MX1_DMA_REQ_EXT
281#define DMA_REQ_SDHC MX1_DMA_REQ_SDHC
282#define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R
283#define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T
284#define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T
285#define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R
286#define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC
287#define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC
288#define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x)
289#define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R
290#define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T
291#define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T
292#define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R
293#define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T
294#define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R
295#endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */
296
297#endif /* ifndef __MACH_MX1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index bb297d8765a7..ed98b9c9f389 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -22,8 +22,8 @@
22 * MA 02110-1301, USA. 22 * MA 02110-1301, USA.
23 */ 23 */
24 24
25#ifndef __ASM_ARCH_MXC_MX21_H__ 25#ifndef __MACH_MX21_H__
26#define __ASM_ARCH_MXC_MX21_H__ 26#define __MACH_MX21_H__
27 27
28#define MX21_AIPI_BASE_ADDR 0x10000000 28#define MX21_AIPI_BASE_ADDR 0x10000000
29#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000 29#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000
@@ -92,6 +92,11 @@
92 92
93#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ 93#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
94 94
95#define MX21_IO_ADDRESS(x) ( \
96 IMX_IO_ADDRESS(x, MX21_AIPI) ?: \
97 IMX_IO_ADDRESS(x, MX21_SAHB1) ?: \
98 IMX_IO_ADDRESS(x, MX21_X_MEMC))
99
95/* fixed interrupt numbers */ 100/* fixed interrupt numbers */
96#define MX21_INT_CSPI3 6 101#define MX21_INT_CSPI3 6
97#define MX21_INT_GPIO 8 102#define MX21_INT_GPIO 8
@@ -179,6 +184,7 @@
179#define MX21_DMA_REQ_CSI_STAT 30 184#define MX21_DMA_REQ_CSI_STAT 30
180#define MX21_DMA_REQ_CSI_RX 31 185#define MX21_DMA_REQ_CSI_RX 31
181 186
187#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
182/* these should go away */ 188/* these should go away */
183#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR 189#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
184#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR 190#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR
@@ -211,5 +217,6 @@
211#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX 217#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX
212#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX 218#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX
213#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX 219#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX
220#endif
214 221
215#endif /* __ASM_ARCH_MXC_MX21_H__ */ 222#endif /* ifndef __MACH_MX21_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 854e2dc58481..4eb6e334bda5 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -22,27 +22,27 @@
22#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000) 22#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000)
23#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000) 23#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000)
24 24
25#define MX25_AIPS1_IO_ADDRESS(x) \ 25#define MX25_IO_ADDRESS(x) ( \
26 (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT) 26 IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \
27#define MX25_AIPS2_IO_ADDRESS(x) \ 27 IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \
28 (((x) - MX25_AIPS2_BASE_ADDR) + MX25_AIPS2_BASE_ADDR_VIRT) 28 IMX_IO_ADDRESS(x, MX25_AVIC))
29#define MX25_AVIC_IO_ADDRESS(x) \
30 (((x) - MX25_AVIC_BASE_ADDR) + MX25_AVIC_BASE_ADDR_VIRT)
31 29
32#define __in_range(addr, name) ((addr) >= name##_BASE_ADDR && (addr) < name##_BASE_ADDR + name##_SIZE) 30#define MX25_UART1_BASE_ADDR 0x43f90000
33 31#define MX25_UART2_BASE_ADDR 0x43f94000
34#define MX25_IO_ADDRESS(x) \
35 (void __force __iomem *) \
36 (__in_range(x, MX25_AIPS1) ? MX25_AIPS1_IO_ADDRESS(x) : \
37 __in_range(x, MX25_AIPS2) ? MX25_AIPS2_IO_ADDRESS(x) : \
38 __in_range(x, MX25_AVIC) ? MX25_AVIC_IO_ADDRESS(x) : \
39 0xDEADBEEF)
40
41#define UART1_BASE_ADDR 0x43f90000
42#define UART2_BASE_ADDR 0x43f94000
43 32
44#define MX25_FEC_BASE_ADDR 0x50038000 33#define MX25_FEC_BASE_ADDR 0x50038000
34#define MX25_NFC_BASE_ADDR 0xbb000000
35#define MX25_DRYICE_BASE_ADDR 0x53ffc000
36#define MX25_LCDC_BASE_ADDR 0x53fbc000
45 37
38#define MX25_INT_DRYICE 25
46#define MX25_INT_FEC 57 39#define MX25_INT_FEC 57
40#define MX25_INT_NANDFC 33
41#define MX25_INT_LCDC 39
42
43#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS)
44#define UART1_BASE_ADDR MX25_UART1_BASE_ADDR
45#define UART2_BASE_ADDR MX25_UART2_BASE_ADDR
46#endif
47 47
48#endif /* __MACH_MX25_H__ */ 48#endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index e2ae19f51710..bae9cd75beee 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -21,8 +21,12 @@
21 * MA 02110-1301, USA. 21 * MA 02110-1301, USA.
22 */ 22 */
23 23
24#ifndef __ASM_ARCH_MXC_MX27_H__ 24#ifndef __MACH_MX27_H__
25#define __ASM_ARCH_MXC_MX27_H__ 25#define __MACH_MX27_H__
26
27#ifndef __ASSEMBLER__
28#include <linux/io.h>
29#endif
26 30
27#define MX27_AIPI_BASE_ADDR 0x10000000 31#define MX27_AIPI_BASE_ADDR 0x10000000
28#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000 32#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000
@@ -109,11 +113,31 @@
109#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) 113#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
110#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) 114#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
111 115
116#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
117#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
118#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
119#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
120
112#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000 121#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
113 122
114/* IRAM */ 123/* IRAM */
115#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ 124#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
116 125
126#define MX27_IO_ADDRESS(x) ( \
127 IMX_IO_ADDRESS(x, MX27_AIPI) ?: \
128 IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \
129 IMX_IO_ADDRESS(x, MX27_X_MEMC))
130
131#ifndef __ASSEMBLER__
132static inline void mx27_setup_weimcs(size_t cs,
133 unsigned upper, unsigned lower, unsigned addional)
134{
135 __raw_writel(upper, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(cs)));
136 __raw_writel(lower, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(cs)));
137 __raw_writel(addional, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(cs)));
138}
139#endif
140
117/* fixed interrupt numbers */ 141/* fixed interrupt numbers */
118#define MX27_INT_I2C2 1 142#define MX27_INT_I2C2 1
119#define MX27_INT_GPT6 2 143#define MX27_INT_GPT6 2
@@ -225,6 +249,7 @@
225extern int mx27_revision(void); 249extern int mx27_revision(void);
226#endif 250#endif
227 251
252#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
228/* these should go away */ 253/* these should go away */
229#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR 254#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR
230#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR 255#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR
@@ -292,5 +317,6 @@ extern int mx27_revision(void);
292#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX 317#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX
293#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3 318#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3
294#define DMA_REQ_NFC MX27_DMA_REQ_NFC 319#define DMA_REQ_NFC MX27_DMA_REQ_NFC
320#endif
295 321
296#endif /* __ASM_ARCH_MXC_MX27_H__ */ 322#endif /* ifndef __MACH_MX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index f2eaf140ed02..afb895a0b5b8 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -20,8 +20,8 @@
20 * MA 02110-1301, USA. 20 * MA 02110-1301, USA.
21 */ 21 */
22 22
23#ifndef __ASM_ARCH_MXC_MX2x_H__ 23#ifndef __MACH_MX2x_H__
24#define __ASM_ARCH_MXC_MX2x_H__ 24#define __MACH_MX2x_H__
25 25
26/* The following addresses are common between i.MX21 and i.MX27 */ 26/* The following addresses are common between i.MX21 and i.MX27 */
27 27
@@ -176,6 +176,7 @@
176#define MX2x_DMA_REQ_CSI_STAT 30 176#define MX2x_DMA_REQ_CSI_STAT 30
177#define MX2x_DMA_REQ_CSI_RX 31 177#define MX2x_DMA_REQ_CSI_RX 31
178 178
179#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
179/* these should go away */ 180/* these should go away */
180#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR 181#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
181#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT 182#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT
@@ -287,5 +288,6 @@
287#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX 288#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
288#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT 289#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
289#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX 290#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
291#endif
290 292
291#endif /* __ASM_ARCH_MXC_MX2x_H__ */ 293#endif /* ifndef __MACH_MX2x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index b8b47d139eb5..fb90e119c2b5 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -1,3 +1,10 @@
1#ifndef __MACH_MX31_H__
2#define __MACH_MX31_H__
3
4#ifndef __ASSEMBLER__
5#include <linux/io.h>
6#endif
7
1/* 8/*
2 * IRAM 9 * IRAM
3 */ 10 */
@@ -107,8 +114,30 @@
107#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000) 114#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
108#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR 115#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
109 116
117#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
118#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs))
119#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
120#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
121
110#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 122#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
111 123
124#define MX31_IO_ADDRESS(x) ( \
125 IMX_IO_ADDRESS(x, MX31_AIPS1) ?: \
126 IMX_IO_ADDRESS(x, MX31_AIPS2) ?: \
127 IMX_IO_ADDRESS(x, MX31_AVIC) ?: \
128 IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \
129 IMX_IO_ADDRESS(x, MX31_SPBA0))
130
131#ifndef __ASSEMBLER__
132static inline void mx31_setup_weimcs(size_t cs,
133 unsigned upper, unsigned lower, unsigned addional)
134{
135 __raw_writel(upper, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(cs)));
136 __raw_writel(lower, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(cs)));
137 __raw_writel(addional, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(cs)));
138}
139#endif
140
112#define MX31_INT_I2C3 3 141#define MX31_INT_I2C3 3
113#define MX31_INT_I2C2 4 142#define MX31_INT_I2C2 4
114#define MX31_INT_MPEG4_ENCODER 5 143#define MX31_INT_MPEG4_ENCODER 5
@@ -186,6 +215,7 @@
186#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0 215#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0
187#define MX31_SYSTEM_REV_NUM 3 216#define MX31_SYSTEM_REV_NUM 3
188 217
218#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
189/* these should go away */ 219/* these should go away */
190#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR 220#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
191#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR 221#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
@@ -216,3 +246,6 @@
216#define MXC_INT_UART5 MX31_INT_UART5 246#define MXC_INT_UART5 MX31_INT_UART5
217#define MXC_INT_CCM MX31_INT_CCM 247#define MXC_INT_CCM MX31_INT_CCM
218#define MXC_INT_PCMCIA MX31_INT_PCMCIA 248#define MXC_INT_PCMCIA MX31_INT_PCMCIA
249#endif
250
251#endif /* ifndef __MACH_MX31_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index af871bce35b6..526a55842ae5 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -1,3 +1,5 @@
1#ifndef __MACH_MX35_H__
2#define __MACH_MX35_H__
1/* 3/*
2 * IRAM 4 * IRAM
3 */ 5 */
@@ -104,6 +106,13 @@
104#define MX35_NFC_BASE_ADDR 0xbb000000 106#define MX35_NFC_BASE_ADDR 0xbb000000
105#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 107#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
106 108
109#define MX35_IO_ADDRESS(x) ( \
110 IMX_IO_ADDRESS(x, MX35_AIPS1) ?: \
111 IMX_IO_ADDRESS(x, MX35_AIPS2) ?: \
112 IMX_IO_ADDRESS(x, MX35_AVIC) ?: \
113 IMX_IO_ADDRESS(x, MX35_X_MEMC) ?: \
114 IMX_IO_ADDRESS(x, MX35_SPBA0))
115
107/* 116/*
108 * Interrupt numbers 117 * Interrupt numbers
109 */ 118 */
@@ -180,6 +189,7 @@
180#define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0 189#define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0
181#define MX35_SYSTEM_REV_NUM 3 190#define MX35_SYSTEM_REV_NUM 3
182 191
192#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
183/* these should go away */ 193/* these should go away */
184#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR 194#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
185#define MXC_INT_OWIRE MX35_INT_OWIRE 195#define MXC_INT_OWIRE MX35_INT_OWIRE
@@ -195,3 +205,6 @@
195#define MXC_INT_MLB MX35_INT_MLB 205#define MXC_INT_MLB MX35_INT_MLB
196#define MXC_INT_SPDIF MX35_INT_SPDIF 206#define MXC_INT_SPDIF MX35_INT_SPDIF
197#define MXC_INT_FEC MX35_INT_FEC 207#define MXC_INT_FEC MX35_INT_FEC
208#endif
209
210#endif /* ifndef __MACH_MX35_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index be69272407ad..7a356de385f5 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -8,8 +8,8 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#ifndef __ASM_ARCH_MXC_MX31_H__ 11#ifndef __MACH_MX3x_H__
12#define __ASM_ARCH_MXC_MX31_H__ 12#define __MACH_MX3x_H__
13 13
14/* 14/*
15 * MX31 memory map: 15 * MX31 memory map:
@@ -269,6 +269,7 @@ static inline int mx31_revision(void)
269} 269}
270#endif 270#endif
271 271
272#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
272/* these should go away */ 273/* these should go away */
273#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR 274#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR
274#define L2CC_SIZE MX3x_L2CC_SIZE 275#define L2CC_SIZE MX3x_L2CC_SIZE
@@ -401,5 +402,6 @@ static inline int mx31_revision(void)
401#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2 402#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2
402#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN 403#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN
403#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM 404#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM
405#endif
404 406
405#endif /* __ASM_ARCH_MXC_MX31_H__ */ 407#endif /* ifndef __MACH_MX3x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
new file mode 100644
index 000000000000..771532b6b4a6
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -0,0 +1,454 @@
1#ifndef __ASM_ARCH_MXC_MX51_H__
2#define __ASM_ARCH_MXC_MX51_H__
3
4/*
5 * MX51 memory map:
6 *
7 *
8 * Virt Phys Size What
9 * ---------------------------------------------------------------------------
10 * FA3E0000 1FFE0000 128K IRAM (SCCv2 RAM)
11 * 30000000 256M GPU
12 * 40000000 512M IPU
13 * FA200000 60000000 1M DEBUG
14 * FB100000 70000000 1M SPBA 0
15 * FB000000 73F00000 1M AIPS 1
16 * FB200000 83F00000 1M AIPS 2
17 * FA100000 8FFFC000 16K TZIC (interrupt controller)
18 * 90000000 256M CSD0 SDRAM/DDR
19 * A0000000 256M CSD1 SDRAM/DDR
20 * B0000000 128M CS0 Flash
21 * B8000000 128M CS1 Flash
22 * C0000000 128M CS2 Flash
23 * C8000000 64M CS3 Flash
24 * CC000000 32M CS4 SRAM
25 * CE000000 32M CS5 SRAM
26 * F9000000 CFFF0000 64K NFC (NAND Flash AXI)
27 *
28 */
29
30/*
31 * IRAM
32 */
33#define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
34#define MX51_IRAM_BASE_ADDR_VIRT 0xFA3E0000
35#define MX51_IRAM_PARTITIONS 16
36#define MX51_IRAM_PARTITIONS_TO1 12
37#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
38
39/*
40 * NFC
41 */
42#define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */
43#define MX51_NFC_AXI_BASE_ADDR_VIRT 0xF9000000
44#define MX51_NFC_AXI_SIZE SZ_64K
45
46/*
47 * Graphics Memory of GPU
48 */
49#define MX51_GPU_BASE_ADDR 0x20000000
50#define MX51_GPU2D_BASE_ADDR 0xD0000000
51
52#define MX51_TZIC_BASE_ADDR 0x8FFFC000
53#define MX51_TZIC_BASE_ADDR_VIRT 0xFA100000
54#define MX51_TZIC_SIZE SZ_16K
55
56#define MX51_DEBUG_BASE_ADDR 0x60000000
57#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000
58#define MX51_DEBUG_SIZE SZ_1M
59#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00001000)
60#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00002000)
61#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00003000)
62#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00004000)
63#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00005000)
64#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00006000)
65#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00007000)
66#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00008000)
67
68/*
69 * SPBA global module enabled #0
70 */
71#define MX51_SPBA0_BASE_ADDR 0x70000000
72#define MX51_SPBA0_BASE_ADDR_VIRT 0xFB100000
73#define MX51_SPBA0_SIZE SZ_1M
74
75#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000)
76#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000)
77#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000)
78#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000)
79#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000)
80#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000)
81#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000)
82#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000)
83#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000)
84#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000)
85#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000)
86#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000)
87
88/*
89 * defines for SPBA modules
90 */
91#define MX51_SPBA_SDHC1 0x04
92#define MX51_SPBA_SDHC2 0x08
93#define MX51_SPBA_UART3 0x0C
94#define MX51_SPBA_CSPI1 0x10
95#define MX51_SPBA_SSI2 0x14
96#define MX51_SPBA_SDHC3 0x20
97#define MX51_SPBA_SDHC4 0x24
98#define MX51_SPBA_SPDIF 0x28
99#define MX51_SPBA_ATA 0x30
100#define MX51_SPBA_SLIM 0x34
101#define MX51_SPBA_HSI2C 0x38
102#define MX51_SPBA_CTRL 0x3C
103
104/*
105 * AIPS 1
106 */
107#define MX51_AIPS1_BASE_ADDR 0x73F00000
108#define MX51_AIPS1_BASE_ADDR_VIRT 0xFB000000
109#define MX51_AIPS1_SIZE SZ_1M
110
111#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00080000)
112#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00084000)
113#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00088000)
114#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0008C000)
115#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00090000)
116#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00094000)
117#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00098000)
118#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0009C000)
119#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A0000)
120#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A4000)
121#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A8000)
122#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000AC000)
123#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B0000)
124#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B4000)
125#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B8000)
126#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000BC000)
127#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000C0000)
128#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D0000)
129#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D4000)
130#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D8000)
131
132/*
133 * Defines for modules using static and dynamic DMA channels
134 */
135#define MX51_MXC_DMA_CHANNEL_IRAM 30
136#define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL
137#define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL
138#define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL
139#define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL
140#define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL
141#define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL
142#define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL
143#define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL
144#define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL
145#define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL
146#define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL
147#define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL
148#ifdef CONFIG_SDMA_IRAM
149#define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1)
150#else /*CONFIG_SDMA_IRAM */
151#define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL
152#endif /*CONFIG_SDMA_IRAM */
153#define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL
154#define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL
155#define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL
156#define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL
157#define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL
158#define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL
159#define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL
160#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL
161#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL
162
163/*
164 * AIPS 2
165 */
166#define MX51_AIPS2_BASE_ADDR 0x83F00000
167#define MX51_AIPS2_BASE_ADDR_VIRT 0xFB200000
168#define MX51_AIPS2_SIZE SZ_1M
169
170#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00080000)
171#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00084000)
172#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00088000)
173#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00094000)
174#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00098000)
175#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x0009C000)
176#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000)
177#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000)
178#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000)
179#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000)
180#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000)
181#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000)
182#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000)
183#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000)
184#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000)
185#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000)
186#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000)
187#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000)
188#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D0000)
189#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D8000)
190#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D9000)
191#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DA000)
192#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DB000)
193#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DBF00)
194#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000)
195#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E0000)
196#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E4000)
197#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E8000)
198#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000EC000)
199#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F0000)
200#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F4000)
201#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000)
202
203/*
204 * Memory regions and CS
205 */
206#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
207#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
208#define MX51_CSD0_BASE_ADDR 0x90000000
209#define MX51_CSD1_BASE_ADDR 0xA0000000
210#define MX51_CS0_BASE_ADDR 0xB0000000
211#define MX51_CS1_BASE_ADDR 0xB8000000
212#define MX51_CS2_BASE_ADDR 0xC0000000
213#define MX51_CS3_BASE_ADDR 0xC8000000
214#define MX51_CS4_BASE_ADDR 0xCC000000
215#define MX51_CS5_BASE_ADDR 0xCE000000
216
217/* Does given address belongs to the specified memory region? */
218#define ADDRESS_IN_REGION(addr, start, size) \
219 (((addr) >= (start)) && ((addr) < (start)+(size)))
220
221/* Does given address belongs to the specified named `module'? */
222#define MX51_IS_MODULE(addr, module) \
223 ADDRESS_IN_REGION(addr, MX51_ ## module ## _BASE_ADDR, \
224 MX51_ ## module ## _SIZE)
225/*
226 * This macro defines the physical to virtual address mapping for all the
227 * peripheral modules. It is used by passing in the physical address as x
228 * and returning the virtual address. If the physical address is not mapped,
229 * it returns 0xDEADBEEF
230 */
231
232#define MX51_IO_ADDRESS(x) \
233 (void __iomem *) \
234 (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \
235 MX51_IS_MODULE(x, TZIC) ? MX51_TZIC_IO_ADDRESS(x) : \
236 MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \
237 MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \
238 MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \
239 MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
240 MX51_IS_MODULE(x, NFC_AXI) ? MX51_NFC_AXI_IO_ADDRESS(x) : \
241 0xDEADBEEF)
242
243/*
244 * define the address mapping macros: in physical address order
245 */
246#define MX51_IRAM_IO_ADDRESS(x) \
247 (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
248
249#define MX51_TZIC_IO_ADDRESS(x) \
250 (((x) - MX51_TZIC_BASE_ADDR) + MX51_TZIC_BASE_ADDR_VIRT)
251
252#define MX51_DEBUG_IO_ADDRESS(x) \
253 (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)
254
255#define MX51_SPBA0_IO_ADDRESS(x) \
256 (((x) - MX51_SPBA0_BASE_ADDR) + MX51_SPBA0_BASE_ADDR_VIRT)
257
258#define MX51_AIPS1_IO_ADDRESS(x) \
259 (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
260
261#define MX51_AIPS2_IO_ADDRESS(x) \
262 (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT)
263
264#define MX51_NFC_AXI_IO_ADDRESS(x) \
265 (((x) - MX51_NFC_AXI_BASE_ADDR) + MX51_NFC_AXI_BASE_ADDR_VIRT)
266
267#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0
268
269/*
270 * DMA request assignments
271 */
272#define MX51_DMA_REQ_SSI3_TX1 47
273#define MX51_DMA_REQ_SSI3_RX1 46
274#define MX51_DMA_REQ_SPDIF 45
275#define MX51_DMA_REQ_UART3_TX 44
276#define MX51_DMA_REQ_UART3_RX 43
277#define MX51_DMA_REQ_SLIM_B_TX 42
278#define MX51_DMA_REQ_SDHC4 41
279#define MX51_DMA_REQ_SDHC3 40
280#define MX51_DMA_REQ_CSPI_TX 39
281#define MX51_DMA_REQ_CSPI_RX 38
282#define MX51_DMA_REQ_SSI3_TX2 37
283#define MX51_DMA_REQ_IPU 36
284#define MX51_DMA_REQ_SSI3_RX2 35
285#define MX51_DMA_REQ_EPIT2 34
286#define MX51_DMA_REQ_CTI2_1 33
287#define MX51_DMA_REQ_EMI_WR 32
288#define MX51_DMA_REQ_CTI2_0 31
289#define MX51_DMA_REQ_EMI_RD 30
290#define MX51_DMA_REQ_SSI1_TX1 29
291#define MX51_DMA_REQ_SSI1_RX1 28
292#define MX51_DMA_REQ_SSI1_TX2 27
293#define MX51_DMA_REQ_SSI1_RX2 26
294#define MX51_DMA_REQ_SSI2_TX1 25
295#define MX51_DMA_REQ_SSI2_RX1 24
296#define MX51_DMA_REQ_SSI2_TX2 23
297#define MX51_DMA_REQ_SSI2_RX2 22
298#define MX51_DMA_REQ_SDHC2 21
299#define MX51_DMA_REQ_SDHC1 20
300#define MX51_DMA_REQ_UART1_TX 19
301#define MX51_DMA_REQ_UART1_RX 18
302#define MX51_DMA_REQ_UART2_TX 17
303#define MX51_DMA_REQ_UART2_RX 16
304#define MX51_DMA_REQ_GPU 15
305#define MX51_DMA_REQ_EXTREQ1 14
306#define MX51_DMA_REQ_FIRI_TX 13
307#define MX51_DMA_REQ_FIRI_RX 12
308#define MX51_DMA_REQ_HS_I2C_RX 11
309#define MX51_DMA_REQ_HS_I2C_TX 10
310#define MX51_DMA_REQ_CSPI2_TX 9
311#define MX51_DMA_REQ_CSPI2_RX 8
312#define MX51_DMA_REQ_CSPI1_TX 7
313#define MX51_DMA_REQ_CSPI1_RX 6
314#define MX51_DMA_REQ_SLIM_B 5
315#define MX51_DMA_REQ_ATA_TX_END 4
316#define MX51_DMA_REQ_ATA_TX 3
317#define MX51_DMA_REQ_ATA_RX 2
318#define MX51_DMA_REQ_GPC 1
319#define MX51_DMA_REQ_VPU 0
320
321/*
322 * Interrupt numbers
323 */
324#define MX51_MXC_INT_BASE 0
325#define MX51_MXC_INT_RESV0 0
326#define MX51_MXC_INT_MMC_SDHC1 1
327#define MX51_MXC_INT_MMC_SDHC2 2
328#define MX51_MXC_INT_MMC_SDHC3 3
329#define MX51_MXC_INT_MMC_SDHC4 4
330#define MX51_MXC_INT_RESV5 5
331#define MX51_MXC_INT_SDMA 6
332#define MX51_MXC_INT_IOMUX 7
333#define MX51_MXC_INT_NFC 8
334#define MX51_MXC_INT_VPU 9
335#define MX51_MXC_INT_IPU_ERR 10
336#define MX51_MXC_INT_IPU_SYN 11
337#define MX51_MXC_INT_GPU 12
338#define MX51_MXC_INT_RESV13 13
339#define MX51_MXC_INT_USB_H1 14
340#define MX51_MXC_INT_EMI 15
341#define MX51_MXC_INT_USB_H2 16
342#define MX51_MXC_INT_USB_H3 17
343#define MX51_MXC_INT_USB_OTG 18
344#define MX51_MXC_INT_SAHARA_H0 19
345#define MX51_MXC_INT_SAHARA_H1 20
346#define MX51_MXC_INT_SCC_SMN 21
347#define MX51_MXC_INT_SCC_STZ 22
348#define MX51_MXC_INT_SCC_SCM 23
349#define MX51_MXC_INT_SRTC_NTZ 24
350#define MX51_MXC_INT_SRTC_TZ 25
351#define MX51_MXC_INT_RTIC 26
352#define MX51_MXC_INT_CSU 27
353#define MX51_MXC_INT_SLIM_B 28
354#define MX51_MXC_INT_SSI1 29
355#define MX51_MXC_INT_SSI2 30
356#define MX51_MXC_INT_UART1 31
357#define MX51_MXC_INT_UART2 32
358#define MX51_MXC_INT_UART3 33
359#define MX51_MXC_INT_RESV34 34
360#define MX51_MXC_INT_RESV35 35
361#define MX51_MXC_INT_CSPI1 36
362#define MX51_MXC_INT_CSPI2 37
363#define MX51_MXC_INT_CSPI 38
364#define MX51_MXC_INT_GPT 39
365#define MX51_MXC_INT_EPIT1 40
366#define MX51_MXC_INT_EPIT2 41
367#define MX51_MXC_INT_GPIO1_INT7 42
368#define MX51_MXC_INT_GPIO1_INT6 43
369#define MX51_MXC_INT_GPIO1_INT5 44
370#define MX51_MXC_INT_GPIO1_INT4 45
371#define MX51_MXC_INT_GPIO1_INT3 46
372#define MX51_MXC_INT_GPIO1_INT2 47
373#define MX51_MXC_INT_GPIO1_INT1 48
374#define MX51_MXC_INT_GPIO1_INT0 49
375#define MX51_MXC_INT_GPIO1_LOW 50
376#define MX51_MXC_INT_GPIO1_HIGH 51
377#define MX51_MXC_INT_GPIO2_LOW 52
378#define MX51_MXC_INT_GPIO2_HIGH 53
379#define MX51_MXC_INT_GPIO3_LOW 54
380#define MX51_MXC_INT_GPIO3_HIGH 55
381#define MX51_MXC_INT_GPIO4_LOW 56
382#define MX51_MXC_INT_GPIO4_HIGH 57
383#define MX51_MXC_INT_WDOG1 58
384#define MX51_MXC_INT_WDOG2 59
385#define MX51_MXC_INT_KPP 60
386#define MX51_MXC_INT_PWM1 61
387#define MX51_MXC_INT_I2C1 62
388#define MX51_MXC_INT_I2C2 63
389#define MX51_MXC_INT_HS_I2C 64
390#define MX51_MXC_INT_RESV65 65
391#define MX51_MXC_INT_RESV66 66
392#define MX51_MXC_INT_SIM_IPB 67
393#define MX51_MXC_INT_SIM_DAT 68
394#define MX51_MXC_INT_IIM 69
395#define MX51_MXC_INT_ATA 70
396#define MX51_MXC_INT_CCM1 71
397#define MX51_MXC_INT_CCM2 72
398#define MX51_MXC_INT_GPC1 73
399#define MX51_MXC_INT_GPC2 74
400#define MX51_MXC_INT_SRC 75
401#define MX51_MXC_INT_NM 76
402#define MX51_MXC_INT_PMU 77
403#define MX51_MXC_INT_CTI_IRQ 78
404#define MX51_MXC_INT_CTI1_TG0 79
405#define MX51_MXC_INT_CTI1_TG1 80
406#define MX51_MXC_INT_MCG_ERR 81
407#define MX51_MXC_INT_MCG_TMR 82
408#define MX51_MXC_INT_MCG_FUNC 83
409#define MX51_MXC_INT_GPU2_IRQ 84
410#define MX51_MXC_INT_GPU2_BUSY 85
411#define MX51_MXC_INT_RESV86 86
412#define MX51_MXC_INT_FEC 87
413#define MX51_MXC_INT_OWIRE 88
414#define MX51_MXC_INT_CTI1_TG2 89
415#define MX51_MXC_INT_SJC 90
416#define MX51_MXC_INT_SPDIF 91
417#define MX51_MXC_INT_TVE 92
418#define MX51_MXC_INT_FIRI 93
419#define MX51_MXC_INT_PWM2 94
420#define MX51_MXC_INT_SLIM_EXP 95
421#define MX51_MXC_INT_SSI3 96
422#define MX51_MXC_INT_EMI_BOOT 97
423#define MX51_MXC_INT_CTI1_TG3 98
424#define MX51_MXC_INT_SMC_RX 99
425#define MX51_MXC_INT_VPU_IDLE 100
426#define MX51_MXC_INT_EMI_NFC 101
427#define MX51_MXC_INT_GPU_IDLE 102
428
429/* silicon revisions specific to i.MX51 */
430#define MX51_CHIP_REV_1_0 0x10
431#define MX51_CHIP_REV_1_1 0x11
432#define MX51_CHIP_REV_1_2 0x12
433#define MX51_CHIP_REV_1_3 0x13
434#define MX51_CHIP_REV_2_0 0x20
435#define MX51_CHIP_REV_2_1 0x21
436#define MX51_CHIP_REV_2_2 0x22
437#define MX51_CHIP_REV_2_3 0x23
438#define MX51_CHIP_REV_3_0 0x30
439#define MX51_CHIP_REV_3_1 0x31
440#define MX51_CHIP_REV_3_2 0x32
441
442/* Mandatory defines used globally */
443
444#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
445
446extern unsigned int system_rev;
447
448static inline unsigned int mx51_revision(void)
449{
450 return system_rev;
451}
452#endif
453
454#endif /* __ASM_ARCH_MXC_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 51990536b845..a790bf212972 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -30,6 +30,7 @@
30#define MXC_CPU_MX27 27 30#define MXC_CPU_MX27 27
31#define MXC_CPU_MX31 31 31#define MXC_CPU_MX31 31
32#define MXC_CPU_MX35 35 32#define MXC_CPU_MX35 35
33#define MXC_CPU_MX51 51
33#define MXC_CPU_MXC91231 91231 34#define MXC_CPU_MXC91231 91231
34 35
35#ifndef __ASSEMBLY__ 36#ifndef __ASSEMBLY__
@@ -108,6 +109,18 @@ extern unsigned int __mxc_cpu_type;
108# define cpu_is_mx35() (0) 109# define cpu_is_mx35() (0)
109#endif 110#endif
110 111
112#ifdef CONFIG_ARCH_MX5
113# ifdef mxc_cpu_type
114# undef mxc_cpu_type
115# define mxc_cpu_type __mxc_cpu_type
116# else
117# define mxc_cpu_type MXC_CPU_MX51
118# endif
119# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51)
120#else
121# define cpu_is_mx51() (0)
122#endif
123
111#ifdef CONFIG_ARCH_MXC91231 124#ifdef CONFIG_ARCH_MXC91231
112# ifdef mxc_cpu_type 125# ifdef mxc_cpu_type
113# undef mxc_cpu_type 126# undef mxc_cpu_type
@@ -121,9 +134,10 @@ extern unsigned int __mxc_cpu_type;
121#endif 134#endif
122 135
123#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) 136#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
124#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10) 137/* These are deprecated, use mx[23][157]_setup_weimcs instead. */
125#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4) 138#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10))
126#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8) 139#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x4))
140#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8))
127#endif 141#endif
128 142
129#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231()) 143#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231())
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
index 81484d1ef232..5182b986b785 100644
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -184,60 +184,22 @@
184#define MXC91231_CS4_BASE_ADDR 0xB4000000 184#define MXC91231_CS4_BASE_ADDR 0xB4000000
185#define MXC91231_CS5_BASE_ADDR 0xB6000000 185#define MXC91231_CS5_BASE_ADDR 0xB6000000
186 186
187/* Is given address belongs to the specified memory region? */
188#define ADDRESS_IN_REGION(addr, start, size) \
189 (((addr) >= (start)) && ((addr) < (start)+(size)))
190
191/* Is given address belongs to the specified named `module'? */
192#define MXC91231_IS_MODULE(addr, module) \
193 ADDRESS_IN_REGION(addr, MXC91231_ ## module ## _BASE_ADDR, \
194 MXC91231_ ## module ## _SIZE)
195/* 187/*
196 * This macro defines the physical to virtual address mapping for all the 188 * This macro defines the physical to virtual address mapping for all the
197 * peripheral modules. It is used by passing in the physical address as x 189 * peripheral modules. It is used by passing in the physical address as x
198 * and returning the virtual address. If the physical address is not mapped, 190 * and returning the virtual address. If the physical address is not mapped,
199 * it returns 0xDEADBEEF 191 * it returns 0.
200 */
201
202#define MXC91231_IO_ADDRESS(x) \
203 (void __iomem *) \
204 (MXC91231_IS_MODULE(x, L2CC) ? MXC91231_L2CC_IO_ADDRESS(x) : \
205 MXC91231_IS_MODULE(x, AIPS1) ? MXC91231_AIPS1_IO_ADDRESS(x) : \
206 MXC91231_IS_MODULE(x, AIPS2) ? MXC91231_AIPS2_IO_ADDRESS(x) : \
207 MXC91231_IS_MODULE(x, SPBA0) ? MXC91231_SPBA0_IO_ADDRESS(x) : \
208 MXC91231_IS_MODULE(x, SPBA1) ? MXC91231_SPBA1_IO_ADDRESS(x) : \
209 MXC91231_IS_MODULE(x, ROMP) ? MXC91231_ROMP_IO_ADDRESS(x) : \
210 MXC91231_IS_MODULE(x, AVIC) ? MXC91231_AVIC_IO_ADDRESS(x) : \
211 MXC91231_IS_MODULE(x, X_MEMC) ? MXC91231_X_MEMC_IO_ADDRESS(x) : \
212 0xDEADBEEF)
213
214
215/*
216 * define the address mapping macros: in physical address order
217 */ 192 */
218#define MXC91231_L2CC_IO_ADDRESS(x) \
219 (((x) - MXC91231_L2CC_BASE_ADDR) + MXC91231_L2CC_BASE_ADDR_VIRT)
220
221#define MXC91231_AIPS1_IO_ADDRESS(x) \
222 (((x) - MXC91231_AIPS1_BASE_ADDR) + MXC91231_AIPS1_BASE_ADDR_VIRT)
223
224#define MXC91231_SPBA0_IO_ADDRESS(x) \
225 (((x) - MXC91231_SPBA0_BASE_ADDR) + MXC91231_SPBA0_BASE_ADDR_VIRT)
226
227#define MXC91231_SPBA1_IO_ADDRESS(x) \
228 (((x) - MXC91231_SPBA1_BASE_ADDR) + MXC91231_SPBA1_BASE_ADDR_VIRT)
229
230#define MXC91231_AIPS2_IO_ADDRESS(x) \
231 (((x) - MXC91231_AIPS2_BASE_ADDR) + MXC91231_AIPS2_BASE_ADDR_VIRT)
232
233#define MXC91231_ROMP_IO_ADDRESS(x) \
234 (((x) - MXC91231_ROMP_BASE_ADDR) + MXC91231_ROMP_BASE_ADDR_VIRT)
235
236#define MXC91231_AVIC_IO_ADDRESS(x) \
237 (((x) - MXC91231_AVIC_BASE_ADDR) + MXC91231_AVIC_BASE_ADDR_VIRT)
238 193
239#define MXC91231_X_MEMC_IO_ADDRESS(x) \ 194#define MXC91231_IO_ADDRESS(x) ( \
240 (((x) - MXC91231_X_MEMC_BASE_ADDR) + MXC91231_X_MEMC_BASE_ADDR_VIRT) 195 IMX_IO_ADDRESS(x, MXC91231_L2CC) ?: \
196 IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?: \
197 IMX_IO_ADDRESS(x, MXC91231_ROMP) ?: \
198 IMX_IO_ADDRESS(x, MXC91231_AVIC) ?: \
199 IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?: \
200 IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?: \
201 IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?: \
202 IMX_IO_ADDRESS(x, MXC91231_AIPS2))
241 203
242/* 204/*
243 * Interrupt numbers 205 * Interrupt numbers
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
index 8f796239393e..4b9b8368c0c0 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
@@ -22,6 +22,10 @@
22#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) 22#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
23#define MXC_EHCI_TTL_ENABLED (1 << 6) 23#define MXC_EHCI_TTL_ENABLED (1 << 6)
24 24
25#define MXC_EHCI_INTERNAL_PHY (1 << 7)
26#define MXC_EHCI_IPPUE_DOWN (1 << 8)
27#define MXC_EHCI_IPPUE_UP (1 << 9)
28
25struct mxc_usbh_platform_data { 29struct mxc_usbh_platform_data {
26 int (*init)(struct platform_device *pdev); 30 int (*init)(struct platform_device *pdev);
27 int (*exit)(struct platform_device *pdev); 31 int (*exit)(struct platform_device *pdev);
diff --git a/arch/arm/plat-mxc/include/mach/ssi.h b/arch/arm/plat-mxc/include/mach/ssi.h
new file mode 100644
index 000000000000..c34ded523f10
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/ssi.h
@@ -0,0 +1,18 @@
1#ifndef __MACH_SSI_H
2#define __MACH_SSI_H
3
4struct snd_ac97;
5
6extern unsigned char imx_ssi_fiq_start, imx_ssi_fiq_end;
7extern unsigned long imx_ssi_fiq_base, imx_ssi_fiq_tx_buffer, imx_ssi_fiq_rx_buffer;
8
9struct imx_ssi_platform_data {
10 unsigned int flags;
11#define IMX_SSI_DMA (1 << 0)
12#define IMX_SSI_USE_AC97 (1 << 1)
13 void (*ac97_reset) (struct snd_ac97 *ac97);
14 void (*ac97_warm_reset)(struct snd_ac97 *ac97);
15};
16
17#endif /* __MACH_SSI_H */
18
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 527a6c24788e..024416ed11cd 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -28,6 +28,8 @@
28#define CLOCK_TICK_RATE 16625000 28#define CLOCK_TICK_RATE 16625000
29#elif defined CONFIG_ARCH_MX25 29#elif defined CONFIG_ARCH_MX25
30#define CLOCK_TICK_RATE 16000000 30#define CLOCK_TICK_RATE 16000000
31#elif defined CONFIG_ARCH_MX5
32#define CLOCK_TICK_RATE 8000000
31#elif defined CONFIG_ARCH_MXC91231 33#elif defined CONFIG_ARCH_MXC91231
32#define CLOCK_TICK_RATE 13000000 34#define CLOCK_TICK_RATE 13000000
33#endif 35#endif
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index d49384cb1e97..52e476a150ca 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -1,8 +1,6 @@
1/* 1/*
2 * arch/arm/plat-mxc/include/mach/uncompress.h 2 * arch/arm/plat-mxc/include/mach/uncompress.h
3 * 3 *
4 *
5 *
6 * Copyright (C) 1999 ARM Limited 4 * Copyright (C) 1999 ARM Limited
7 * Copyright (C) Shane Nay (shane@minirl.com) 5 * Copyright (C) Shane Nay (shane@minirl.com)
8 * 6 *
@@ -25,7 +23,6 @@
25 23
26#define __MXC_BOOT_UNCOMPRESS 24#define __MXC_BOOT_UNCOMPRESS
27 25
28#include <mach/hardware.h>
29#include <asm/mach-types.h> 26#include <asm/mach-types.h>
30 27
31static unsigned long uart_base; 28static unsigned long uart_base;
diff --git a/arch/arm/plat-mxc/iomux-mx1-mx2.c b/arch/arm/plat-mxc/iomux-mx1-mx2.c
deleted file mode 100644
index a37163ce280b..000000000000
--- a/arch/arm/plat-mxc/iomux-mx1-mx2.c
+++ /dev/null
@@ -1,157 +0,0 @@
1/*
2 * arch/arm/mach-mxc/generic.c
3 *
4 * author: Sascha Hauer
5 * Created: april 20th, 2004
6 * Copyright: Synertronixx GmbH
7 *
8 * Common code for i.MX machines
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#include <linux/errno.h>
27#include <linux/init.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/string.h>
31#include <linux/gpio.h>
32
33#include <mach/hardware.h>
34#include <asm/mach/map.h>
35#include <mach/iomux.h>
36
37void mxc_gpio_mode(int gpio_mode)
38{
39 unsigned int pin = gpio_mode & GPIO_PIN_MASK;
40 unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
41 unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
42 unsigned int tmp;
43
44 /* Pullup enable */
45 tmp = __raw_readl(VA_GPIO_BASE + MXC_PUEN(port));
46 if (gpio_mode & GPIO_PUEN)
47 tmp |= (1 << pin);
48 else
49 tmp &= ~(1 << pin);
50 __raw_writel(tmp, VA_GPIO_BASE + MXC_PUEN(port));
51
52 /* Data direction */
53 tmp = __raw_readl(VA_GPIO_BASE + MXC_DDIR(port));
54 if (gpio_mode & GPIO_OUT)
55 tmp |= 1 << pin;
56 else
57 tmp &= ~(1 << pin);
58 __raw_writel(tmp, VA_GPIO_BASE + MXC_DDIR(port));
59
60 /* Primary / alternate function */
61 tmp = __raw_readl(VA_GPIO_BASE + MXC_GPR(port));
62 if (gpio_mode & GPIO_AF)
63 tmp |= (1 << pin);
64 else
65 tmp &= ~(1 << pin);
66 __raw_writel(tmp, VA_GPIO_BASE + MXC_GPR(port));
67
68 /* use as gpio? */
69 tmp = __raw_readl(VA_GPIO_BASE + MXC_GIUS(port));
70 if (gpio_mode & (GPIO_PF | GPIO_AF))
71 tmp &= ~(1 << pin);
72 else
73 tmp |= (1 << pin);
74 __raw_writel(tmp, VA_GPIO_BASE + MXC_GIUS(port));
75
76 if (pin < 16) {
77 tmp = __raw_readl(VA_GPIO_BASE + MXC_OCR1(port));
78 tmp &= ~(3 << (pin * 2));
79 tmp |= (ocr << (pin * 2));
80 __raw_writel(tmp, VA_GPIO_BASE + MXC_OCR1(port));
81
82 tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFA1(port));
83 tmp &= ~(3 << (pin * 2));
84 tmp |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2);
85 __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFA1(port));
86
87 tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFB1(port));
88 tmp &= ~(3 << (pin * 2));
89 tmp |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2);
90 __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFB1(port));
91 } else {
92 pin -= 16;
93
94 tmp = __raw_readl(VA_GPIO_BASE + MXC_OCR2(port));
95 tmp &= ~(3 << (pin * 2));
96 tmp |= (ocr << (pin * 2));
97 __raw_writel(tmp, VA_GPIO_BASE + MXC_OCR2(port));
98
99 tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFA2(port));
100 tmp &= ~(3 << (pin * 2));
101 tmp |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2);
102 __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFA2(port));
103
104 tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFB2(port));
105 tmp &= ~(3 << (pin * 2));
106 tmp |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2);
107 __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFB2(port));
108 }
109}
110EXPORT_SYMBOL(mxc_gpio_mode);
111
112int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
113 const char *label)
114{
115 const int *p = pin_list;
116 int i;
117 unsigned gpio;
118 unsigned mode;
119 int ret = -EINVAL;
120
121 for (i = 0; i < count; i++) {
122 gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
123 mode = *p & ~(GPIO_PIN_MASK | GPIO_PORT_MASK);
124
125 if (gpio >= (GPIO_PORT_MAX + 1) * 32)
126 goto setup_error;
127
128 ret = gpio_request(gpio, label);
129 if (ret)
130 goto setup_error;
131
132 mxc_gpio_mode(gpio | mode);
133
134 p++;
135 }
136 return 0;
137
138setup_error:
139 mxc_gpio_release_multiple_pins(pin_list, i);
140 return ret;
141}
142EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
143
144void mxc_gpio_release_multiple_pins(const int *pin_list, int count)
145{
146 const int *p = pin_list;
147 int i;
148
149 for (i = 0; i < count; i++) {
150 unsigned gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
151 gpio_free(gpio);
152 p++;
153 }
154
155}
156EXPORT_SYMBOL(mxc_gpio_release_multiple_pins);
157
diff --git a/arch/arm/plat-mxc/iomux-v1.c b/arch/arm/plat-mxc/iomux-v1.c
new file mode 100644
index 000000000000..960a02cbcbaf
--- /dev/null
+++ b/arch/arm/plat-mxc/iomux-v1.c
@@ -0,0 +1,238 @@
1/*
2 * arch/arm/plat-mxc/iomux-v1.c
3 *
4 * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
5 * Copyright (C) 2009 Uwe Kleine-Koenig, Pengutronix
6 *
7 * Common code for i.MX1, i.MX21 and i.MX27
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
22 */
23
24#include <linux/errno.h>
25#include <linux/init.h>
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/string.h>
29#include <linux/gpio.h>
30
31#include <mach/hardware.h>
32#include <asm/mach/map.h>
33#include <mach/iomux-v1.h>
34
35static void __iomem *imx_iomuxv1_baseaddr;
36static unsigned imx_iomuxv1_numports;
37
38static inline unsigned long imx_iomuxv1_readl(unsigned offset)
39{
40 return __raw_readl(imx_iomuxv1_baseaddr + offset);
41}
42
43static inline void imx_iomuxv1_writel(unsigned long val, unsigned offset)
44{
45 __raw_writel(val, imx_iomuxv1_baseaddr + offset);
46}
47
48static inline void imx_iomuxv1_rmwl(unsigned offset,
49 unsigned long mask, unsigned long value)
50{
51 unsigned long reg = imx_iomuxv1_readl(offset);
52
53 reg &= ~mask;
54 reg |= value;
55
56 imx_iomuxv1_writel(reg, offset);
57}
58
59static inline void imx_iomuxv1_set_puen(
60 unsigned int port, unsigned int pin, int on)
61{
62 unsigned long mask = 1 << pin;
63
64 imx_iomuxv1_rmwl(MXC_PUEN(port), mask, on ? mask : 0);
65}
66
67static inline void imx_iomuxv1_set_ddir(
68 unsigned int port, unsigned int pin, int out)
69{
70 unsigned long mask = 1 << pin;
71
72 imx_iomuxv1_rmwl(MXC_DDIR(port), mask, out ? mask : 0);
73}
74
75static inline void imx_iomuxv1_set_gpr(
76 unsigned int port, unsigned int pin, int af)
77{
78 unsigned long mask = 1 << pin;
79
80 imx_iomuxv1_rmwl(MXC_GPR(port), mask, af ? mask : 0);
81}
82
83static inline void imx_iomuxv1_set_gius(
84 unsigned int port, unsigned int pin, int inuse)
85{
86 unsigned long mask = 1 << pin;
87
88 imx_iomuxv1_rmwl(MXC_GIUS(port), mask, inuse ? mask : 0);
89}
90
91static inline void imx_iomuxv1_set_ocr(
92 unsigned int port, unsigned int pin, unsigned int ocr)
93{
94 unsigned long shift = (pin & 0xf) << 1;
95 unsigned long mask = 3 << shift;
96 unsigned long value = ocr << shift;
97 unsigned long offset = pin < 16 ? MXC_OCR1(port) : MXC_OCR2(port);
98
99 imx_iomuxv1_rmwl(offset, mask, value);
100}
101
102static inline void imx_iomuxv1_set_iconfa(
103 unsigned int port, unsigned int pin, unsigned int aout)
104{
105 unsigned long shift = (pin & 0xf) << 1;
106 unsigned long mask = 3 << shift;
107 unsigned long value = aout << shift;
108 unsigned long offset = pin < 16 ? MXC_ICONFA1(port) : MXC_ICONFA2(port);
109
110 imx_iomuxv1_rmwl(offset, mask, value);
111}
112
113static inline void imx_iomuxv1_set_iconfb(
114 unsigned int port, unsigned int pin, unsigned int bout)
115{
116 unsigned long shift = (pin & 0xf) << 1;
117 unsigned long mask = 3 << shift;
118 unsigned long value = bout << shift;
119 unsigned long offset = pin < 16 ? MXC_ICONFB1(port) : MXC_ICONFB2(port);
120
121 imx_iomuxv1_rmwl(offset, mask, value);
122}
123
124int mxc_gpio_mode(int gpio_mode)
125{
126 unsigned int pin = gpio_mode & GPIO_PIN_MASK;
127 unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
128 unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
129 unsigned int aout = (gpio_mode >> GPIO_AOUT_SHIFT) & 3;
130 unsigned int bout = (gpio_mode >> GPIO_BOUT_SHIFT) & 3;
131
132 if (port >= imx_iomuxv1_numports)
133 return -EINVAL;
134
135 /* Pullup enable */
136 imx_iomuxv1_set_puen(port, pin, gpio_mode & GPIO_PUEN);
137
138 /* Data direction */
139 imx_iomuxv1_set_ddir(port, pin, gpio_mode & GPIO_OUT);
140
141 /* Primary / alternate function */
142 imx_iomuxv1_set_gpr(port, pin, gpio_mode & GPIO_AF);
143
144 /* use as gpio? */
145 imx_iomuxv1_set_gius(port, pin, !(gpio_mode & (GPIO_PF | GPIO_AF)));
146
147 imx_iomuxv1_set_ocr(port, pin, ocr);
148
149 imx_iomuxv1_set_iconfa(port, pin, aout);
150
151 imx_iomuxv1_set_iconfb(port, pin, bout);
152
153 return 0;
154}
155EXPORT_SYMBOL(mxc_gpio_mode);
156
157static int imx_iomuxv1_setup_multiple(const int *list, unsigned count)
158{
159 size_t i;
160 int ret;
161
162 for (i = 0; i < count; ++i) {
163 ret = mxc_gpio_mode(list[i]);
164
165 if (ret)
166 return ret;
167 }
168
169 return ret;
170}
171
172int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
173 const char *label)
174{
175 size_t i;
176 int ret;
177
178 for (i = 0; i < count; ++i) {
179 unsigned gpio = pin_list[i] & (GPIO_PIN_MASK | GPIO_PORT_MASK);
180
181 ret = gpio_request(gpio, label);
182 if (ret)
183 goto err_gpio_request;
184 }
185
186 ret = imx_iomuxv1_setup_multiple(pin_list, count);
187 if (ret)
188 goto err_setup;
189
190 return 0;
191
192err_setup:
193 BUG_ON(i != count);
194
195err_gpio_request:
196 mxc_gpio_release_multiple_pins(pin_list, i);
197
198 return ret;
199}
200EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
201
202void mxc_gpio_release_multiple_pins(const int *pin_list, int count)
203{
204 size_t i;
205
206 for (i = 0; i < count; ++i) {
207 unsigned gpio = pin_list[i] & (GPIO_PIN_MASK | GPIO_PORT_MASK);
208
209 gpio_free(gpio);
210 }
211}
212EXPORT_SYMBOL(mxc_gpio_release_multiple_pins);
213
214static int imx_iomuxv1_init(void)
215{
216#ifdef CONFIG_ARCH_MX1
217 if (cpu_is_mx1()) {
218 imx_iomuxv1_baseaddr = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR);
219 imx_iomuxv1_numports = MX1_NUM_GPIO_PORT;
220 } else
221#endif
222#ifdef CONFIG_MACH_MX21
223 if (cpu_is_mx21()) {
224 imx_iomuxv1_baseaddr = MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR);
225 imx_iomuxv1_numports = MX21_NUM_GPIO_PORT;
226 } else
227#endif
228#ifdef CONFIG_MACH_MX27
229 if (cpu_is_mx27()) {
230 imx_iomuxv1_baseaddr = MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR);
231 imx_iomuxv1_numports = MX27_NUM_GPIO_PORT;
232 } else
233#endif
234 return -ENODEV;
235
236 return 0;
237}
238pure_initcall(imx_iomuxv1_init);
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 844567ee35fe..c1ce51abdba6 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -30,9 +30,15 @@
30#include <asm/mach/time.h> 30#include <asm/mach/time.h>
31#include <mach/common.h> 31#include <mach/common.h>
32 32
33/*
34 * There are 2 versions of the timer hardware on Freescale MXC hardware.
35 * Version 1: MX1/MXL, MX21, MX27.
36 * Version 2: MX25, MX31, MX35, MX37, MX51
37 */
38
33/* defines common for all i.MX */ 39/* defines common for all i.MX */
34#define MXC_TCTL 0x00 40#define MXC_TCTL 0x00
35#define MXC_TCTL_TEN (1 << 0) 41#define MXC_TCTL_TEN (1 << 0) /* Enable module */
36#define MXC_TPRER 0x04 42#define MXC_TPRER 0x04
37 43
38/* MX1, MX21, MX27 */ 44/* MX1, MX21, MX27 */
@@ -47,8 +53,8 @@
47#define MX2_TSTAT_CAPT (1 << 1) 53#define MX2_TSTAT_CAPT (1 << 1)
48#define MX2_TSTAT_COMP (1 << 0) 54#define MX2_TSTAT_COMP (1 << 0)
49 55
50/* MX31, MX35, MX25, MXC91231 */ 56/* MX31, MX35, MX25, MXC91231, MX5 */
51#define MX3_TCTL_WAITEN (1 << 3) 57#define MX3_TCTL_WAITEN (1 << 3) /* Wait enable mode */
52#define MX3_TCTL_CLK_IPG (1 << 6) 58#define MX3_TCTL_CLK_IPG (1 << 6)
53#define MX3_TCTL_FRR (1 << 9) 59#define MX3_TCTL_FRR (1 << 9)
54#define MX3_IR 0x0c 60#define MX3_IR 0x0c
@@ -57,6 +63,9 @@
57#define MX3_TCN 0x24 63#define MX3_TCN 0x24
58#define MX3_TCMP 0x10 64#define MX3_TCMP 0x10
59 65
66#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
67#define timer_is_v2() (!timer_is_v1())
68
60static struct clock_event_device clockevent_mxc; 69static struct clock_event_device clockevent_mxc;
61static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; 70static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
62 71
@@ -66,7 +75,7 @@ static inline void gpt_irq_disable(void)
66{ 75{
67 unsigned int tmp; 76 unsigned int tmp;
68 77
69 if (cpu_is_mx3() || cpu_is_mx25()) 78 if (timer_is_v2())
70 __raw_writel(0, timer_base + MX3_IR); 79 __raw_writel(0, timer_base + MX3_IR);
71 else { 80 else {
72 tmp = __raw_readl(timer_base + MXC_TCTL); 81 tmp = __raw_readl(timer_base + MXC_TCTL);
@@ -76,7 +85,7 @@ static inline void gpt_irq_disable(void)
76 85
77static inline void gpt_irq_enable(void) 86static inline void gpt_irq_enable(void)
78{ 87{
79 if (cpu_is_mx3() || cpu_is_mx25()) 88 if (timer_is_v2())
80 __raw_writel(1<<0, timer_base + MX3_IR); 89 __raw_writel(1<<0, timer_base + MX3_IR);
81 else { 90 else {
82 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, 91 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
@@ -86,11 +95,13 @@ static inline void gpt_irq_enable(void)
86 95
87static void gpt_irq_acknowledge(void) 96static void gpt_irq_acknowledge(void)
88{ 97{
89 if (cpu_is_mx1()) 98 if (timer_is_v1()) {
90 __raw_writel(0, timer_base + MX1_2_TSTAT); 99 if (cpu_is_mx1())
91 if (cpu_is_mx2()) 100 __raw_writel(0, timer_base + MX1_2_TSTAT);
92 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT); 101 else
93 if (cpu_is_mx3() || cpu_is_mx25()) 102 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
103 timer_base + MX1_2_TSTAT);
104 } else if (timer_is_v2())
94 __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT); 105 __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT);
95} 106}
96 107
@@ -117,7 +128,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
117{ 128{
118 unsigned int c = clk_get_rate(timer_clk); 129 unsigned int c = clk_get_rate(timer_clk);
119 130
120 if (cpu_is_mx3() || cpu_is_mx25()) 131 if (timer_is_v2())
121 clocksource_mxc.read = mx3_get_cycles; 132 clocksource_mxc.read = mx3_get_cycles;
122 133
123 clocksource_mxc.mult = clocksource_hz2mult(c, 134 clocksource_mxc.mult = clocksource_hz2mult(c,
@@ -180,7 +191,7 @@ static void mxc_set_mode(enum clock_event_mode mode,
180 191
181 if (mode != clockevent_mode) { 192 if (mode != clockevent_mode) {
182 /* Set event time into far-far future */ 193 /* Set event time into far-far future */
183 if (cpu_is_mx3() || cpu_is_mx25()) 194 if (timer_is_v2())
184 __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3, 195 __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3,
185 timer_base + MX3_TCMP); 196 timer_base + MX3_TCMP);
186 else 197 else
@@ -233,7 +244,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
233 struct clock_event_device *evt = &clockevent_mxc; 244 struct clock_event_device *evt = &clockevent_mxc;
234 uint32_t tstat; 245 uint32_t tstat;
235 246
236 if (cpu_is_mx3() || cpu_is_mx25()) 247 if (timer_is_v2())
237 tstat = __raw_readl(timer_base + MX3_TSTAT); 248 tstat = __raw_readl(timer_base + MX3_TSTAT);
238 else 249 else
239 tstat = __raw_readl(timer_base + MX1_2_TSTAT); 250 tstat = __raw_readl(timer_base + MX1_2_TSTAT);
@@ -264,7 +275,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
264{ 275{
265 unsigned int c = clk_get_rate(timer_clk); 276 unsigned int c = clk_get_rate(timer_clk);
266 277
267 if (cpu_is_mx3() || cpu_is_mx25()) 278 if (timer_is_v2())
268 clockevent_mxc.set_next_event = mx3_set_next_event; 279 clockevent_mxc.set_next_event = mx3_set_next_event;
269 280
270 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, 281 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
@@ -296,7 +307,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
296 __raw_writel(0, timer_base + MXC_TCTL); 307 __raw_writel(0, timer_base + MXC_TCTL);
297 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ 308 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
298 309
299 if (cpu_is_mx3() || cpu_is_mx25()) 310 if (timer_is_v2())
300 tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; 311 tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN;
301 else 312 else
302 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; 313 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
new file mode 100644
index 000000000000..afa6709db0b3
--- /dev/null
+++ b/arch/arm/plat-mxc/tzic.c
@@ -0,0 +1,172 @@
1/*
2 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/device.h>
16#include <linux/errno.h>
17#include <linux/io.h>
18
19#include <asm/mach/irq.h>
20
21#include <mach/hardware.h>
22
23/*
24 *****************************************
25 * TZIC Registers *
26 *****************************************
27 */
28
29#define TZIC_INTCNTL 0x0000 /* Control register */
30#define TZIC_INTTYPE 0x0004 /* Controller Type register */
31#define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */
32#define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */
33#define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */
34#define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */
35#define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
36#define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
37#define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
38#define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */
39#define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */
40#define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */
41#define TZIC_PND0 0x0D00 /* Pending Register 0 */
42#define TZIC_HIPND0 0x0D80 /* High Priority Pending Register */
43#define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */
44#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
45#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
46
47void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
48
49/**
50 * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC
51 *
52 * @param irq interrupt source number
53 */
54static void tzic_mask_irq(unsigned int irq)
55{
56 int index, off;
57
58 index = irq >> 5;
59 off = irq & 0x1F;
60 __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index));
61}
62
63/**
64 * tzic_unmask_irq() - Enable interrupt number "irq" in the TZIC
65 *
66 * @param irq interrupt source number
67 */
68static void tzic_unmask_irq(unsigned int irq)
69{
70 int index, off;
71
72 index = irq >> 5;
73 off = irq & 0x1F;
74 __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index));
75}
76
77static unsigned int wakeup_intr[4];
78
79/**
80 * tzic_set_wake_irq() - Set interrupt number "irq" in the TZIC as a wake-up source.
81 *
82 * @param irq interrupt source number
83 * @param enable enable as wake-up if equal to non-zero
84 * disble as wake-up if equal to zero
85 *
86 * @return This function returns 0 on success.
87 */
88static int tzic_set_wake_irq(unsigned int irq, unsigned int enable)
89{
90 unsigned int index, off;
91
92 index = irq >> 5;
93 off = irq & 0x1F;
94
95 if (index > 3)
96 return -EINVAL;
97
98 if (enable)
99 wakeup_intr[index] |= (1 << off);
100 else
101 wakeup_intr[index] &= ~(1 << off);
102
103 return 0;
104}
105
106static struct irq_chip mxc_tzic_chip = {
107 .name = "MXC_TZIC",
108 .ack = tzic_mask_irq,
109 .mask = tzic_mask_irq,
110 .unmask = tzic_unmask_irq,
111 .set_wake = tzic_set_wake_irq,
112};
113
114/*
115 * This function initializes the TZIC hardware and disables all the
116 * interrupts. It registers the interrupt enable and disable functions
117 * to the kernel for each interrupt source.
118 */
119void __init tzic_init_irq(void __iomem *irqbase)
120{
121 int i;
122
123 tzic_base = irqbase;
124 /* put the TZIC into the reset value with
125 * all interrupts disabled
126 */
127 i = __raw_readl(tzic_base + TZIC_INTCNTL);
128
129 __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);
130 __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);
131 __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);
132
133 for (i = 0; i < 4; i++)
134 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
135
136 /* disable all interrupts */
137 for (i = 0; i < 4; i++)
138 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
139
140 /* all IRQ no FIQ Warning :: No selection */
141
142 for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
143 set_irq_chip(i, &mxc_tzic_chip);
144 set_irq_handler(i, handle_level_irq);
145 set_irq_flags(i, IRQF_VALID);
146 }
147
148 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
149}
150
151/**
152 * tzic_enable_wake() - enable wakeup interrupt
153 *
154 * @param is_idle 1 if called in idle loop (ENSET0 register);
155 * 0 to be used when called from low power entry
156 * @return 0 if successful; non-zero otherwise
157 */
158int tzic_enable_wake(int is_idle)
159{
160 unsigned int i, v;
161
162 __raw_writel(1, tzic_base + TZIC_DSMINT);
163 if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
164 return -EAGAIN;
165
166 for (i = 0; i < 4; i++) {
167 v = is_idle ? __raw_readl(TZIC_ENSET0(i)) : wakeup_intr[i];
168 __raw_writel(v, TZIC_WAKEUP0(i));
169 }
170
171 return 0;
172}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 18:10:00 -0500