18 files changed, 112 insertions, 43 deletions

diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
index c856fa397606..f0ba0726306c 100644
--- a/arch/arm/plat-mxc/3ds_debugboard.c
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -100,14 +100,9 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
 
         expio_irq = MXC_BOARD_IRQ_START;
         for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
-                struct irq_desc *d;
                 if ((int_valid & 1) == 0)
                         continue;
-                d = irq_desc + expio_irq;
-                if (unlikely(!(d->handle_irq)))
-                        pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
-                else
-                        d->handle_irq(expio_irq, d);
+                generic_handle_irq(expio_irq);
         }
 
         desc->irq_data.chip->irq_ack(&desc->irq_data);
@@ -186,12 +181,11 @@ int __init mxc_expio_init(u32 base, u32 p_irq)
         __raw_writew(0x1F, brd_io + INTR_MASK_REG);
         for (i = MXC_EXP_IO_BASE;
              i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
-                set_irq_chip(i, &expio_irq_chip);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
-        set_irq_type(p_irq, IRQF_TRIGGER_LOW);
-        set_irq_chained_handler(p_irq, mxc_expio_irq_handler);
+        irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW);
+        irq_set_chained_handler(p_irq, mxc_expio_irq_handler);
 
         /* Register Lan device on the debugboard */
         smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index deb284bc7c4b..09e2bd0fcdca 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -139,8 +139,8 @@ void __init mxc_init_irq(void __iomem *irqbase)
         __raw_writel(0, avic_base + AVIC_INTTYPEH);
         __raw_writel(0, avic_base + AVIC_INTTYPEL);
         for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
-                set_irq_chip(i, &mxc_avic_chip.base);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip_and_handler(i, &mxc_avic_chip.base,
+                                         handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
 
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index ce81481becf1..4268a2bdf145 100644
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -13,7 +13,7 @@
 
 /*
  * A driver for the Freescale Semiconductor i.MXC CPUfreq module.
- * The CPUFREQ driver is for controling CPU frequency. It allows you to change
+ * The CPUFREQ driver is for controlling CPU frequency. It allows you to change
  * the CPU clock speed on the fly.
  */
 
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c
index 6561c9df5f0d..ccc789e21daa 100644
--- a/arch/arm/plat-mxc/devices/platform-fec.c
+++ b/arch/arm/plat-mxc/devices/platform-fec.c
@@ -53,7 +53,7 @@ struct platform_device *__init imx_add_fec(
         struct resource res[] = {
                 {
                         .start = data->iobase,
-                        .end = data->iobase + SZ_4K,
+                        .end = data->iobase + SZ_4K - 1,
                         .flags = IORESOURCE_MEM,
                 }, {
                         .start = data->irq,
diff --git a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c
index 10653cc8d1fa..805336fdc252 100644
--- a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c
+++ b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c
@@ -27,7 +27,7 @@ struct platform_device *__init imx_add_imxdi_rtc(
         struct resource res[] = {
                 {
                         .start = data->iobase,
-                        .end = data->iobase + SZ_16K,
+                        .end = data->iobase + SZ_16K - 1,
                         .flags = IORESOURCE_MEM,
                 }, {
                         .start = data->irq,
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 57d59855f9ec..7a107246fd98 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -175,7 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
         u32 irq_stat;
-        struct mxc_gpio_port *port = get_irq_data(irq);
+        struct mxc_gpio_port *port = irq_get_handler_data(irq);
 
         irq_stat = __raw_readl(port->base + GPIO_ISR) &
                         __raw_readl(port->base + GPIO_IMR);
@@ -188,7 +188,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
         int i;
         u32 irq_msk, irq_stat;
-        struct mxc_gpio_port *port = get_irq_data(irq);
+        struct mxc_gpio_port *port = irq_get_handler_data(irq);
 
         /* walk through all interrupt status registers */
         for (i = 0; i < gpio_table_size; i++) {
@@ -311,8 +311,8 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
                 __raw_writel(~0, port[i].base + GPIO_ISR);
                 for (j = port[i].virtual_irq_start;
                         j < port[i].virtual_irq_start + 32; j++) {
-                        set_irq_chip(j, &gpio_irq_chip);
-                        set_irq_handler(j, handle_level_irq);
+                        irq_set_chip_and_handler(j, &gpio_irq_chip,
+                                                 handle_level_irq);
                         set_irq_flags(j, IRQF_VALID);
                 }
 
@@ -331,21 +331,23 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
 
                 if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) {
                         /* setup one handler for each entry */
-                        set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
-                        set_irq_data(port[i].irq, &port[i]);
+                        irq_set_chained_handler(port[i].irq,
+                                                mx3_gpio_irq_handler);
+                        irq_set_handler_data(port[i].irq, &port[i]);
                         if (port[i].irq_high) {
                                 /* setup handler for GPIO 16 to 31 */
-                                set_irq_chained_handler(port[i].irq_high,
-                                                mx3_gpio_irq_handler);
-                                set_irq_data(port[i].irq_high, &port[i]);
+                                irq_set_chained_handler(port[i].irq_high,
+                                                        mx3_gpio_irq_handler);
+                                irq_set_handler_data(port[i].irq_high,
+                                                     &port[i]);
                         }
                 }
         }
 
         if (cpu_is_mx2()) {
                 /* setup one handler for all GPIO interrupts */
-                set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
-                set_irq_data(port[0].irq, port);
+                irq_set_chained_handler(port[0].irq, mx2_gpio_irq_handler);
+                irq_set_handler_data(port[0].irq, port);
         }
 
         return 0;
diff --git a/arch/arm/plat-mxc/include/mach/audmux.h b/arch/arm/plat-mxc/include/mach/audmux.h
index 5cd6466964af..6fda788ed0e9 100644
--- a/arch/arm/plat-mxc/include/mach/audmux.h
+++ b/arch/arm/plat-mxc/include/mach/audmux.h
@@ -15,6 +15,14 @@
 #define MX31_AUDMUX_PORT5_SSI_PINS_5    4
 #define MX31_AUDMUX_PORT6_SSI_PINS_6    5
 
+#define MX51_AUDMUX_PORT1_SSI0          0
+#define MX51_AUDMUX_PORT2_SSI1          1
+#define MX51_AUDMUX_PORT3               2
+#define MX51_AUDMUX_PORT4               3
+#define MX51_AUDMUX_PORT5               4
+#define MX51_AUDMUX_PORT6               5
+#define MX51_AUDMUX_PORT7               6
+
 /* Register definitions for the i.MX21/27 Digital Audio Multiplexer */
 #define MXC_AUDMUX_V1_PCR_INMMASK(x)    ((x) & 0xff)
 #define MXC_AUDMUX_V1_PCR_INMEN         (1 << 8)
@@ -28,7 +36,7 @@
 #define MXC_AUDMUX_V1_PCR_TCLKDIR       (1 << 30)
 #define MXC_AUDMUX_V1_PCR_TFSDIR        (1 << 31)
 
-/* Register definitions for the i.MX25/31/35 Digital Audio Multiplexer */
+/* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */
 #define MXC_AUDMUX_V2_PTCR_TFSDIR       (1 << 31)
 #define MXC_AUDMUX_V2_PTCR_TFSEL(x)     (((x) & 0xf) << 27)
 #define MXC_AUDMUX_V2_PTCR_TCLKDIR      (1 << 26)
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index bd9bb9799141..2e49e71b1b98 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -33,9 +33,9 @@
         .macro  arch_ret_to_user, tmp1, tmp2
         .endm
 
-        @ this macro checks which interrupt occured
+        @ this macro checks which interrupt occurred
         @ and returns its number in irqnr
-        @ and returns if an interrupt occured in irqstat
+        @ and returns if an interrupt occurred in irqstat
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 #ifndef CONFIG_MXC_TZIC
         @ Load offset & priority of the highest priority
diff --git a/arch/arm/plat-mxc/include/mach/esdhc.h b/arch/arm/plat-mxc/include/mach/esdhc.h
index a48a9aaa56b1..86003f411755 100644
--- a/arch/arm/plat-mxc/include/mach/esdhc.h
+++ b/arch/arm/plat-mxc/include/mach/esdhc.h
@@ -10,7 +10,17 @@
 #ifndef __ASM_ARCH_IMX_ESDHC_H
 #define __ASM_ARCH_IMX_ESDHC_H
 
+/**
+ * struct esdhc_platform_data - optional platform data for esdhc on i.MX
+ *
+ * strongly recommended for i.MX25/35, not needed for other variants
+ *
+ * @wp_gpio:    gpio for write_protect (-EINVAL if unused)
+ * @cd_gpio:    gpio for card_detect interrupt (-EINVAL if unused)
+ */
+
 struct esdhc_platform_data {
-        unsigned int wp_gpio;   /* write protect pin */
+        unsigned int wp_gpio;
+        unsigned int cd_gpio;
 };
 #endif /* __ASM_ARCH_IMX_ESDHC_H */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
index c4f116d214f2..7a9b20abda09 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
@@ -90,12 +90,12 @@
 #define PC31_PF_SSI3_CLK        (GPIO_PORTC | GPIO_PF | GPIO_IN | 31)
 #define PD17_PF_I2C_DATA        (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
 #define PD18_PF_I2C_CLK         (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
-#define PD19_PF_CSPI2_SS2       (GPIO_PORTD | GPIO_PF | 19)
-#define PD20_PF_CSPI2_SS1       (GPIO_PORTD | GPIO_PF | 20)
-#define PD21_PF_CSPI2_SS0       (GPIO_PORTD | GPIO_PF | 21)
-#define PD22_PF_CSPI2_SCLK      (GPIO_PORTD | GPIO_PF | 22)
-#define PD23_PF_CSPI2_MISO      (GPIO_PORTD | GPIO_PF | 23)
-#define PD24_PF_CSPI2_MOSI      (GPIO_PORTD | GPIO_PF | 24)
+#define PD19_PF_CSPI2_SS2       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19)
+#define PD20_PF_CSPI2_SS1       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20)
+#define PD21_PF_CSPI2_SS0       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21)
+#define PD22_PF_CSPI2_SCLK      (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22)
+#define PD23_PF_CSPI2_MISO      (GPIO_PORTD | GPIO_PF | GPIO_IN | 23)
+#define PD24_PF_CSPI2_MOSI      (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24)
 #define PD25_PF_CSPI1_RDY       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
 #define PD26_PF_CSPI1_SS2       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
 #define PD27_PF_CSPI1_SS1       (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h
index aaec2a6e7b3a..5f2da75a47f4 100644
--- a/arch/arm/plat-mxc/include/mach/mx50.h
+++ b/arch/arm/plat-mxc/include/mach/mx50.h
@@ -282,4 +282,8 @@
 #define MX50_INT_APBHDMA_CHAN6  116
 #define MX50_INT_APBHDMA_CHAN7  117
 
+#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
+extern int mx50_revision(void);
+#endif
+
 #endif /* ifndef __MACH_MX50_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 1eb339e6c857..dede19a766ff 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -347,6 +347,7 @@
 
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 extern int mx51_revision(void);
+extern void mx51_display_revision(void);
 #endif
 
 /* tape-out 1 defines */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 7e072637eefa..1aea818d9d31 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -51,6 +51,20 @@
 #define IMX_CHIP_REVISION_3_3           0x33
 #define IMX_CHIP_REVISION_UNKNOWN       0xff
 
+#define IMX_CHIP_REVISION_1_0_STRING            "1.0"
+#define IMX_CHIP_REVISION_1_1_STRING            "1.1"
+#define IMX_CHIP_REVISION_1_2_STRING            "1.2"
+#define IMX_CHIP_REVISION_1_3_STRING            "1.3"
+#define IMX_CHIP_REVISION_2_0_STRING            "2.0"
+#define IMX_CHIP_REVISION_2_1_STRING            "2.1"
+#define IMX_CHIP_REVISION_2_2_STRING            "2.2"
+#define IMX_CHIP_REVISION_2_3_STRING            "2.3"
+#define IMX_CHIP_REVISION_3_0_STRING            "3.0"
+#define IMX_CHIP_REVISION_3_1_STRING            "3.1"
+#define IMX_CHIP_REVISION_3_2_STRING            "3.2"
+#define IMX_CHIP_REVISION_3_3_STRING            "3.3"
+#define IMX_CHIP_REVISION_UNKNOWN_STRING        "unknown"
+
 #ifndef __ASSEMBLY__
 extern unsigned int __mxc_cpu_type;
 #endif
@@ -181,6 +195,15 @@ struct cpu_op {
         u32 cpu_rate;
 };
 
+int tzic_enable_wake(int is_idle);
+enum mxc_cpu_pwr_mode {
+        WAIT_CLOCKED,           /* wfi only */
+        WAIT_UNCLOCKED,         /* WAIT */
+        WAIT_UNCLOCKED_POWER_OFF,       /* WAIT + SRPG */
+        STOP_POWER_ON,          /* just STOP */
+        STOP_POWER_OFF,         /* STOP + SRPG */
+};
+
 extern struct cpu_op *(*get_cpu_op)(int *op);
 #endif
 
diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h
index 04c0d060d814..6bb96ef1600b 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_nand.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h
@@ -24,7 +24,7 @@
 
 struct mxc_nand_platform_data {
         unsigned int width;     /* data bus width in bytes */
-        unsigned int hw_ecc:1;  /* 0 if supress hardware ECC */
+        unsigned int hw_ecc:1;  /* 0 if suppress hardware ECC */
         unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
         struct mtd_partition *parts;    /* partition table */
         int nr_parts;                   /* size of parts */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index 95be51bfe9a9..0417da9f710d 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -20,6 +20,8 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 
+extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
+
 static inline void arch_idle(void)
 {
 #ifdef CONFIG_ARCH_MXC91231
@@ -54,7 +56,9 @@ static inline void arch_idle(void)
                         "orr %0, %0, #0x00000004\n"
                         "mcr p15, 0, %0, c1, c0, 0\n"
                         : "=r" (reg));
-        } else
+        } else if (cpu_is_mx51())
+                mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+        else
                 cpu_do_idle();
 }
 
diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c
index 0c799ac27730..e1c6eff7258a 100644
--- a/arch/arm/plat-mxc/irq-common.c
+++ b/arch/arm/plat-mxc/irq-common.c
@@ -29,7 +29,7 @@ int imx_irq_set_priority(unsigned char irq, unsigned char prio)
 
         ret = -ENOSYS;
 
-        base = get_irq_chip(irq);
+        base = irq_get_chip(irq);
         if (base) {
                 chip = container_of(base, struct mxc_irq_chip, base);
                 if (chip->set_priority)
@@ -48,7 +48,7 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
 
         ret = -ENOSYS;
 
-        base = get_irq_chip(irq);
+        base = irq_get_chip(irq);
         if (base) {
                 chip = container_of(base, struct mxc_irq_chip, base);
                 if (chip->set_irq_fiq)
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 9f0c2610595e..2237ff8b434f 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -27,6 +27,7 @@
 #include <linux/clk.h>
 
 #include <mach/hardware.h>
+#include <asm/sched_clock.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
 
@@ -105,6 +106,11 @@ static void gpt_irq_acknowledge(void)
                 __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
 }
 
+static cycle_t dummy_get_cycles(struct clocksource *cs)
+{
+        return 0;
+}
+
 static cycle_t mx1_2_get_cycles(struct clocksource *cs)
 {
         return __raw_readl(timer_base + MX1_2_TCN);
@@ -118,18 +124,35 @@ static cycle_t v2_get_cycles(struct clocksource *cs)
 static struct clocksource clocksource_mxc = {
         .name           = "mxc_timer1",
         .rating         = 200,
-        .read           = mx1_2_get_cycles,
+        .read           = dummy_get_cycles,
         .mask           = CLOCKSOURCE_MASK(32),
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+static DEFINE_CLOCK_DATA(cd);
+unsigned long long notrace sched_clock(void)
+{
+        cycle_t cyc = clocksource_mxc.read(&clocksource_mxc);
+
+        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+}
+
+static void notrace mxc_update_sched_clock(void)
+{
+        cycle_t cyc = clocksource_mxc.read(&clocksource_mxc);
+        update_sched_clock(&cd, cyc, (u32)~0);
+}
+
 static int __init mxc_clocksource_init(struct clk *timer_clk)
 {
         unsigned int c = clk_get_rate(timer_clk);
 
         if (timer_is_v2())
                 clocksource_mxc.read = v2_get_cycles;
+        else
+                clocksource_mxc.read = mx1_2_get_cycles;
 
+        init_sched_clock(&cd, mxc_update_sched_clock, 32, c);
         clocksource_register_hz(&clocksource_mxc, c);
 
         return 0;
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index bc3a6be8a27f..57f9395f87ce 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -167,8 +167,8 @@ void __init tzic_init_irq(void __iomem *irqbase)
         /* all IRQ no FIQ Warning :: No selection */
 
         for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
-                set_irq_chip(i, &mxc_tzic_chip.base);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip_and_handler(i, &mxc_tzic_chip.base,
+                                         handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }