32 files changed, 2945 insertions, 8 deletions

diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 1aa86fd60d71..2f8627218839 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -39,7 +39,7 @@
 #include <linux/string.h>
 #include <linux/version.h>
 
-#include <asm/arch/clock.h>
+#include <mach/clock.h>
 
 static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 73d304633642..733e0acac916 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -23,7 +23,7 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm-generic/bug.h>
 
 static struct mxc_gpio_port *mxc_gpio_ports;
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
new file mode 100644
index 000000000000..61e66dac90ef
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
@@ -0,0 +1,354 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
+#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
+
+/* external interrupt multiplexer */
+#define MXC_EXP_IO_BASE         (MXC_GPIO_BASE + MXC_MAX_GPIO_LINES)
+
+#define MXC_VIRTUAL_INTS_BASE   (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
+#define MXC_SDIO1_CARD_IRQ      MXC_VIRTUAL_INTS_BASE
+#define MXC_SDIO2_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 1)
+#define MXC_SDIO3_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 2)
+
+#define MXC_MAX_BOARD_INTS      (MXC_MAX_EXP_IO_LINES + \
+                                MXC_MAX_VIRTUAL_INTS)
+
+/*
+ * MXC UART EVB board level configurations
+ */
+
+#define MXC_LL_EXTUART_PADDR    (CS4_BASE_ADDR + 0x20000)
+#define MXC_LL_EXTUART_VADDR    (CS4_BASE_ADDR_VIRT + 0x20000)
+#define MXC_LL_EXTUART_16BIT_BUS
+
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPI_IO_ADDRESS(UART1_BASE_ADDR)
+
+/*
+ * @name Memory Size parameters
+ */
+
+/*
+ * Size of SDRAM memory
+ */
+#define SDRAM_MEM_SIZE          SZ_128M
+
+/*
+ * PBC Controller parameters
+ */
+
+/*
+ * Base address of PBC controller, CS4
+ */
+#define PBC_BASE_ADDRESS        0xEB000000
+#define PBC_REG_ADDR(offset)    (PBC_BASE_ADDRESS + (offset))
+
+/*
+ * PBC Interupt name definitions
+ */
+#define PBC_GPIO1_0  0
+#define PBC_GPIO1_1  1
+#define PBC_GPIO1_2  2
+#define PBC_GPIO1_3  3
+#define PBC_GPIO1_4  4
+#define PBC_GPIO1_5  5
+
+#define PBC_INTR_MAX_NUM 6
+#define PBC_INTR_SHARED_MAX_NUM 8
+
+/* When the PBC address connection is fixed in h/w, defined as 1 */
+#define PBC_ADDR_SH             0
+
+/* Offsets for the PBC Controller register */
+/*
+ * PBC Board version register offset
+ */
+#define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 1 set address.
+ */
+#define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 1 clear address.
+ */
+#define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 2 set address.
+ */
+#define PBC_BCTRL2_SET_REG      PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 2 clear address.
+ */
+#define PBC_BCTRL2_CLEAR_REG    PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 3 set address.
+ */
+#define PBC_BCTRL3_SET_REG      PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 3 clear address.
+ */
+#define PBC_BCTRL3_CLEAR_REG    PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 3 set address.
+ */
+#define PBC_BCTRL4_SET_REG      PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 4 clear address.
+ */
+#define PBC_BCTRL4_CLEAR_REG    PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
+/*PBC_ADDR_SH
+ * PBC Board status register 1.
+ */
+#define PBC_BSTAT1_REG          PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
+/*
+ * PBC Board interrupt status register.
+ */
+#define PBC_INTSTATUS_REG       PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
+/*
+ * PBC Board interrupt current status register.
+ */
+#define PBC_INTCURR_STATUS_REG  PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
+/*
+ * PBC Interrupt mask register set address.
+ */
+#define PBC_INTMASK_SET_REG     PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
+/*
+ * PBC Interrupt mask register clear address.
+ */
+#define PBC_INTMASK_CLEAR_REG   PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
+/*
+ * External UART A.
+ */
+#define PBC_SC16C652_UARTA_REG  PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
+/*
+ * UART 4 Expanding Signal Status.
+ */
+#define PBC_UART_STATUS_REG     PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
+/*
+ * UART 4 Expanding Signal Control Set.
+ */
+#define PBC_UCTRL_SET_REG       PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
+/*
+ * UART 4 Expanding Signal Control Clear.
+ */
+#define PBC_UCTRL_CLR_REG       PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
+/*
+ * Ethernet Controller IO base address.
+ */
+#define PBC_CS8900A_IOBASE_REG  PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
+/*
+ * Ethernet Controller Memory base address.
+ */
+#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
+/*
+ * Ethernet Controller DMA base address.
+ */
+#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
+
+/* PBC Board Version Register bit definition */
+#define PBC_VERSION_ADS         0x8000  /* Bit15=1 means version for ads */
+#define PBC_VERSION_EVB_REVB    0x4000  /* BIT14=1 means version for evb revb */
+
+/* PBC Board Control Register 1 bit definitions */
+#define PBC_BCTRL1_ERST         0x0001  /* Ethernet Reset */
+#define PBC_BCTRL1_URST         0x0002  /* Reset External UART controller */
+#define PBC_BCTRL1_FRST         0x0004  /* FEC Reset */
+#define PBC_BCTRL1_ESLEEP       0x0010  /* Enable ethernet Sleep */
+#define PBC_BCTRL1_LCDON        0x0800  /* Enable the LCD */
+
+/* PBC Board Control Register 2 bit definitions */
+#define PBC_BCTRL2_VCC_EN       0x0004  /*   Enable VCC */
+#define PBC_BCTRL2_VPP_EN       0x0008  /*   Enable Vpp */
+#define PBC_BCTRL2_ATAFEC_EN    0X0010
+#define PBC_BCTRL2_ATAFEC_SEL   0X0020
+#define PBC_BCTRL2_ATA_EN       0X0040
+#define PBC_BCTRL2_IRDA_SD      0X0080
+#define PBC_BCTRL2_IRDA_EN      0X0100
+#define PBC_BCTRL2_CCTL10       0X0200
+#define PBC_BCTRL2_CCTL11       0X0400
+
+/* PBC Board Control Register 3 bit definitions */
+#define PBC_BCTRL3_HSH_EN       0X0020
+#define PBC_BCTRL3_FSH_MOD      0X0040
+#define PBC_BCTRL3_OTG_HS_EN    0X0080
+#define PBC_BCTRL3_OTG_VBUS_EN  0X0100
+#define PBC_BCTRL3_FSH_VBUS_EN  0X0200
+#define PBC_BCTRL3_USB_OTG_ON   0X0800
+#define PBC_BCTRL3_USB_FSH_ON   0X1000
+
+/* PBC Board Control Register 4 bit definitions */
+#define PBC_BCTRL4_REGEN_SEL    0X0001
+#define PBC_BCTRL4_USER_OFF     0X0002
+#define PBC_BCTRL4_VIB_EN       0X0004
+#define PBC_BCTRL4_PWRGT1_EN    0X0008
+#define PBC_BCTRL4_PWRGT2_EN    0X0010
+#define PBC_BCTRL4_STDBY_PRI    0X0020
+
+#ifndef __ASSEMBLY__
+/*
+ * Enumerations for SD cards and memory stick card. This corresponds to
+ * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
+ */
+enum mxc_card_no {
+        MXC_CARD_SD2 = 0,
+        MXC_CARD_SD3,
+        MXC_CARD_MS,
+        MXC_CARD_SD1,
+        MXC_CARD_MIN = MXC_CARD_SD2,
+        MXC_CARD_MAX = MXC_CARD_SD1,
+};
+#endif
+
+#define MXC_CPLD_VER_1_50       0x01
+
+/*
+ * PBC BSTAT Register bit definitions
+ */
+#define PBC_BSTAT_PRI_INT       0X0001
+#define PBC_BSTAT_USB_BYP       0X0002
+#define PBC_BSTAT_ATA_IOCS16    0X0004
+#define PBC_BSTAT_ATA_CBLID     0X0008
+#define PBC_BSTAT_ATA_DASP      0X0010
+#define PBC_BSTAT_PWR_RDY       0X0020
+#define PBC_BSTAT_SD3_WP        0X0100
+#define PBC_BSTAT_SD2_WP        0X0200
+#define PBC_BSTAT_SD1_WP        0X0400
+#define PBC_BSTAT_SD3_DET       0X0800
+#define PBC_BSTAT_SD2_DET       0X1000
+#define PBC_BSTAT_SD1_DET       0X2000
+#define PBC_BSTAT_MS_DET        0X4000
+#define PBC_BSTAT_SD3_DET_BIT   11
+#define PBC_BSTAT_SD2_DET_BIT   12
+#define PBC_BSTAT_SD1_DET_BIT   13
+#define PBC_BSTAT_MS_DET_BIT    14
+#define MXC_BSTAT_BIT(n)        ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
+                                 ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
+                                 ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
+                                 ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
+                                        0x0))))
+
+/*
+ * PBC UART Control Register bit definitions
+ */
+#define PBC_UCTRL_DCE_DCD       0X0001
+#define PBC_UCTRL_DCE_DSR       0X0002
+#define PBC_UCTRL_DCE_RI        0X0004
+#define PBC_UCTRL_DTE_DTR       0X0100
+
+/*
+ * PBC UART Status Register bit definitions
+ */
+#define PBC_USTAT_DTE_DCD       0X0001
+#define PBC_USTAT_DTE_DSR       0X0002
+#define PBC_USTAT_DTE_RI        0X0004
+#define PBC_USTAT_DCE_DTR       0X0100
+
+/*
+ * PBC Interupt mask register bit definitions
+ */
+#define PBC_INTR_SD3_R_EN_BIT   4
+#define PBC_INTR_SD2_R_EN_BIT   0
+#define PBC_INTR_SD1_R_EN_BIT   6
+#define PBC_INTR_MS_R_EN_BIT    5
+#define PBC_INTR_SD3_EN_BIT     13
+#define PBC_INTR_SD2_EN_BIT     12
+#define PBC_INTR_MS_EN_BIT      14
+#define PBC_INTR_SD1_EN_BIT     15
+
+#define PBC_INTR_SD2_R_EN       0x0001
+#define PBC_INTR_LOW_BAT        0X0002
+#define PBC_INTR_OTG_FSOVER     0X0004
+#define PBC_INTR_FSH_OVER       0X0008
+#define PBC_INTR_SD3_R_EN       0x0010
+#define PBC_INTR_MS_R_EN        0x0020
+#define PBC_INTR_SD1_R_EN       0x0040
+#define PBC_INTR_FEC_INT        0X0080
+#define PBC_INTR_ENET_INT       0X0100
+#define PBC_INTR_OTGFS_INT      0X0200
+#define PBC_INTR_XUART_INT      0X0400
+#define PBC_INTR_CCTL12         0X0800
+#define PBC_INTR_SD2_EN         0x1000
+#define PBC_INTR_SD3_EN         0x2000
+#define PBC_INTR_MS_EN          0x4000
+#define PBC_INTR_SD1_EN         0x8000
+
+
+
+/* For interrupts like xuart, enet etc */
+#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX27_PIN_TIN)
+#define MXC_MAX_EXP_IO_LINES    16
+
+/*
+ * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
+ *
+ */
+#define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 1)
+#define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
+#define EXPIO_INT_FSH_OVR       (MXC_EXP_IO_BASE + 3)
+#define EXPIO_INT_RES4          (MXC_EXP_IO_BASE + 4)
+#define EXPIO_INT_RES5          (MXC_EXP_IO_BASE + 5)
+#define EXPIO_INT_RES6          (MXC_EXP_IO_BASE + 6)
+#define EXPIO_INT_FEC           (MXC_EXP_IO_BASE + 7)
+#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
+#define EXPIO_INT_OTG_FS_INT    (MXC_EXP_IO_BASE + 9)
+#define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
+#define EXPIO_INT_CCTL12_INT    (MXC_EXP_IO_BASE + 11)
+#define EXPIO_INT_SD2_EN        (MXC_EXP_IO_BASE + 12)
+#define EXPIO_INT_SD3_EN        (MXC_EXP_IO_BASE + 13)
+#define EXPIO_INT_MS_EN         (MXC_EXP_IO_BASE + 14)
+#define EXPIO_INT_SD1_EN        (MXC_EXP_IO_BASE + 15)
+
+/*
+ * This is System IRQ used by CS8900A for interrupt generation
+ * taken from platform.h
+ */
+#define CS8900AIRQ              EXPIO_INT_ENET_INT
+/* This is I/O Base address used to access registers of CS8900A on MXC ADS */
+#define CS8900A_BASE_ADDRESS    (PBC_CS8900A_IOBASE_REG + 0x300)
+
+#define MXC_PMIC_INT_LINE       IOMUX_TO_IRQ(MX27_PIN_TOUT)
+
+/*
+* This is used to detect if the CPLD version is for mx27 evb board rev-a
+*/
+#define PBC_CPLD_VERSION_IS_REVA() \
+        ((__raw_readw(PBC_VERSION_REG) & \
+        (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
+        == 0)
+
+/* This is used to active or inactive ata signal in CPLD .
+ *  It is dependent with hardware
+ */
+#define PBC_ATA_SIGNAL_ACTIVE() \
+        __raw_writew(           \
+                PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
+                PBC_BCTRL2_CLEAR_REG)
+
+#define PBC_ATA_SIGNAL_INACTIVE() \
+        __raw_writew(  \
+                PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
+                PBC_BCTRL2_SET_REG)
+
+#define MXC_BD_LED1             (1 << 5)
+#define MXC_BD_LED2             (1 << 6)
+#define MXC_BD_LED_ON(led) \
+        __raw_writew(led, PBC_BCTRL1_SET_REG)
+#define MXC_BD_LED_OFF(led) \
+        __raw_writew(led, PBC_BCTRL1_CLEAR_REG)
+
+/* to determine the correct external crystal reference */
+#define CKIH_27MHZ_BIT_SET      (1 << 3)
+
+#endif                          /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
new file mode 100644
index 000000000000..1bc6fb0f9a83
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
+#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
+
+/* Base address of PBC controller */
+#define PBC_BASE_ADDRESS        IO_ADDRESS(CS4_BASE_ADDR)
+/* Offsets for the PBC Controller register */
+
+/* PBC Board status register offset */
+#define PBC_BSTAT               0x000002
+
+/* PBC Board control register 1 set address */
+#define PBC_BCTRL1_SET          0x000004
+
+/* PBC Board control register 1 clear address */
+#define PBC_BCTRL1_CLEAR        0x000006
+
+/* PBC Board control register 2 set address */
+#define PBC_BCTRL2_SET          0x000008
+
+/* PBC Board control register 2 clear address */
+#define PBC_BCTRL2_CLEAR        0x00000A
+
+/* PBC Board control register 3 set address */
+#define PBC_BCTRL3_SET          0x00000C
+
+/* PBC Board control register 3 clear address */
+#define PBC_BCTRL3_CLEAR        0x00000E
+
+/* PBC Board control register 4 set address */
+#define PBC_BCTRL4_SET          0x000010
+
+/* PBC Board control register 4 clear address */
+#define PBC_BCTRL4_CLEAR        0x000012
+
+/* PBC Board status register 1 */
+#define PBC_BSTAT1              0x000014
+
+/* PBC Board interrupt status register */
+#define PBC_INTSTATUS           0x000016
+
+/* PBC Board interrupt current status register */
+#define PBC_INTCURR_STATUS      0x000018
+
+/* PBC Interrupt mask register set address */
+#define PBC_INTMASK_SET         0x00001A
+
+/* PBC Interrupt mask register clear address */
+#define PBC_INTMASK_CLEAR       0x00001C
+
+/* External UART A */
+#define PBC_SC16C652_UARTA      0x010000
+
+/* External UART B */
+#define PBC_SC16C652_UARTB      0x010010
+
+/* Ethernet Controller IO base address */
+#define PBC_CS8900A_IOBASE      0x020000
+
+/* Ethernet Controller Memory base address */
+#define PBC_CS8900A_MEMBASE     0x021000
+
+/* Ethernet Controller DMA base address */
+#define PBC_CS8900A_DMABASE     0x022000
+
+/* External chip select 0 */
+#define PBC_XCS0                0x040000
+
+/* LCD Display enable */
+#define PBC_LCD_EN_B            0x060000
+
+/* Code test debug enable */
+#define PBC_CODE_B              0x070000
+
+/* PSRAM memory select */
+#define PBC_PSRAM_B             0x5000000
+
+#define PBC_INTSTATUS_REG       (PBC_INTSTATUS + PBC_BASE_ADDRESS)
+#define PBC_INTCURR_STATUS_REG  (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_SET_REG     (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
+#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
+
+#define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 0)
+#define EXPIO_INT_PB_IRQ        (MXC_EXP_IO_BASE + 1)
+#define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
+#define EXPIO_INT_FSH_OVR       (MXC_EXP_IO_BASE + 3)
+#define EXPIO_INT_RES4          (MXC_EXP_IO_BASE + 4)
+#define EXPIO_INT_RES5          (MXC_EXP_IO_BASE + 5)
+#define EXPIO_INT_RES6          (MXC_EXP_IO_BASE + 6)
+#define EXPIO_INT_RES7          (MXC_EXP_IO_BASE + 7)
+#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
+#define EXPIO_INT_OTG_FS_INT    (MXC_EXP_IO_BASE + 9)
+#define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
+#define EXPIO_INT_XUART_INTB    (MXC_EXP_IO_BASE + 11)
+#define EXPIO_INT_SYNTH_IRQ     (MXC_EXP_IO_BASE + 12)
+#define EXPIO_INT_CE_INT1       (MXC_EXP_IO_BASE + 13)
+#define EXPIO_INT_CE_INT2       (MXC_EXP_IO_BASE + 14)
+#define EXPIO_INT_RES15         (MXC_EXP_IO_BASE + 15)
+
+#define MXC_MAX_EXP_IO_LINES    16
+
+/* mandatory for CONFIG_LL_DEBUG */
+
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+
+#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
new file mode 100644
index 000000000000..e4e5cf5ad7db
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
+#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
+
+#define MXC_MAX_EXP_IO_LINES    16
+
+
+/*
+ * Memory Size parameters
+ */
+
+/*
+ * Size of SDRAM memory
+ */
+#define SDRAM_MEM_SIZE          SZ_128M
+/*
+ * Size of MBX buffer memory
+ */
+#define MXC_MBX_MEM_SIZE        SZ_16M
+/*
+ * Size of memory available to kernel
+ */
+#define MEM_SIZE                (SDRAM_MEM_SIZE - MXC_MBX_MEM_SIZE)
+
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+
+#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
+
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm037.h b/arch/arm/plat-mxc/include/mach/board-pcm037.h
new file mode 100644
index 000000000000..82232ba3c8fc
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-pcm037.h
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2008 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
+#define __ASM_ARCH_MXC_BOARD_PCM037_H__
+
+/* mandatory for CONFIG_LL_DEBUG */
+
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+
+#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h
new file mode 100644
index 000000000000..750c62afd90f
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
+#define __ASM_ARCH_MXC_BOARD_PCM038_H__
+
+/* mandatory for CONFIG_LL_DEBUG */
+
+#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR       (AIPI_BASE_ADDR_VIRT + 0x0A000)
+
+#ifndef __ASSEMBLY__
+/*
+ * This CPU module needs a baseboard to work. After basic initializing
+ * its own devices, it calls baseboard's init function.
+ * TODO: Add your own baseboard init function and call it from
+ * inside pcm038_init().
+ *
+ * This example here is for the development board. Refer pcm970-baseboard.c
+ */
+
+extern void pcm970_baseboard_init(void);
+
+#endif
+
+#endif /* __ASM_ARCH_MXC_BOARD_PCM038_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
new file mode 100644
index 000000000000..24caa2b7c91d
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/clock.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_CLOCK_H__
+#define __ASM_ARCH_MXC_CLOCK_H__
+
+#ifndef __ASSEMBLY__
+#include <linux/list.h>
+
+struct module;
+
+struct clk {
+        struct list_head node;
+        struct module *owner;
+        const char *name;
+        int id;
+        /* Source clock this clk depends on */
+        struct clk *parent;
+        /* Secondary clock to enable/disable with this clock */
+        struct clk *secondary;
+        /* Reference count of clock enable/disable */
+        __s8 usecount;
+        /* Register bit position for clock's enable/disable control. */
+        u8 enable_shift;
+        /* Register address for clock's enable/disable control. */
+        u32 enable_reg;
+        u32 flags;
+        /* get the current clock rate (always a fresh value) */
+        unsigned long (*get_rate) (struct clk *);
+        /* Function ptr to set the clock to a new rate. The rate must match a
+           supported rate returned from round_rate. Leave blank if clock is not
+           programmable */
+        int (*set_rate) (struct clk *, unsigned long);
+        /* Function ptr to round the requested clock rate to the nearest
+           supported rate that is less than or equal to the requested rate. */
+        unsigned long (*round_rate) (struct clk *, unsigned long);
+        /* Function ptr to enable the clock. Leave blank if clock can not
+           be gated. */
+        int (*enable) (struct clk *);
+        /* Function ptr to disable the clock. Leave blank if clock can not
+           be gated. */
+        void (*disable) (struct clk *);
+        /* Function ptr to set the parent clock of the clock. */
+        int (*set_parent) (struct clk *, struct clk *);
+};
+
+int clk_register(struct clk *clk);
+void clk_unregister(struct clk *clk);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
new file mode 100644
index 000000000000..a6d2e24aab15
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_COMMON_H__
+#define __ASM_ARCH_MXC_COMMON_H__
+
+extern void mxc_map_io(void);
+extern void mxc_init_irq(void);
+extern void mxc_timer_init(const char *clk_timer);
+extern int mxc_clocks_init(unsigned long fref);
+extern int mxc_register_gpios(void);
+
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
new file mode 100644
index 000000000000..b9907bebba3b
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -0,0 +1,49 @@
+/* arch/arm/mach-imx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <mach/hardware.h>
+
+#ifdef CONFIG_MACH_MX31ADS
+#include <mach/board-mx31ads.h>
+#endif
+#ifdef CONFIG_MACH_PCM037
+#include <mach/board-pcm037.h>
+#endif
+#ifdef CONFIG_MACH_MX31LITE
+#include <mach/board-mx31lite.h>
+#endif
+#ifdef CONFIG_MACH_MX27ADS
+#include <mach/board-mx27ads.h>
+#endif
+#ifdef CONFIG_MACH_PCM038
+#include <mach/board-pcm038.h>
+#endif
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                ldreq   \rx, =MXC_LL_UART_PADDR @ physical
+                ldrne   \rx, =MXC_LL_UART_VADDR @ virtual
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0x40]       @ TXDATA
+                .endm
+
+                .macro  waituart,rd,rx
+                .endm
+
+                .macro  busyuart,rd,rx
+1002:           ldr     \rd, [\rx, #0x98]       @ SR2
+                tst     \rd, #1 << 3            @ TXDC
+                beq     1002b                   @ wait until transmit done
+                .endm
diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h
new file mode 100644
index 000000000000..c822d569a05e
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/dma.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_DMA_H__
+#define __ASM_ARCH_MXC_DMA_H__
+
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
new file mode 100644
index 000000000000..b542433afb1b
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -0,0 +1,39 @@
+/*
+ *  Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+        @ this macro disables fast irq (not implemented)
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        @ this macro checks which interrupt occured
+        @ and returns its number in irqnr
+        @ and returns if an interrupt occured in irqstat
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
+        @ Load offset & priority of the highest priority
+        @ interrupt pending from AVIC_NIVECSR
+        ldr     \irqstat, [\base, #0x40]
+        @ Shift to get the decoded IRQ number, using ASR so
+        @ 'no interrupt pending' becomes 0xffffffff
+        mov     \irqnr, \irqstat, asr #16
+        @ set zero flag if IRQ + 1 == 0
+        adds    \tmp, \irqnr, #1
+        .endm
+
+        @ irq priority table (not used)
+        .macro  irq_prio_table
+        .endm
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
new file mode 100644
index 000000000000..65eedc0d196f
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_GPIO_H__
+#define __ASM_ARCH_MXC_GPIO_H__
+
+#include <mach/hardware.h>
+#include <asm-generic/gpio.h>
+
+/* use gpiolib dispatchers */
+#define gpio_get_value          __gpio_get_value
+#define gpio_set_value          __gpio_set_value
+#define gpio_cansleep           __gpio_cansleep
+
+#define gpio_to_irq(gpio)       (MXC_MAX_INT_LINES + (gpio))
+#define irq_to_gpio(irq)        ((irq) - MXC_MAX_INT_LINES)
+
+struct mxc_gpio_port {
+        void __iomem *base;
+        int irq;
+        int virtual_irq_start;
+        struct gpio_chip chip;
+};
+
+int mxc_gpio_init(struct mxc_gpio_port*, int);
+
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
new file mode 100644
index 000000000000..3caadeeda701
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#define __ASM_ARCH_MXC_HARDWARE_H__
+
+#include <asm/sizes.h>
+
+#ifdef CONFIG_ARCH_MX3
+# include <mach/mx31.h>
+#endif
+
+#ifdef CONFIG_ARCH_MX2
+# ifdef CONFIG_MACH_MX27
+#  include <mach/mx27.h>
+# endif
+#endif
+
+#include <mach/mxc.h>
+
+#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iim.h b/arch/arm/plat-mxc/include/mach/iim.h
new file mode 100644
index 000000000000..315bffadafda
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iim.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_IIM_H__
+#define __ASM_ARCH_MXC_IIM_H__
+
+/* Register offsets */
+#define MXC_IIMSTAT             0x0000
+#define MXC_IIMSTATM            0x0004
+#define MXC_IIMERR              0x0008
+#define MXC_IIMEMASK            0x000C
+#define MXC_IIMFCTL             0x0010
+#define MXC_IIMUA               0x0014
+#define MXC_IIMLA               0x0018
+#define MXC_IIMSDAT             0x001C
+#define MXC_IIMPREV             0x0020
+#define MXC_IIMSREV             0x0024
+#define MXC_IIMPRG_P            0x0028
+#define MXC_IIMSCS0             0x002C
+#define MXC_IIMSCS1             0x0030
+#define MXC_IIMSCS2             0x0034
+#define MXC_IIMSCS3             0x0038
+#define MXC_IIMFBAC0            0x0800
+#define MXC_IIMJAC              0x0804
+#define MXC_IIMHWV1             0x0808
+#define MXC_IIMHWV2             0x080C
+#define MXC_IIMHAB0             0x0810
+#define MXC_IIMHAB1             0x0814
+/* Definitions for i.MX27 TO2 */
+#define MXC_IIMMAC              0x0814
+#define MXC_IIMPREV_FUSE        0x0818
+#define MXC_IIMSREV_FUSE        0x081C
+#define MXC_IIMSJC_CHALL_0      0x0820
+#define MXC_IIMSJC_CHALL_7      0x083C
+#define MXC_IIMFB0UC17          0x0840
+#define MXC_IIMFB0UC255         0x0BFC
+#define MXC_IIMFBAC1            0x0C00
+/* Definitions for i.MX27 TO2 */
+#define MXC_IIMSUID             0x0C04
+#define MXC_IIMKEY0             0x0C04
+#define MXC_IIMKEY20            0x0C54
+#define MXC_IIMSJC_RESP_0       0x0C58
+#define MXC_IIMSJC_RESP_7       0x0C74
+#define MXC_IIMFB1UC30          0x0C78
+#define MXC_IIMFB1UC255         0x0FFC
+
+/* Bit definitions */
+
+#define MXC_IIMHWV1_WLOCK               (0x1 << 7)
+#define MXC_IIMHWV1_MCU_ENDIAN          (0x1 << 6)
+#define MXC_IIMHWV1_DSP_ENDIAN          (0x1 << 5)
+#define MXC_IIMHWV1_BOOT_INT            (0x1 << 4)
+#define MXC_IIMHWV1_SCC_DISABLE         (0x1 << 3)
+#define MXC_IIMHWV1_HANTRO_DISABLE      (0x1 << 2)
+#define MXC_IIMHWV1_MEMSTICK_DIS        (0x1 << 1)
+
+#define MXC_IIMHWV2_WLOCK               (0x1 << 7)
+#define MXC_IIMHWV2_BP_SDMA             (0x1 << 6)
+#define MXC_IIMHWV2_SCM_DCM             (0x1 << 5)
+
+#endif /* __ASM_ARCH_MXC_IIM_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/imx-uart.h b/arch/arm/plat-mxc/include/mach/imx-uart.h
new file mode 100644
index 000000000000..83fb72c4048a
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/imx-uart.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef ASMARM_ARCH_UART_H
+#define ASMARM_ARCH_UART_H
+
+#define IMXUART_HAVE_RTSCTS (1<<0)
+
+struct imxuart_platform_data {
+        int (*init)(struct platform_device *pdev);
+        int (*exit)(struct platform_device *pdev);
+        unsigned int flags;
+};
+
+int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata);
+
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h
new file mode 100644
index 000000000000..65b6810124c1
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/io.h
@@ -0,0 +1,22 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_IO_H__
+#define __ASM_ARCH_MXC_IO_H__
+
+/* Allow IO space to be anywhere in the memory */
+#define IO_SPACE_LIMIT 0xffffffff
+
+/* io address mapping macro */
+#define __io(a)                 ((void __iomem *)(a))
+
+#define __mem_pci(a)            (a)
+
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
new file mode 100644
index 000000000000..076d37b38eb2
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
@@ -0,0 +1,372 @@
+/*
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef _MXC_GPIO_MX1_MX2_H
+#define _MXC_GPIO_MX1_MX2_H
+
+#include <linux/io.h>
+
+#define MXC_GPIO_ALLOC_MODE_NORMAL      0
+#define MXC_GPIO_ALLOC_MODE_NO_ALLOC    1
+#define MXC_GPIO_ALLOC_MODE_TRY_ALLOC   2
+#define MXC_GPIO_ALLOC_MODE_ALLOC_ONLY  4
+#define MXC_GPIO_ALLOC_MODE_RELEASE     8
+
+/*
+ *  GPIO Module and I/O Multiplexer
+ *  x = 0..3 for reg_A, reg_B, reg_C, reg_D
+ */
+#define VA_GPIO_BASE    IO_ADDRESS(GPIO_BASE_ADDR)
+#define MXC_DDIR(x)    (0x00 + ((x) << 8))
+#define MXC_OCR1(x)    (0x04 + ((x) << 8))
+#define MXC_OCR2(x)    (0x08 + ((x) << 8))
+#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
+#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
+#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
+#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
+#define MXC_DR(x)      (0x1c + ((x) << 8))
+#define MXC_GIUS(x)    (0x20 + ((x) << 8))
+#define MXC_SSR(x)     (0x24 + ((x) << 8))
+#define MXC_ICR1(x)    (0x28 + ((x) << 8))
+#define MXC_ICR2(x)    (0x2c + ((x) << 8))
+#define MXC_IMR(x)     (0x30 + ((x) << 8))
+#define MXC_ISR(x)     (0x34 + ((x) << 8))
+#define MXC_GPR(x)     (0x38 + ((x) << 8))
+#define MXC_SWR(x)     (0x3c + ((x) << 8))
+#define MXC_PUEN(x)    (0x40 + ((x) << 8))
+
+#ifdef CONFIG_ARCH_MX1
+# define GPIO_PORT_MAX  3
+#endif
+#ifdef CONFIG_ARCH_MX2
+# define GPIO_PORT_MAX  5
+#endif
+
+#ifndef GPIO_PORT_MAX
+# error "GPIO config port count unknown!"
+#endif
+
+#define GPIO_PIN_MASK 0x1f
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
+
+#define GPIO_OUT   (1 << 8)
+#define GPIO_IN    (0 << 8)
+#define GPIO_PUEN  (1 << 9)
+
+#define GPIO_PF    (1 << 10)
+#define GPIO_AF    (1 << 11)
+
+#define GPIO_OCR_SHIFT 12
+#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
+#define GPIO_AIN   (0 << GPIO_OCR_SHIFT)
+#define GPIO_BIN   (1 << GPIO_OCR_SHIFT)
+#define GPIO_CIN   (2 << GPIO_OCR_SHIFT)
+#define GPIO_GPIO  (3 << GPIO_OCR_SHIFT)
+
+#define GPIO_AOUT_SHIFT 14
+#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT     (0 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_0   (2 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_1   (3 << GPIO_AOUT_SHIFT)
+
+#define GPIO_BOUT_SHIFT 16
+#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT      (0 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_ISR  (1 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_0    (2 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_1    (3 << GPIO_BOUT_SHIFT)
+
+extern void mxc_gpio_mode(int gpio_mode);
+extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
+                                        int alloc_mode, const char *label);
+
+/*-------------------------------------------------------------------------*/
+
+/* assignements for GPIO alternate/primary functions */
+
+/* FIXME: This list is not completed. The correct directions are
+ * missing on some (many) pins
+ */
+#ifdef CONFIG_ARCH_MX1
+#define PA0_AIN_SPI2_CLK     (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0)
+#define PA0_AF_ETMTRACESYNC  (GPIO_PORTA | GPIO_AF | 0)
+#define PA1_AOUT_SPI2_RXD    (GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1)
+#define PA1_PF_TIN           (GPIO_PORTA | GPIO_PF | 1)
+#define PA2_PF_PWM0          (GPIO_PORTA | GPIO_OUT | GPIO_PF | 2)
+#define PA3_PF_CSI_MCLK      (GPIO_PORTA | GPIO_PF | 3)
+#define PA4_PF_CSI_D0        (GPIO_PORTA | GPIO_PF | 4)
+#define PA5_PF_CSI_D1        (GPIO_PORTA | GPIO_PF | 5)
+#define PA6_PF_CSI_D2        (GPIO_PORTA | GPIO_PF | 6)
+#define PA7_PF_CSI_D3        (GPIO_PORTA | GPIO_PF | 7)
+#define PA8_PF_CSI_D4        (GPIO_PORTA | GPIO_PF | 8)
+#define PA9_PF_CSI_D5        (GPIO_PORTA | GPIO_PF | 9)
+#define PA10_PF_CSI_D6       (GPIO_PORTA | GPIO_PF | 10)
+#define PA11_PF_CSI_D7       (GPIO_PORTA | GPIO_PF | 11)
+#define PA12_PF_CSI_VSYNC    (GPIO_PORTA | GPIO_PF | 12)
+#define PA13_PF_CSI_HSYNC    (GPIO_PORTA | GPIO_PF | 13)
+#define PA14_PF_CSI_PIXCLK   (GPIO_PORTA | GPIO_PF | 14)
+#define PA15_PF_I2C_SDA      (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
+#define PA16_PF_I2C_SCL      (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
+#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
+#define PA17_AIN_SPI2_SS     (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17)
+#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
+#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
+#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
+#define PA21_PF_A0           (GPIO_PORTA | GPIO_PF | 21)
+#define PA22_PF_CS4          (GPIO_PORTA | GPIO_PF | 22)
+#define PA23_PF_CS5          (GPIO_PORTA | GPIO_PF | 23)
+#define PA24_PF_A16          (GPIO_PORTA | GPIO_PF | 24)
+#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
+#define PA25_PF_A17          (GPIO_PORTA | GPIO_PF | 25)
+#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
+#define PA26_PF_A18          (GPIO_PORTA | GPIO_PF | 26)
+#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
+#define PA27_PF_A19          (GPIO_PORTA | GPIO_PF | 27)
+#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
+#define PA28_PF_A20          (GPIO_PORTA | GPIO_PF | 28)
+#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
+#define PA29_PF_A21          (GPIO_PORTA | GPIO_PF | 29)
+#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
+#define PA30_PF_A22          (GPIO_PORTA | GPIO_PF | 30)
+#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
+#define PA31_PF_A23          (GPIO_PORTA | GPIO_PF | 31)
+#define PA31_AF_ETMTRACECLK  (GPIO_PORTA | GPIO_AF | 31)
+#define PB8_PF_SD_DAT0       (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
+#define PB8_AF_MS_PIO        (GPIO_PORTB | GPIO_AF | 8)
+#define PB9_PF_SD_DAT1       (GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 9)
+#define PB9_AF_MS_PI1        (GPIO_PORTB | GPIO_AF | 9)
+#define PB10_PF_SD_DAT2      (GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 10)
+#define PB10_AF_MS_SCLKI     (GPIO_PORTB | GPIO_AF | 10)
+#define PB11_PF_SD_DAT3      (GPIO_PORTB | GPIO_PF | 11)
+#define PB11_AF_MS_SDIO      (GPIO_PORTB | GPIO_AF | 11)
+#define PB12_PF_SD_CLK       (GPIO_PORTB | GPIO_PF | 12)
+#define PB12_AF_MS_SCLK0     (GPIO_PORTB | GPIO_AF | 12)
+#define PB13_PF_SD_CMD       (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
+#define PB13_AF_MS_BS        (GPIO_PORTB | GPIO_AF | 13)
+#define PB14_AF_SSI_RXFS     (GPIO_PORTB | GPIO_AF | 14)
+#define PB15_AF_SSI_RXCLK    (GPIO_PORTB | GPIO_AF | 15)
+#define PB16_AF_SSI_RXDAT    (GPIO_PORTB | GPIO_IN | GPIO_AF | 16)
+#define PB17_AF_SSI_TXDAT    (GPIO_PORTB | GPIO_OUT | GPIO_AF | 17)
+#define PB18_AF_SSI_TXFS     (GPIO_PORTB | GPIO_AF | 18)
+#define PB19_AF_SSI_TXCLK    (GPIO_PORTB | GPIO_AF | 19)
+#define PB20_PF_USBD_AFE     (GPIO_PORTB | GPIO_PF | 20)
+#define PB21_PF_USBD_OE      (GPIO_PORTB | GPIO_PF | 21)
+#define PB22_PFUSBD_RCV      (GPIO_PORTB | GPIO_PF | 22)
+#define PB23_PF_USBD_SUSPND  (GPIO_PORTB | GPIO_PF | 23)
+#define PB24_PF_USBD_VP      (GPIO_PORTB | GPIO_PF | 24)
+#define PB25_PF_USBD_VM      (GPIO_PORTB | GPIO_PF | 25)
+#define PB26_PF_USBD_VPO     (GPIO_PORTB | GPIO_PF | 26)
+#define PB27_PF_USBD_VMO     (GPIO_PORTB | GPIO_PF | 27)
+#define PB28_PF_UART2_CTS    (GPIO_PORTB | GPIO_OUT | GPIO_PF | 28)
+#define PB29_PF_UART2_RTS    (GPIO_PORTB | GPIO_IN | GPIO_PF | 29)
+#define PB30_PF_UART2_TXD    (GPIO_PORTB | GPIO_OUT | GPIO_PF | 30)
+#define PB31_PF_UART2_RXD    (GPIO_PORTB | GPIO_IN | GPIO_PF | 31)
+#define PC3_PF_SSI_RXFS      (GPIO_PORTC | GPIO_PF | 3)
+#define PC4_PF_SSI_RXCLK     (GPIO_PORTC | GPIO_PF | 4)
+#define PC5_PF_SSI_RXDAT     (GPIO_PORTC | GPIO_IN | GPIO_PF | 5)
+#define PC6_PF_SSI_TXDAT     (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
+#define PC7_PF_SSI_TXFS      (GPIO_PORTC | GPIO_PF | 7)
+#define PC8_PF_SSI_TXCLK     (GPIO_PORTC | GPIO_PF | 8)
+#define PC9_PF_UART1_CTS     (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
+#define PC10_PF_UART1_RTS    (GPIO_PORTC | GPIO_IN | GPIO_PF | 10)
+#define PC11_PF_UART1_TXD    (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
+#define PC12_PF_UART1_RXD    (GPIO_PORTC | GPIO_IN | GPIO_PF | 12)
+#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
+#define PC14_PF_SPI1_SCLK    (GPIO_PORTC | GPIO_PF | 14)
+#define PC15_PF_SPI1_SS      (GPIO_PORTC | GPIO_PF | 15)
+#define PC16_PF_SPI1_MISO    (GPIO_PORTC | GPIO_PF | 16)
+#define PC17_PF_SPI1_MOSI    (GPIO_PORTC | GPIO_PF | 17)
+#define PC24_BIN_UART3_RI    (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24)
+#define PC25_BIN_UART3_DSR   (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25)
+#define PC26_AOUT_UART3_DTR  (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26)
+#define PC27_BIN_UART3_DCD   (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27)
+#define PC28_BIN_UART3_CTS   (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28)
+#define PC29_AOUT_UART3_RTS  (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29)
+#define PC30_BIN_UART3_TX    (GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30)
+#define PC31_AOUT_UART3_RX   (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
+#define PD6_PF_LSCLK         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 6)
+#define PD7_PF_REV           (GPIO_PORTD | GPIO_PF | 7)
+#define PD7_AF_UART2_DTR     (GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7)
+#define PD7_AIN_SPI2_SCLK    (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7)
+#define PD8_PF_CLS           (GPIO_PORTD | GPIO_PF | 8)
+#define PD8_AF_UART2_DCD     (GPIO_PORTD | GPIO_OUT | GPIO_AF | 8)
+#define PD8_AIN_SPI2_SS      (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8)
+#define PD9_PF_PS            (GPIO_PORTD | GPIO_PF | 9)
+#define PD9_AF_UART2_RI      (GPIO_PORTD | GPIO_OUT | GPIO_AF | 9)
+#define PD9_AOUT_SPI2_RXD    (GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9)
+#define PD10_PF_SPL_SPR      (GPIO_PORTD | GPIO_OUT | GPIO_PF | 10)
+#define PD10_AF_UART2_DSR    (GPIO_PORTD | GPIO_OUT | GPIO_AF | 10)
+#define PD10_AIN_SPI2_TXD    (GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10)
+#define PD11_PF_CONTRAST     (GPIO_PORTD | GPIO_OUT | GPIO_PF | 11)
+#define PD12_PF_ACD_OE       (GPIO_PORTD | GPIO_OUT | GPIO_PF | 12)
+#define PD13_PF_LP_HSYNC     (GPIO_PORTD | GPIO_OUT | GPIO_PF | 13)
+#define PD14_PF_FLM_VSYNC    (GPIO_PORTD | GPIO_OUT | GPIO_PF | 14)
+#define PD15_PF_LD0          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 15)
+#define PD16_PF_LD1          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 16)
+#define PD17_PF_LD2          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
+#define PD18_PF_LD3          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
+#define PD19_PF_LD4          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 19)
+#define PD20_PF_LD5          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 20)
+#define PD21_PF_LD6          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 21)
+#define PD22_PF_LD7          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 22)
+#define PD23_PF_LD8          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 23)
+#define PD24_PF_LD9          (GPIO_PORTD | GPIO_OUT | GPIO_PF | 24)
+#define PD25_PF_LD10         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25)
+#define PD26_PF_LD11         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26)
+#define PD27_PF_LD12         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27)
+#define PD28_PF_LD13         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28)
+#define PD29_PF_LD14         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
+#define PD30_PF_LD15         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 30)
+#define PD31_PF_TMR2OUT      (GPIO_PORTD | GPIO_PF | 31)
+#define PD31_BIN_SPI2_TXD    (GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31)
+#endif
+
+#ifdef CONFIG_ARCH_MX2
+#define PA5_PF_LSCLK            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 5)
+#define PA6_PF_LD0              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 6)
+#define PA7_PF_LD1              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 7)
+#define PA8_PF_LD2              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 8)
+#define PA9_PF_LD3              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 9)
+#define PA10_PF_LD4             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 10)
+#define PA11_PF_LD5             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 11)
+#define PA12_PF_LD6             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 12)
+#define PA13_PF_LD7             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 13)
+#define PA14_PF_LD8             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 14)
+#define PA15_PF_LD9             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
+#define PA16_PF_LD10            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
+#define PA17_PF_LD11            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 17)
+#define PA18_PF_LD12            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 18)
+#define PA19_PF_LD13            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 19)
+#define PA20_PF_LD14            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 20)
+#define PA21_PF_LD15            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 21)
+#define PA22_PF_LD16            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 22)
+#define PA23_PF_LD17            (GPIO_PORTA | GPIO_OUT | GPIO_PF | 23)
+#define PA24_PF_REV             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 24)
+#define PA25_PF_CLS             (GPIO_PORTA | GPIO_OUT | GPIO_PF | 25)
+#define PA26_PF_PS              (GPIO_PORTA | GPIO_OUT | GPIO_PF | 26)
+#define PA27_PF_SPL_SPR         (GPIO_PORTA | GPIO_OUT | GPIO_PF | 27)
+#define PA28_PF_HSYNC           (GPIO_PORTA | GPIO_OUT | GPIO_PF | 28)
+#define PA29_PF_VSYNC           (GPIO_PORTA | GPIO_OUT | GPIO_PF | 29)
+#define PA30_PF_CONTRAST        (GPIO_PORTA | GPIO_OUT | GPIO_PF | 30)
+#define PA31_PF_OE_ACD          (GPIO_PORTA | GPIO_OUT | GPIO_PF | 31)
+#define PB10_PF_CSI_D0          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 10)
+#define PB10_AF_UART6_TXD       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 10)
+#define PB11_PF_CSI_D1          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 11)
+#define PB11_AF_UART6_RXD       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 11)
+#define PB12_PF_CSI_D2          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 12)
+#define PB12_AF_UART6_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 12)
+#define PB13_PF_CSI_D3          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 13)
+#define PB13_AF_UART6_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 13)
+#define PB14_PF_CSI_D4          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 14)
+#define PB15_PF_CSI_MCLK        (GPIO_PORTB | GPIO_OUT | GPIO_PF | 15)
+#define PB16_PF_CSI_PIXCLK      (GPIO_PORTB | GPIO_OUT | GPIO_PF | 16)
+#define PB17_PF_CSI_D5          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 17)
+#define PB18_PF_CSI_D6          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 18)
+#define PB18_AF_UART5_TXD       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 18)
+#define PB19_PF_CSI_D7          (GPIO_PORTB | GPIO_OUT | GPIO_PF | 19)
+#define PB19_AF_UART5_RXD       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 19)
+#define PB20_PF_CSI_VSYNC       (GPIO_PORTB | GPIO_OUT | GPIO_PF | 20)
+#define PB20_AF_UART5_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 20)
+#define PB21_PF_CSI_HSYNC       (GPIO_PORTB | GPIO_OUT | GPIO_PF | 21)
+#define PB21_AF_UART5_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 21)
+#define PB26_AF_UART4_RTS       (GPIO_PORTB | GPIO_IN  | GPIO_PF | 26)
+#define PB28_AF_UART4_TXD       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 28)
+#define PB29_AF_UART4_CTS       (GPIO_PORTB | GPIO_OUT | GPIO_AF | 29)
+#define PB31_AF_UART4_RXD       (GPIO_PORTB | GPIO_IN  | GPIO_AF | 31)
+#define PC5_PF_I2C2_SDA         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 5)
+#define PC6_PF_I2C2_SCL         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 6)
+#define PC16_PF_SSI4_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 16)
+#define PC17_PF_SSI4_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 17)
+#define PC18_PF_SSI4_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 18)
+#define PC19_PF_SSI4_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 19)
+#define PC20_PF_SSI1_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 20)
+#define PC21_PF_SSI1_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 21)
+#define PC22_PF_SSI1_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 22)
+#define PC23_PF_SSI1_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 23)
+#define PC24_PF_SSI2_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 24)
+#define PC25_PF_SSI2_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 25)
+#define PC26_PF_SSI2_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 26)
+#define PC27_PF_SSI2_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 27)
+#define PC28_PF_SSI3_FS         (GPIO_PORTC | GPIO_IN  | GPIO_PF | 28)
+#define PC29_PF_SSI3_RXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 29)
+#define PC30_PF_SSI3_TXD        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 30)
+#define PC31_PF_SSI3_CLK        (GPIO_PORTC | GPIO_IN  | GPIO_PF | 31)
+#define PD0_AIN_FEC_TXD0        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
+#define PD1_AIN_FEC_TXD1        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
+#define PD2_AIN_FEC_TXD2        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
+#define PD3_AIN_FEC_TXD3        (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
+#define PD4_AOUT_FEC_RX_ER      (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
+#define PD5_AOUT_FEC_RXD1       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
+#define PD6_AOUT_FEC_RXD2       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
+#define PD7_AOUT_FEC_RXD3       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
+#define PD8_AF_FEC_MDIO         (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
+#define PD9_AIN_FEC_MDC         (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
+#define PD10_AOUT_FEC_CRS       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
+#define PD11_AOUT_FEC_TX_CLK    (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
+#define PD12_AOUT_FEC_RXD0      (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
+#define PD13_AOUT_FEC_RX_DV     (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
+#define PD14_AOUT_FEC_CLR       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
+#define PD15_AOUT_FEC_COL       (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
+#define PD16_AIN_FEC_TX_ER      (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
+#define PD17_PF_I2C_DATA        (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
+#define PD18_PF_I2C_CLK         (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
+#define PD25_PF_CSPI1_RDY       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 25)
+#define PD26_PF_CSPI1_SS2       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 26)
+#define PD27_PF_CSPI1_SS1       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 27)
+#define PD28_PF_CSPI1_SS0       (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 28)
+#define PD29_PF_CSPI1_SCLK      (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 29)
+#define PD30_PF_CSPI1_MISO      (GPIO_PORTD | GPIO_IN | GPIO_PF  | 30)
+#define PD31_PF_CSPI1_MOSI      (GPIO_PORTD | GPIO_OUT | GPIO_PF  | 31)
+#define PF23_AIN_FEC_TX_EN      (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
+#define PE3_PF_UART2_CTS        (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
+#define PE4_PF_UART2_RTS        (GPIO_PORTE | GPIO_IN  | GPIO_PF | 4)
+#define PE6_PF_UART2_TXD        (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
+#define PE7_PF_UART2_RXD        (GPIO_PORTE | GPIO_IN  | GPIO_PF | 7)
+#define PE8_PF_UART3_TXD        (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
+#define PE9_PF_UART3_RXD        (GPIO_PORTE | GPIO_IN  | GPIO_PF | 9)
+#define PE10_PF_UART3_CTS       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
+#define PE11_PF_UART3_RTS       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 11)
+#define PE12_PF_UART1_TXD       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
+#define PE13_PF_UART1_RXD       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 13)
+#define PE14_PF_UART1_CTS       (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
+#define PE15_PF_UART1_RTS       (GPIO_PORTE | GPIO_IN  | GPIO_PF | 15)
+#define PE18_AF_CSPI3_MISO      (GPIO_PORTE | GPIO_IN  | GPIO_AF | 18)
+#define PE21_AF_CSPI3_SS        (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21)
+#define PE22_AF_CSPI3_MOSI      (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22)
+#define PE23_AF_CSPI3_SCLK      (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23)
+#endif
+
+/* decode irq number to use with IMR(x), ISR(x) and friends */
+#define IRQ_TO_REG(irq) ((irq - MXC_MAX_INT_LINES) >> 5)
+
+#define IRQ_GPIOA(x)  (MXC_MAX_INT_LINES + x)
+#define IRQ_GPIOB(x)  (IRQ_GPIOA(32) + x)
+#define IRQ_GPIOC(x)  (IRQ_GPIOB(32) + x)
+#define IRQ_GPIOD(x)  (IRQ_GPIOC(32) + x)
+
+#endif /* _MXC_GPIO_MX1_MX2_H */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
new file mode 100644
index 000000000000..7509e7692f08
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -0,0 +1,501 @@
+/*
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __MACH_MX31_IOMUX_H__
+#define __MACH_MX31_IOMUX_H__
+
+#include <linux/types.h>
+
+/*
+ * various IOMUX output functions
+ */
+
+#define IOMUX_OCONFIG_GPIO (0 << 4)     /* used as GPIO */
+#define IOMUX_OCONFIG_FUNC (1 << 4)     /* used as function */
+#define IOMUX_OCONFIG_ALT1 (2 << 4)     /* used as alternate function 1 */
+#define IOMUX_OCONFIG_ALT2 (3 << 4)     /* used as alternate function 2 */
+#define IOMUX_OCONFIG_ALT3 (4 << 4)     /* used as alternate function 3 */
+#define IOMUX_OCONFIG_ALT4 (5 << 4)     /* used as alternate function 4 */
+#define IOMUX_OCONFIG_ALT5 (6 << 4)     /* used as alternate function 5 */
+#define IOMUX_OCONFIG_ALT6 (7 << 4)     /* used as alternate function 6 */
+#define IOMUX_ICONFIG_NONE  0           /* not configured for input */
+#define IOMUX_ICONFIG_GPIO  1           /* used as GPIO */
+#define IOMUX_ICONFIG_FUNC  2           /* used as function */
+#define IOMUX_ICONFIG_ALT1  4           /* used as alternate function 1 */
+#define IOMUX_ICONFIG_ALT2  8           /* used as alternate function 2 */
+
+#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
+#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
+#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
+#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
+
+/*
+ * various IOMUX pad functions
+ */
+enum iomux_pad_config {
+        PAD_CTL_NOLOOPBACK      = 0x0 << 9,
+        PAD_CTL_LOOPBACK        = 0x1 << 9,
+        PAD_CTL_PKE_NONE        = 0x0 << 8,
+        PAD_CTL_PKE_ENABLE      = 0x1 << 8,
+        PAD_CTL_PUE_KEEPER      = 0x0 << 7,
+        PAD_CTL_PUE_PUD         = 0x1 << 7,
+        PAD_CTL_100K_PD         = 0x0 << 5,
+        PAD_CTL_100K_PU         = 0x1 << 5,
+        PAD_CTL_47K_PU          = 0x2 << 5,
+        PAD_CTL_22K_PU          = 0x3 << 5,
+        PAD_CTL_HYS_CMOS        = 0x0 << 4,
+        PAD_CTL_HYS_SCHMITZ     = 0x1 << 4,
+        PAD_CTL_ODE_CMOS        = 0x0 << 3,
+        PAD_CTL_ODE_OpenDrain   = 0x1 << 3,
+        PAD_CTL_DRV_NORMAL      = 0x0 << 1,
+        PAD_CTL_DRV_HIGH        = 0x1 << 1,
+        PAD_CTL_DRV_MAX         = 0x2 << 1,
+        PAD_CTL_SRE_SLOW        = 0x0 << 0,
+        PAD_CTL_SRE_FAST        = 0x1 << 0
+};
+
+/*
+ * various IOMUX general purpose functions
+ */
+enum iomux_gp_func {
+        MUX_PGP_FIRI                    = 1 << 0,
+        MUX_DDR_MODE                    = 1 << 1,
+        MUX_PGP_CSPI_BB                 = 1 << 2,
+        MUX_PGP_ATA_1                   = 1 << 3,
+        MUX_PGP_ATA_2                   = 1 << 4,
+        MUX_PGP_ATA_3                   = 1 << 5,
+        MUX_PGP_ATA_4                   = 1 << 6,
+        MUX_PGP_ATA_5                   = 1 << 7,
+        MUX_PGP_ATA_6                   = 1 << 8,
+        MUX_PGP_ATA_7                   = 1 << 9,
+        MUX_PGP_ATA_8                   = 1 << 10,
+        MUX_PGP_UH2                     = 1 << 11,
+        MUX_SDCTL_CSD0_SEL              = 1 << 12,
+        MUX_SDCTL_CSD1_SEL              = 1 << 13,
+        MUX_CSPI1_UART3                 = 1 << 14,
+        MUX_EXTDMAREQ2_MBX_SEL          = 1 << 15,
+        MUX_TAMPER_DETECT_EN            = 1 << 16,
+        MUX_PGP_USB_4WIRE               = 1 << 17,
+        MUX_PGB_USB_COMMON              = 1 << 18,
+        MUX_SDHC_MEMSTICK1              = 1 << 19,
+        MUX_SDHC_MEMSTICK2              = 1 << 20,
+        MUX_PGP_SPLL_BYP                = 1 << 21,
+        MUX_PGP_UPLL_BYP                = 1 << 22,
+        MUX_PGP_MSHC1_CLK_SEL           = 1 << 23,
+        MUX_PGP_MSHC2_CLK_SEL           = 1 << 24,
+        MUX_CSPI3_UART5_SEL             = 1 << 25,
+        MUX_PGP_ATA_9                   = 1 << 26,
+        MUX_PGP_USB_SUSPEND             = 1 << 27,
+        MUX_PGP_USB_OTG_LOOPBACK        = 1 << 28,
+        MUX_PGP_USB_HS1_LOOPBACK        = 1 << 29,
+        MUX_PGP_USB_HS2_LOOPBACK        = 1 << 30,
+        MUX_CLKO_DDR_MODE               = 1 << 31,
+};
+
+/*
+ * This function enables/disables the general purpose function for a particular
+ * signal.
+ */
+void iomux_config_gpr(enum iomux_gp_func , bool);
+
+/*
+ * set the mode for a IOMUX pin.
+ */
+int mxc_iomux_mode(unsigned int);
+
+/*
+ * This function enables/disables the general purpose function for a particular
+ * signal.
+ */
+void mxc_iomux_set_gpr(enum iomux_gp_func, bool);
+
+#define IOMUX_PADNUM_MASK       0x1ff
+#define IOMUX_GPIONUM_SHIFT     9
+#define IOMUX_GPIONUM_MASK      (0xff << IOMUX_GPIONUM_SHIFT)
+#define IOMUX_MODE_SHIFT        17
+#define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT)
+
+#define IOMUX_PIN(gpionum, padnum) \
+        (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \
+         (padnum & IOMUX_PADNUM_MASK))
+
+#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT)
+
+#define IOMUX_TO_GPIO(iomux_pin) \
+        ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
+#define IOMUX_TO_IRQ(iomux_pin) \
+        (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \
+        MXC_GPIO_INT_BASE)
+
+/*
+ * This enumeration is constructed based on the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
+ * value is constructed based on the rules described above.
+ */
+
+enum iomux_pins {
+        MX31_PIN_TTM_PAD        = IOMUX_PIN(0xff,   0),
+        MX31_PIN_CSPI3_SPI_RDY  = IOMUX_PIN(0xff,   1),
+        MX31_PIN_CSPI3_SCLK     = IOMUX_PIN(0xff,   2),
+        MX31_PIN_CSPI3_MISO     = IOMUX_PIN(0xff,   3),
+        MX31_PIN_CSPI3_MOSI     = IOMUX_PIN(0xff,   4),
+        MX31_PIN_CLKSS          = IOMUX_PIN(0xff,   5),
+        MX31_PIN_CE_CONTROL     = IOMUX_PIN(0xff,   6),
+        MX31_PIN_ATA_RESET_B    = IOMUX_PIN(95,     7),
+        MX31_PIN_ATA_DMACK      = IOMUX_PIN(94,     8),
+        MX31_PIN_ATA_DIOW       = IOMUX_PIN(93,     9),
+        MX31_PIN_ATA_DIOR       = IOMUX_PIN(92,    10),
+        MX31_PIN_ATA_CS1        = IOMUX_PIN(91,    11),
+        MX31_PIN_ATA_CS0        = IOMUX_PIN(90,    12),
+        MX31_PIN_SD1_DATA3      = IOMUX_PIN(63,    13),
+        MX31_PIN_SD1_DATA2      = IOMUX_PIN(62,    14),
+        MX31_PIN_SD1_DATA1      = IOMUX_PIN(61,    15),
+        MX31_PIN_SD1_DATA0      = IOMUX_PIN(60,    16),
+        MX31_PIN_SD1_CLK        = IOMUX_PIN(59,    17),
+        MX31_PIN_SD1_CMD        = IOMUX_PIN(58,    18),
+        MX31_PIN_D3_SPL         = IOMUX_PIN(0xff,  19),
+        MX31_PIN_D3_CLS         = IOMUX_PIN(0xff,  20),
+        MX31_PIN_D3_REV         = IOMUX_PIN(0xff,  21),
+        MX31_PIN_CONTRAST       = IOMUX_PIN(0xff,  22),
+        MX31_PIN_VSYNC3         = IOMUX_PIN(0xff,  23),
+        MX31_PIN_READ           = IOMUX_PIN(0xff,  24),
+        MX31_PIN_WRITE          = IOMUX_PIN(0xff,  25),
+        MX31_PIN_PAR_RS         = IOMUX_PIN(0xff,  26),
+        MX31_PIN_SER_RS         = IOMUX_PIN(89,    27),
+        MX31_PIN_LCS1           = IOMUX_PIN(88,    28),
+        MX31_PIN_LCS0           = IOMUX_PIN(87,    29),
+        MX31_PIN_SD_D_CLK       = IOMUX_PIN(86,    30),
+        MX31_PIN_SD_D_IO        = IOMUX_PIN(85,    31),
+        MX31_PIN_SD_D_I         = IOMUX_PIN(84,    32),
+        MX31_PIN_DRDY0          = IOMUX_PIN(0xff,  33),
+        MX31_PIN_FPSHIFT        = IOMUX_PIN(0xff,  34),
+        MX31_PIN_HSYNC          = IOMUX_PIN(0xff,  35),
+        MX31_PIN_VSYNC0         = IOMUX_PIN(0xff,  36),
+        MX31_PIN_LD17           = IOMUX_PIN(0xff,  37),
+        MX31_PIN_LD16           = IOMUX_PIN(0xff,  38),
+        MX31_PIN_LD15           = IOMUX_PIN(0xff,  39),
+        MX31_PIN_LD14           = IOMUX_PIN(0xff,  40),
+        MX31_PIN_LD13           = IOMUX_PIN(0xff,  41),
+        MX31_PIN_LD12           = IOMUX_PIN(0xff,  42),
+        MX31_PIN_LD11           = IOMUX_PIN(0xff,  43),
+        MX31_PIN_LD10           = IOMUX_PIN(0xff,  44),
+        MX31_PIN_LD9            = IOMUX_PIN(0xff,  45),
+        MX31_PIN_LD8            = IOMUX_PIN(0xff,  46),
+        MX31_PIN_LD7            = IOMUX_PIN(0xff,  47),
+        MX31_PIN_LD6            = IOMUX_PIN(0xff,  48),
+        MX31_PIN_LD5            = IOMUX_PIN(0xff,  49),
+        MX31_PIN_LD4            = IOMUX_PIN(0xff,  50),
+        MX31_PIN_LD3            = IOMUX_PIN(0xff,  51),
+        MX31_PIN_LD2            = IOMUX_PIN(0xff,  52),
+        MX31_PIN_LD1            = IOMUX_PIN(0xff,  53),
+        MX31_PIN_LD0            = IOMUX_PIN(0xff,  54),
+        MX31_PIN_USBH2_DATA1    = IOMUX_PIN(0xff,  55),
+        MX31_PIN_USBH2_DATA0    = IOMUX_PIN(0xff,  56),
+        MX31_PIN_USBH2_NXT      = IOMUX_PIN(0xff,  57),
+        MX31_PIN_USBH2_STP      = IOMUX_PIN(0xff,  58),
+        MX31_PIN_USBH2_DIR      = IOMUX_PIN(0xff,  59),
+        MX31_PIN_USBH2_CLK      = IOMUX_PIN(0xff,  60),
+        MX31_PIN_USBOTG_DATA7   = IOMUX_PIN(0xff,  61),
+        MX31_PIN_USBOTG_DATA6   = IOMUX_PIN(0xff,  62),
+        MX31_PIN_USBOTG_DATA5   = IOMUX_PIN(0xff,  63),
+        MX31_PIN_USBOTG_DATA4   = IOMUX_PIN(0xff,  64),
+        MX31_PIN_USBOTG_DATA3   = IOMUX_PIN(0xff,  65),
+        MX31_PIN_USBOTG_DATA2   = IOMUX_PIN(0xff,  66),
+        MX31_PIN_USBOTG_DATA1   = IOMUX_PIN(0xff,  67),
+        MX31_PIN_USBOTG_DATA0   = IOMUX_PIN(0xff,  68),
+        MX31_PIN_USBOTG_NXT     = IOMUX_PIN(0xff,  69),
+        MX31_PIN_USBOTG_STP     = IOMUX_PIN(0xff,  70),
+        MX31_PIN_USBOTG_DIR     = IOMUX_PIN(0xff,  71),
+        MX31_PIN_USBOTG_CLK     = IOMUX_PIN(0xff,  72),
+        MX31_PIN_USB_BYP        = IOMUX_PIN(31,    73),
+        MX31_PIN_USB_OC         = IOMUX_PIN(30,    74),
+        MX31_PIN_USB_PWR        = IOMUX_PIN(29,    75),
+        MX31_PIN_SJC_MOD        = IOMUX_PIN(0xff,  76),
+        MX31_PIN_DE_B           = IOMUX_PIN(0xff,  77),
+        MX31_PIN_TRSTB          = IOMUX_PIN(0xff,  78),
+        MX31_PIN_TDO            = IOMUX_PIN(0xff,  79),
+        MX31_PIN_TDI            = IOMUX_PIN(0xff,  80),
+        MX31_PIN_TMS            = IOMUX_PIN(0xff,  81),
+        MX31_PIN_TCK            = IOMUX_PIN(0xff,  82),
+        MX31_PIN_RTCK           = IOMUX_PIN(0xff,  83),
+        MX31_PIN_KEY_COL7       = IOMUX_PIN(57,    84),
+        MX31_PIN_KEY_COL6       = IOMUX_PIN(56,    85),
+        MX31_PIN_KEY_COL5       = IOMUX_PIN(55,    86),
+        MX31_PIN_KEY_COL4       = IOMUX_PIN(54,    87),
+        MX31_PIN_KEY_COL3       = IOMUX_PIN(0xff,  88),
+        MX31_PIN_KEY_COL2       = IOMUX_PIN(0xff,  89),
+        MX31_PIN_KEY_COL1       = IOMUX_PIN(0xff,  90),
+        MX31_PIN_KEY_COL0       = IOMUX_PIN(0xff,  91),
+        MX31_PIN_KEY_ROW7       = IOMUX_PIN(53,    92),
+        MX31_PIN_KEY_ROW6       = IOMUX_PIN(52,    93),
+        MX31_PIN_KEY_ROW5       = IOMUX_PIN(51,    94),
+        MX31_PIN_KEY_ROW4       = IOMUX_PIN(50,    95),
+        MX31_PIN_KEY_ROW3       = IOMUX_PIN(0xff,  96),
+        MX31_PIN_KEY_ROW2       = IOMUX_PIN(0xff,  97),
+        MX31_PIN_KEY_ROW1       = IOMUX_PIN(0xff,  98),
+        MX31_PIN_KEY_ROW0       = IOMUX_PIN(0xff,  99),
+        MX31_PIN_BATT_LINE      = IOMUX_PIN(49,   100),
+        MX31_PIN_CTS2           = IOMUX_PIN(0xff, 101),
+        MX31_PIN_RTS2           = IOMUX_PIN(0xff, 102),
+        MX31_PIN_TXD2           = IOMUX_PIN(28,   103),
+        MX31_PIN_RXD2           = IOMUX_PIN(27,   104),
+        MX31_PIN_DTR_DCE2       = IOMUX_PIN(48,   105),
+        MX31_PIN_DCD_DTE1       = IOMUX_PIN(47,   106),
+        MX31_PIN_RI_DTE1        = IOMUX_PIN(46,   107),
+        MX31_PIN_DSR_DTE1       = IOMUX_PIN(45,   108),
+        MX31_PIN_DTR_DTE1       = IOMUX_PIN(44,   109),
+        MX31_PIN_DCD_DCE1       = IOMUX_PIN(43,   110),
+        MX31_PIN_RI_DCE1        = IOMUX_PIN(42,   111),
+        MX31_PIN_DSR_DCE1       = IOMUX_PIN(41,   112),
+        MX31_PIN_DTR_DCE1       = IOMUX_PIN(40,   113),
+        MX31_PIN_CTS1           = IOMUX_PIN(39,   114),
+        MX31_PIN_RTS1           = IOMUX_PIN(38,   115),
+        MX31_PIN_TXD1           = IOMUX_PIN(37,   116),
+        MX31_PIN_RXD1           = IOMUX_PIN(36,   117),
+        MX31_PIN_CSPI2_SPI_RDY  = IOMUX_PIN(0xff, 118),
+        MX31_PIN_CSPI2_SCLK     = IOMUX_PIN(0xff, 119),
+        MX31_PIN_CSPI2_SS2      = IOMUX_PIN(0xff, 120),
+        MX31_PIN_CSPI2_SS1      = IOMUX_PIN(0xff, 121),
+        MX31_PIN_CSPI2_SS0      = IOMUX_PIN(0xff, 122),
+        MX31_PIN_CSPI2_MISO     = IOMUX_PIN(0xff, 123),
+        MX31_PIN_CSPI2_MOSI     = IOMUX_PIN(0xff, 124),
+        MX31_PIN_CSPI1_SPI_RDY  = IOMUX_PIN(0xff, 125),
+        MX31_PIN_CSPI1_SCLK     = IOMUX_PIN(0xff, 126),
+        MX31_PIN_CSPI1_SS2      = IOMUX_PIN(0xff, 127),
+        MX31_PIN_CSPI1_SS1      = IOMUX_PIN(0xff, 128),
+        MX31_PIN_CSPI1_SS0      = IOMUX_PIN(0xff, 129),
+        MX31_PIN_CSPI1_MISO     = IOMUX_PIN(0xff, 130),
+        MX31_PIN_CSPI1_MOSI     = IOMUX_PIN(0xff, 131),
+        MX31_PIN_SFS6           = IOMUX_PIN(26,   132),
+        MX31_PIN_SCK6           = IOMUX_PIN(25,   133),
+        MX31_PIN_SRXD6          = IOMUX_PIN(24,   134),
+        MX31_PIN_STXD6          = IOMUX_PIN(23,   135),
+        MX31_PIN_SFS5           = IOMUX_PIN(0xff, 136),
+        MX31_PIN_SCK5           = IOMUX_PIN(0xff, 137),
+        MX31_PIN_SRXD5          = IOMUX_PIN(22,   138),
+        MX31_PIN_STXD5          = IOMUX_PIN(21,   139),
+        MX31_PIN_SFS4           = IOMUX_PIN(0xff, 140),
+        MX31_PIN_SCK4           = IOMUX_PIN(0xff, 141),
+        MX31_PIN_SRXD4          = IOMUX_PIN(20,   142),
+        MX31_PIN_STXD4          = IOMUX_PIN(19,   143),
+        MX31_PIN_SFS3           = IOMUX_PIN(0xff, 144),
+        MX31_PIN_SCK3           = IOMUX_PIN(0xff, 145),
+        MX31_PIN_SRXD3          = IOMUX_PIN(18,   146),
+        MX31_PIN_STXD3          = IOMUX_PIN(17,   147),
+        MX31_PIN_I2C_DAT        = IOMUX_PIN(0xff, 148),
+        MX31_PIN_I2C_CLK        = IOMUX_PIN(0xff, 149),
+        MX31_PIN_CSI_PIXCLK     = IOMUX_PIN(83,   150),
+        MX31_PIN_CSI_HSYNC      = IOMUX_PIN(82,   151),
+        MX31_PIN_CSI_VSYNC      = IOMUX_PIN(81,   152),
+        MX31_PIN_CSI_MCLK       = IOMUX_PIN(80,   153),
+        MX31_PIN_CSI_D15        = IOMUX_PIN(79,   154),
+        MX31_PIN_CSI_D14        = IOMUX_PIN(78,   155),
+        MX31_PIN_CSI_D13        = IOMUX_PIN(77,   156),
+        MX31_PIN_CSI_D12        = IOMUX_PIN(76,   157),
+        MX31_PIN_CSI_D11        = IOMUX_PIN(75,   158),
+        MX31_PIN_CSI_D10        = IOMUX_PIN(74,   159),
+        MX31_PIN_CSI_D9         = IOMUX_PIN(73,   160),
+        MX31_PIN_CSI_D8         = IOMUX_PIN(72,   161),
+        MX31_PIN_CSI_D7         = IOMUX_PIN(71,   162),
+        MX31_PIN_CSI_D6         = IOMUX_PIN(70,   163),
+        MX31_PIN_CSI_D5         = IOMUX_PIN(69,   164),
+        MX31_PIN_CSI_D4         = IOMUX_PIN(68,   165),
+        MX31_PIN_M_GRANT        = IOMUX_PIN(0xff, 166),
+        MX31_PIN_M_REQUEST      = IOMUX_PIN(0xff, 167),
+        MX31_PIN_PC_POE         = IOMUX_PIN(0xff, 168),
+        MX31_PIN_PC_RW_B        = IOMUX_PIN(0xff, 169),
+        MX31_PIN_IOIS16         = IOMUX_PIN(0xff, 170),
+        MX31_PIN_PC_RST         = IOMUX_PIN(0xff, 171),
+        MX31_PIN_PC_BVD2        = IOMUX_PIN(0xff, 172),
+        MX31_PIN_PC_BVD1        = IOMUX_PIN(0xff, 173),
+        MX31_PIN_PC_VS2         = IOMUX_PIN(0xff, 174),
+        MX31_PIN_PC_VS1         = IOMUX_PIN(0xff, 175),
+        MX31_PIN_PC_PWRON       = IOMUX_PIN(0xff, 176),
+        MX31_PIN_PC_READY       = IOMUX_PIN(0xff, 177),
+        MX31_PIN_PC_WAIT_B      = IOMUX_PIN(0xff, 178),
+        MX31_PIN_PC_CD2_B       = IOMUX_PIN(0xff, 179),
+        MX31_PIN_PC_CD1_B       = IOMUX_PIN(0xff, 180),
+        MX31_PIN_D0             = IOMUX_PIN(0xff, 181),
+        MX31_PIN_D1             = IOMUX_PIN(0xff, 182),
+        MX31_PIN_D2             = IOMUX_PIN(0xff, 183),
+        MX31_PIN_D3             = IOMUX_PIN(0xff, 184),
+        MX31_PIN_D4             = IOMUX_PIN(0xff, 185),
+        MX31_PIN_D5             = IOMUX_PIN(0xff, 186),
+        MX31_PIN_D6             = IOMUX_PIN(0xff, 187),
+        MX31_PIN_D7             = IOMUX_PIN(0xff, 188),
+        MX31_PIN_D8             = IOMUX_PIN(0xff, 189),
+        MX31_PIN_D9             = IOMUX_PIN(0xff, 190),
+        MX31_PIN_D10            = IOMUX_PIN(0xff, 191),
+        MX31_PIN_D11            = IOMUX_PIN(0xff, 192),
+        MX31_PIN_D12            = IOMUX_PIN(0xff, 193),
+        MX31_PIN_D13            = IOMUX_PIN(0xff, 194),
+        MX31_PIN_D14            = IOMUX_PIN(0xff, 195),
+        MX31_PIN_D15            = IOMUX_PIN(0xff, 196),
+        MX31_PIN_NFRB           = IOMUX_PIN(16,   197),
+        MX31_PIN_NFCE_B         = IOMUX_PIN(15,   198),
+        MX31_PIN_NFWP_B         = IOMUX_PIN(14,   199),
+        MX31_PIN_NFCLE          = IOMUX_PIN(13,   200),
+        MX31_PIN_NFALE          = IOMUX_PIN(12,   201),
+        MX31_PIN_NFRE_B         = IOMUX_PIN(11,   202),
+        MX31_PIN_NFWE_B         = IOMUX_PIN(10,   203),
+        MX31_PIN_SDQS3          = IOMUX_PIN(0xff, 204),
+        MX31_PIN_SDQS2          = IOMUX_PIN(0xff, 205),
+        MX31_PIN_SDQS1          = IOMUX_PIN(0xff, 206),
+        MX31_PIN_SDQS0          = IOMUX_PIN(0xff, 207),
+        MX31_PIN_SDCLK_B        = IOMUX_PIN(0xff, 208),
+        MX31_PIN_SDCLK          = IOMUX_PIN(0xff, 209),
+        MX31_PIN_SDCKE1         = IOMUX_PIN(0xff, 210),
+        MX31_PIN_SDCKE0         = IOMUX_PIN(0xff, 211),
+        MX31_PIN_SDWE           = IOMUX_PIN(0xff, 212),
+        MX31_PIN_CAS            = IOMUX_PIN(0xff, 213),
+        MX31_PIN_RAS            = IOMUX_PIN(0xff, 214),
+        MX31_PIN_RW             = IOMUX_PIN(0xff, 215),
+        MX31_PIN_BCLK           = IOMUX_PIN(0xff, 216),
+        MX31_PIN_LBA            = IOMUX_PIN(0xff, 217),
+        MX31_PIN_ECB            = IOMUX_PIN(0xff, 218),
+        MX31_PIN_CS5            = IOMUX_PIN(0xff, 219),
+        MX31_PIN_CS4            = IOMUX_PIN(0xff, 220),
+        MX31_PIN_CS3            = IOMUX_PIN(0xff, 221),
+        MX31_PIN_CS2            = IOMUX_PIN(0xff, 222),
+        MX31_PIN_CS1            = IOMUX_PIN(0xff, 223),
+        MX31_PIN_CS0            = IOMUX_PIN(0xff, 224),
+        MX31_PIN_OE             = IOMUX_PIN(0xff, 225),
+        MX31_PIN_EB1            = IOMUX_PIN(0xff, 226),
+        MX31_PIN_EB0            = IOMUX_PIN(0xff, 227),
+        MX31_PIN_DQM3           = IOMUX_PIN(0xff, 228),
+        MX31_PIN_DQM2           = IOMUX_PIN(0xff, 229),
+        MX31_PIN_DQM1           = IOMUX_PIN(0xff, 230),
+        MX31_PIN_DQM0           = IOMUX_PIN(0xff, 231),
+        MX31_PIN_SD31           = IOMUX_PIN(0xff, 232),
+        MX31_PIN_SD30           = IOMUX_PIN(0xff, 233),
+        MX31_PIN_SD29           = IOMUX_PIN(0xff, 234),
+        MX31_PIN_SD28           = IOMUX_PIN(0xff, 235),
+        MX31_PIN_SD27           = IOMUX_PIN(0xff, 236),
+        MX31_PIN_SD26           = IOMUX_PIN(0xff, 237),
+        MX31_PIN_SD25           = IOMUX_PIN(0xff, 238),
+        MX31_PIN_SD24           = IOMUX_PIN(0xff, 239),
+        MX31_PIN_SD23           = IOMUX_PIN(0xff, 240),
+        MX31_PIN_SD22           = IOMUX_PIN(0xff, 241),
+        MX31_PIN_SD21           = IOMUX_PIN(0xff, 242),
+        MX31_PIN_SD20           = IOMUX_PIN(0xff, 243),
+        MX31_PIN_SD19           = IOMUX_PIN(0xff, 244),
+        MX31_PIN_SD18           = IOMUX_PIN(0xff, 245),
+        MX31_PIN_SD17           = IOMUX_PIN(0xff, 246),
+        MX31_PIN_SD16           = IOMUX_PIN(0xff, 247),
+        MX31_PIN_SD15           = IOMUX_PIN(0xff, 248),
+        MX31_PIN_SD14           = IOMUX_PIN(0xff, 249),
+        MX31_PIN_SD13           = IOMUX_PIN(0xff, 250),
+        MX31_PIN_SD12           = IOMUX_PIN(0xff, 251),
+        MX31_PIN_SD11           = IOMUX_PIN(0xff, 252),
+        MX31_PIN_SD10           = IOMUX_PIN(0xff, 253),
+        MX31_PIN_SD9            = IOMUX_PIN(0xff, 254),
+        MX31_PIN_SD8            = IOMUX_PIN(0xff, 255),
+        MX31_PIN_SD7            = IOMUX_PIN(0xff, 256),
+        MX31_PIN_SD6            = IOMUX_PIN(0xff, 257),
+        MX31_PIN_SD5            = IOMUX_PIN(0xff, 258),
+        MX31_PIN_SD4            = IOMUX_PIN(0xff, 259),
+        MX31_PIN_SD3            = IOMUX_PIN(0xff, 260),
+        MX31_PIN_SD2            = IOMUX_PIN(0xff, 261),
+        MX31_PIN_SD1            = IOMUX_PIN(0xff, 262),
+        MX31_PIN_SD0            = IOMUX_PIN(0xff, 263),
+        MX31_PIN_SDBA0          = IOMUX_PIN(0xff, 264),
+        MX31_PIN_SDBA1          = IOMUX_PIN(0xff, 265),
+        MX31_PIN_A25            = IOMUX_PIN(0xff, 266),
+        MX31_PIN_A24            = IOMUX_PIN(0xff, 267),
+        MX31_PIN_A23            = IOMUX_PIN(0xff, 268),
+        MX31_PIN_A22            = IOMUX_PIN(0xff, 269),
+        MX31_PIN_A21            = IOMUX_PIN(0xff, 270),
+        MX31_PIN_A20            = IOMUX_PIN(0xff, 271),
+        MX31_PIN_A19            = IOMUX_PIN(0xff, 272),
+        MX31_PIN_A18            = IOMUX_PIN(0xff, 273),
+        MX31_PIN_A17            = IOMUX_PIN(0xff, 274),
+        MX31_PIN_A16            = IOMUX_PIN(0xff, 275),
+        MX31_PIN_A14            = IOMUX_PIN(0xff, 276),
+        MX31_PIN_A15            = IOMUX_PIN(0xff, 277),
+        MX31_PIN_A13            = IOMUX_PIN(0xff, 278),
+        MX31_PIN_A12            = IOMUX_PIN(0xff, 279),
+        MX31_PIN_A11            = IOMUX_PIN(0xff, 280),
+        MX31_PIN_MA10           = IOMUX_PIN(0xff, 281),
+        MX31_PIN_A10            = IOMUX_PIN(0xff, 282),
+        MX31_PIN_A9             = IOMUX_PIN(0xff, 283),
+        MX31_PIN_A8             = IOMUX_PIN(0xff, 284),
+        MX31_PIN_A7             = IOMUX_PIN(0xff, 285),
+        MX31_PIN_A6             = IOMUX_PIN(0xff, 286),
+        MX31_PIN_A5             = IOMUX_PIN(0xff, 287),
+        MX31_PIN_A4             = IOMUX_PIN(0xff, 288),
+        MX31_PIN_A3             = IOMUX_PIN(0xff, 289),
+        MX31_PIN_A2             = IOMUX_PIN(0xff, 290),
+        MX31_PIN_A1             = IOMUX_PIN(0xff, 291),
+        MX31_PIN_A0             = IOMUX_PIN(0xff, 292),
+        MX31_PIN_VPG1           = IOMUX_PIN(0xff, 293),
+        MX31_PIN_VPG0           = IOMUX_PIN(0xff, 294),
+        MX31_PIN_DVFS1          = IOMUX_PIN(0xff, 295),
+        MX31_PIN_DVFS0          = IOMUX_PIN(0xff, 296),
+        MX31_PIN_VSTBY          = IOMUX_PIN(0xff, 297),
+        MX31_PIN_POWER_FAIL     = IOMUX_PIN(0xff, 298),
+        MX31_PIN_CKIL           = IOMUX_PIN(0xff, 299),
+        MX31_PIN_BOOT_MODE4     = IOMUX_PIN(0xff, 300),
+        MX31_PIN_BOOT_MODE3     = IOMUX_PIN(0xff, 301),
+        MX31_PIN_BOOT_MODE2     = IOMUX_PIN(0xff, 302),
+        MX31_PIN_BOOT_MODE1     = IOMUX_PIN(0xff, 303),
+        MX31_PIN_BOOT_MODE0     = IOMUX_PIN(0xff, 304),
+        MX31_PIN_CLKO           = IOMUX_PIN(0xff, 305),
+        MX31_PIN_POR_B          = IOMUX_PIN(0xff, 306),
+        MX31_PIN_RESET_IN_B     = IOMUX_PIN(0xff, 307),
+        MX31_PIN_CKIH           = IOMUX_PIN(0xff, 308),
+        MX31_PIN_SIMPD0         = IOMUX_PIN(35,   309),
+        MX31_PIN_SRX0           = IOMUX_PIN(34,   310),
+        MX31_PIN_STX0           = IOMUX_PIN(33,   311),
+        MX31_PIN_SVEN0          = IOMUX_PIN(32,   312),
+        MX31_PIN_SRST0          = IOMUX_PIN(67,   313),
+        MX31_PIN_SCLK0          = IOMUX_PIN(66,   314),
+        MX31_PIN_GPIO3_1        = IOMUX_PIN(65,   315),
+        MX31_PIN_GPIO3_0        = IOMUX_PIN(64,   316),
+        MX31_PIN_GPIO1_6        = IOMUX_PIN( 6,   317),
+        MX31_PIN_GPIO1_5        = IOMUX_PIN( 5,   318),
+        MX31_PIN_GPIO1_4        = IOMUX_PIN( 4,   319),
+        MX31_PIN_GPIO1_3        = IOMUX_PIN( 3,   320),
+        MX31_PIN_GPIO1_2        = IOMUX_PIN( 2,   321),
+        MX31_PIN_GPIO1_1        = IOMUX_PIN( 1,   322),
+        MX31_PIN_GPIO1_0        = IOMUX_PIN( 0,   323),
+        MX31_PIN_PWMO           = IOMUX_PIN( 9,   324),
+        MX31_PIN_WATCHDOG_RST   = IOMUX_PIN(0xff, 325),
+        MX31_PIN_COMPARE        = IOMUX_PIN( 8,   326),
+        MX31_PIN_CAPTURE        = IOMUX_PIN( 7,   327),
+};
+
+/*
+ * Convenience values for use with mxc_iomux_mode()
+ *
+ * Format here is MX31_PIN_(pin name)__(function)
+ */
+#define MX31_PIN_CSPI3_MOSI__RXD3       IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI3_MISO__TXD3       IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CTS1__CTS1             IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RTS1__RTS1             IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_TXD1__TXD1             IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RXD1__RXD1             IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
+
+/*
+ * This function configures the pad value for a IOMUX pin.
+ */
+void mxc_iomux_set_pad(enum iomux_pins, u32);
+
+#endif
+
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
new file mode 100644
index 000000000000..228c4f68ccdf
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -0,0 +1,16 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_IRQS_H__
+#define __ASM_ARCH_MXC_IRQS_H__
+
+#include <mach/hardware.h>
+
+#endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
new file mode 100644
index 000000000000..d7a8d3ebed57
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_MEMORY_H__
+#define __ASM_ARCH_MXC_MEMORY_H__
+
+#include <mach/hardware.h>
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * This macro is used to translate the virtual address to an address
+ * suitable to be passed to set_dma_addr()
+ */
+#define __virt_to_bus(a)        __virt_to_phys(a)
+
+/*
+ * Used to convert an address for DMA operations to an address that the
+ * kernel can use.
+ */
+#define __bus_to_virt(a)        __phys_to_virt(a)
+
+#endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
new file mode 100644
index 000000000000..212ecc246626
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -0,0 +1,302 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_MX27_H__
+#define __ASM_ARCH_MXC_MX27_H__
+
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#error "Do not include directly."
+#endif
+
+/* IRAM */
+#define IRAM_BASE_ADDR          0xFFFF4C00      /* internal ram */
+
+/* Register offests */
+#define AIPI_BASE_ADDR          0x10000000
+#define AIPI_BASE_ADDR_VIRT     0xF4000000
+#define AIPI_SIZE               SZ_1M
+
+#define DMA_BASE_ADDR           (AIPI_BASE_ADDR + 0x01000)
+#define WDOG_BASE_ADDR          (AIPI_BASE_ADDR + 0x02000)
+#define GPT1_BASE_ADDR          (AIPI_BASE_ADDR + 0x03000)
+#define GPT2_BASE_ADDR          (AIPI_BASE_ADDR + 0x04000)
+#define GPT3_BASE_ADDR          (AIPI_BASE_ADDR + 0x05000)
+#define PWM_BASE_ADDR           (AIPI_BASE_ADDR + 0x06000)
+#define RTC_BASE_ADDR           (AIPI_BASE_ADDR + 0x07000)
+#define KPP_BASE_ADDR           (AIPI_BASE_ADDR + 0x08000)
+#define OWIRE_BASE_ADDR         (AIPI_BASE_ADDR + 0x09000)
+#define UART1_BASE_ADDR         (AIPI_BASE_ADDR + 0x0A000)
+#define UART2_BASE_ADDR         (AIPI_BASE_ADDR + 0x0B000)
+#define UART3_BASE_ADDR         (AIPI_BASE_ADDR + 0x0C000)
+#define UART4_BASE_ADDR         (AIPI_BASE_ADDR + 0x0D000)
+#define CSPI1_BASE_ADDR         (AIPI_BASE_ADDR + 0x0E000)
+#define CSPI2_BASE_ADDR         (AIPI_BASE_ADDR + 0x0F000)
+#define SSI1_BASE_ADDR          (AIPI_BASE_ADDR + 0x10000)
+#define SSI2_BASE_ADDR          (AIPI_BASE_ADDR + 0x11000)
+#define I2C_BASE_ADDR           (AIPI_BASE_ADDR + 0x12000)
+#define SDHC1_BASE_ADDR         (AIPI_BASE_ADDR + 0x13000)
+#define SDHC2_BASE_ADDR         (AIPI_BASE_ADDR + 0x14000)
+#define GPIO_BASE_ADDR          (AIPI_BASE_ADDR + 0x15000)
+#define AUDMUX_BASE_ADDR        (AIPI_BASE_ADDR + 0x16000)
+
+#define CSPI3_BASE_ADDR         (AIPI_BASE_ADDR + 0x17000)
+#define MSHC_BASE_ADDR          (AIPI_BASE_ADDR + 0x18000)
+#define GPT5_BASE_ADDR          (AIPI_BASE_ADDR + 0x19000)
+#define GPT4_BASE_ADDR          (AIPI_BASE_ADDR + 0x1A000)
+#define UART5_BASE_ADDR         (AIPI_BASE_ADDR + 0x1B000)
+#define UART6_BASE_ADDR         (AIPI_BASE_ADDR + 0x1C000)
+#define I2C2_BASE_ADDR          (AIPI_BASE_ADDR + 0x1D000)
+#define SDHC3_BASE_ADDR         (AIPI_BASE_ADDR + 0x1E000)
+#define GPT6_BASE_ADDR          (AIPI_BASE_ADDR + 0x1F000)
+
+#define LCDC_BASE_ADDR          (AIPI_BASE_ADDR + 0x21000)
+#define SLCDC_BASE_ADDR         (AIPI_BASE_ADDR + 0x22000)
+#define VPU_BASE_ADDR           (AIPI_BASE_ADDR + 0x23000)
+#define USBOTG_BASE_ADDR        (AIPI_BASE_ADDR + 0x24000)
+/* for mx27*/
+#define OTG_BASE_ADDR           USBOTG_BASE_ADDR
+#define SAHARA_BASE_ADDR        (AIPI_BASE_ADDR + 0x25000)
+#define EMMA_BASE_ADDR          (AIPI_BASE_ADDR + 0x26400)
+#define CCM_BASE_ADDR           (AIPI_BASE_ADDR + 0x27000)
+#define SYSCTRL_BASE_ADDR       (AIPI_BASE_ADDR + 0x27800)
+#define IIM_BASE_ADDR           (AIPI_BASE_ADDR + 0x28000)
+
+#define RTIC_BASE_ADDR          (AIPI_BASE_ADDR + 0x2A000)
+#define FEC_BASE_ADDR           (AIPI_BASE_ADDR + 0x2B000)
+#define SCC_BASE_ADDR           (AIPI_BASE_ADDR + 0x2C000)
+#define ETB_BASE_ADDR           (AIPI_BASE_ADDR + 0x3B000)
+#define ETB_RAM_BASE_ADDR       (AIPI_BASE_ADDR + 0x3C000)
+
+#define JAM_BASE_ADDR           (AIPI_BASE_ADDR + 0x3E000)
+#define MAX_BASE_ADDR           (AIPI_BASE_ADDR + 0x3F000)
+
+/* ROMP and AVIC */
+#define ROMP_BASE_ADDR          0x10041000
+
+#define AVIC_BASE_ADDR          0x10040000
+
+#define SAHB1_BASE_ADDR         0x80000000
+#define SAHB1_BASE_ADDR_VIRT    0xF4100000
+#define SAHB1_SIZE              SZ_1M
+
+#define CSI_BASE_ADDR           (SAHB1_BASE_ADDR + 0x0000)
+#define ATA_BASE_ADDR           (SAHB1_BASE_ADDR + 0x1000)
+
+/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
+#define X_MEMC_BASE_ADDR        0xD8000000
+#define X_MEMC_BASE_ADDR_VIRT   0xF4200000
+#define X_MEMC_SIZE             SZ_1M
+
+#define NFC_BASE_ADDR           (X_MEMC_BASE_ADDR)
+#define SDRAMC_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x1000)
+#define WEIM_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x2000)
+#define M3IF_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x3000)
+#define PCMCIA_CTL_BASE_ADDR    (X_MEMC_BASE_ADDR + 0x4000)
+
+/* Memory regions and CS */
+#define SDRAM_BASE_ADDR         0xA0000000
+#define CSD1_BASE_ADDR          0xB0000000
+
+#define CS0_BASE_ADDR           0xC0000000
+#define CS1_BASE_ADDR           0xC8000000
+#define CS2_BASE_ADDR           0xD0000000
+#define CS3_BASE_ADDR           0xD2000000
+#define CS4_BASE_ADDR           0xD4000000
+#define CS5_BASE_ADDR           0xD6000000
+#define PCMCIA_MEM_BASE_ADDR    0xDC000000
+
+/*
+ * This macro defines the physical to virtual address mapping for all the
+ * peripheral modules. It is used by passing in the physical address as x
+ * and returning the virtual address. If the physical address is not mapped,
+ * it returns 0xDEADBEEF
+ */
+#define IO_ADDRESS(x)   \
+        (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
+                AIPI_IO_ADDRESS(x) : \
+        ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
+                SAHB1_IO_ADDRESS(x) : \
+        ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
+                X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
+
+/* define the address mapping macros: in physical address order */
+#define AIPI_IO_ADDRESS(x)  \
+        (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
+
+#define AVIC_IO_ADDRESS(x)      AIPI_IO_ADDRESS(x)
+
+#define SAHB1_IO_ADDRESS(x)  \
+        (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
+
+#define CS4_IO_ADDRESS(x)  \
+        (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
+
+#define X_MEMC_IO_ADDRESS(x)  \
+        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+
+#define PCMCIA_IO_ADDRESS(x) \
+        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+
+/* fixed interrput numbers */
+#define MXC_INT_CCM             63
+#define MXC_INT_IIM             62
+#define MXC_INT_LCDC            61
+#define MXC_INT_SLCDC           60
+#define MXC_INT_SAHARA          59
+#define MXC_INT_SCC_SCM         58
+#define MXC_INT_SCC_SMN         57
+#define MXC_INT_USB3            56
+#define MXC_INT_USB2            55
+#define MXC_INT_USB1            54
+#define MXC_INT_VPU             53
+#define MXC_INT_EMMAPP          52
+#define MXC_INT_EMMAPRP         51
+#define MXC_INT_FEC             50
+#define MXC_INT_UART5           49
+#define MXC_INT_UART6           48
+#define MXC_INT_DMACH15         47
+#define MXC_INT_DMACH14         46
+#define MXC_INT_DMACH13         45
+#define MXC_INT_DMACH12         44
+#define MXC_INT_DMACH11         43
+#define MXC_INT_DMACH10         42
+#define MXC_INT_DMACH9          41
+#define MXC_INT_DMACH8          40
+#define MXC_INT_DMACH7          39
+#define MXC_INT_DMACH6          38
+#define MXC_INT_DMACH5          37
+#define MXC_INT_DMACH4          36
+#define MXC_INT_DMACH3          35
+#define MXC_INT_DMACH2          34
+#define MXC_INT_DMACH1          33
+#define MXC_INT_DMACH0          32
+#define MXC_INT_CSI             31
+#define MXC_INT_ATA             30
+#define MXC_INT_NANDFC          29
+#define MXC_INT_PCMCIA          28
+#define MXC_INT_WDOG            27
+#define MXC_INT_GPT1            26
+#define MXC_INT_GPT2            25
+#define MXC_INT_GPT3            24
+#define MXC_INT_GPT             INT_GPT1
+#define MXC_INT_PWM             23
+#define MXC_INT_RTC             22
+#define MXC_INT_KPP             21
+#define MXC_INT_UART1           20
+#define MXC_INT_UART2           19
+#define MXC_INT_UART3           18
+#define MXC_INT_UART4           17
+#define MXC_INT_CSPI1           16
+#define MXC_INT_CSPI2           15
+#define MXC_INT_SSI1            14
+#define MXC_INT_SSI2            13
+#define MXC_INT_I2C             12
+#define MXC_INT_SDHC1           11
+#define MXC_INT_SDHC2           10
+#define MXC_INT_SDHC3           9
+#define MXC_INT_GPIO            8
+#define MXC_INT_SDHC            7
+#define MXC_INT_CSPI3           6
+#define MXC_INT_RTIC            5
+#define MXC_INT_GPT4            4
+#define MXC_INT_GPT5            3
+#define MXC_INT_GPT6            2
+#define MXC_INT_I2C2            1
+
+/* fixed DMA request numbers */
+#define DMA_REQ_NFC             37
+#define DMA_REQ_SDHC3           36
+#define DMA_REQ_UART6_RX        35
+#define DMA_REQ_UART6_TX        34
+#define DMA_REQ_UART5_RX        33
+#define DMA_REQ_UART5_TX        32
+#define DMA_REQ_CSI_RX          31
+#define DMA_REQ_CSI_STAT        30
+#define DMA_REQ_ATA_RCV         29
+#define DMA_REQ_ATA_TX          28
+#define DMA_REQ_UART1_TX        27
+#define DMA_REQ_UART1_RX        26
+#define DMA_REQ_UART2_TX        25
+#define DMA_REQ_UART2_RX        24
+#define DMA_REQ_UART3_TX        23
+#define DMA_REQ_UART3_RX        22
+#define DMA_REQ_UART4_TX        21
+#define DMA_REQ_UART4_RX        20
+#define DMA_REQ_CSPI1_TX        19
+#define DMA_REQ_CSPI1_RX        18
+#define DMA_REQ_CSPI2_TX        17
+#define DMA_REQ_CSPI2_RX        16
+#define DMA_REQ_SSI1_TX1        15
+#define DMA_REQ_SSI1_RX1        14
+#define DMA_REQ_SSI1_TX0        13
+#define DMA_REQ_SSI1_RX0        12
+#define DMA_REQ_SSI2_TX1        11
+#define DMA_REQ_SSI2_RX1        10
+#define DMA_REQ_SSI2_TX0        9
+#define DMA_REQ_SSI2_RX0        8
+#define DMA_REQ_SDHC1           7
+#define DMA_REQ_SDHC2           6
+#define DMA_REQ_MSHC            4
+#define DMA_REQ_EXT             3
+#define DMA_REQ_CSPI3_TX        2
+#define DMA_REQ_CSPI3_RX        1
+
+/* silicon revisions specific to i.MX27 */
+#define CHIP_REV_1_0            0x00
+#define CHIP_REV_2_0            0x01
+
+#ifndef __ASSEMBLY__
+extern int mx27_revision(void);
+#endif
+
+/* gpio and gpio based interrupt handling */
+#define GPIO_DR                 0x1C
+#define GPIO_GDIR               0x00
+#define GPIO_PSR                0x24
+#define GPIO_ICR1               0x28
+#define GPIO_ICR2               0x2C
+#define GPIO_IMR                0x30
+#define GPIO_ISR                0x34
+#define GPIO_INT_LOW_LEV        0x3
+#define GPIO_INT_HIGH_LEV       0x2
+#define GPIO_INT_RISE_EDGE      0x0
+#define GPIO_INT_FALL_EDGE      0x1
+#define GPIO_INT_NONE           0x4
+
+/* Mandatory defines used globally */
+
+/* this is an i.MX27 CPU */
+#define cpu_is_mx27()           (1)
+
+/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
+#define ARCH_NR_GPIOS           (192 + 16)
+
+/* OS clock tick rate */
+#define CLOCK_TICK_RATE         13300000
+
+/* Start of RAM */
+#define PHYS_OFFSET             SDRAM_BASE_ADDR
+
+/* max interrupt lines count */
+#define NR_IRQS                 256
+
+/* count of internal interrupt sources */
+#define MXC_MAX_INT_LINES       64
+
+#endif /* __ASM_ARCH_MXC_MX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
new file mode 100644
index 000000000000..a7373e4a56cb
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -0,0 +1,384 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_MX31_H__
+#define __ASM_ARCH_MXC_MX31_H__
+
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#error "Do not include directly."
+#endif
+
+/*!
+ * defines the hardware clock tick rate
+ */
+#define CLOCK_TICK_RATE         16625000
+
+/*
+ * MX31 memory map:
+ *
+ * Virt         Phys            Size    What
+ * ---------------------------------------------------------------------------
+ * F8000000     1FFC0000        16K     IRAM
+ * F9000000     30000000        256M    L2CC
+ * FC000000     43F00000        1M      AIPS 1
+ * FC100000     50000000        1M      SPBA
+ * FC200000     53F00000        1M      AIPS 2
+ * FC500000     60000000        128M    ROMPATCH
+ * FC400000     68000000        128M    AVIC
+ *              70000000        256M    IPU (MAX M2)
+ *              80000000        256M    CSD0 SDRAM/DDR
+ *              90000000        256M    CSD1 SDRAM/DDR
+ *              A0000000        128M    CS0 Flash
+ *              A8000000        128M    CS1 Flash
+ *              B0000000        32M     CS2
+ *              B2000000        32M     CS3
+ * F4000000     B4000000        32M     CS4
+ *              B6000000        32M     CS5
+ * FC320000     B8000000        64K     NAND, SDRAM, WEIM, M3IF, EMI controllers
+ *              C0000000        64M     PCMCIA/CF
+ */
+
+#define CS0_BASE_ADDR           0xA0000000
+#define CS1_BASE_ADDR           0xA8000000
+#define CS2_BASE_ADDR           0xB0000000
+#define CS3_BASE_ADDR           0xB2000000
+
+#define CS4_BASE_ADDR           0xB4000000
+#define CS4_BASE_ADDR_VIRT      0xF4000000
+#define CS4_SIZE                SZ_32M
+
+#define CS5_BASE_ADDR           0xB6000000
+#define PCMCIA_MEM_BASE_ADDR    0xBC000000
+
+/*
+ * IRAM
+ */
+#define IRAM_BASE_ADDR          0x1FFC0000      /* internal ram */
+#define IRAM_BASE_ADDR_VIRT     0xF8000000
+#define IRAM_SIZE               SZ_16K
+
+/*
+ * L2CC
+ */
+#define L2CC_BASE_ADDR          0x30000000
+#define L2CC_BASE_ADDR_VIRT     0xF9000000
+#define L2CC_SIZE               SZ_1M
+
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR         0x43F00000
+#define AIPS1_BASE_ADDR_VIRT    0xFC000000
+#define AIPS1_SIZE              SZ_1M
+
+#define MAX_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00004000)
+#define EVTMON_BASE_ADDR        (AIPS1_BASE_ADDR + 0x00008000)
+#define CLKCTL_BASE_ADDR        (AIPS1_BASE_ADDR + 0x0000C000)
+#define ETB_SLOT4_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00010000)
+#define ETB_SLOT5_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00014000)
+#define ECT_CTIO_BASE_ADDR      (AIPS1_BASE_ADDR + 0x00018000)
+#define I2C_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00080000)
+#define I2C3_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00084000)
+#define OTG_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00088000)
+#define ATA_BASE_ADDR           (AIPS1_BASE_ADDR + 0x0008C000)
+#define UART1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00090000)
+#define UART2_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00094000)
+#define I2C2_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00098000)
+#define OWIRE_BASE_ADDR         (AIPS1_BASE_ADDR + 0x0009C000)
+#define SSI1_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000A0000)
+#define CSPI1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000A4000)
+#define KPP_BASE_ADDR           (AIPS1_BASE_ADDR + 0x000A8000)
+#define IOMUXC_BASE_ADDR        (AIPS1_BASE_ADDR + 0x000AC000)
+#define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B0000)
+#define UART5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B4000)
+#define ECT_IP1_BASE_ADDR       (AIPS1_BASE_ADDR + 0x000B8000)
+#define ECT_IP2_BASE_ADDR       (AIPS1_BASE_ADDR + 0x000BC000)
+
+/*
+ * SPBA global module enabled #0
+ */
+#define SPBA0_BASE_ADDR         0x50000000
+#define SPBA0_BASE_ADDR_VIRT    0xFC100000
+#define SPBA0_SIZE              SZ_1M
+
+#define MMC_SDHC1_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00004000)
+#define MMC_SDHC2_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00008000)
+#define UART3_BASE_ADDR         (SPBA0_BASE_ADDR + 0x0000C000)
+#define CSPI2_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00010000)
+#define SSI2_BASE_ADDR          (SPBA0_BASE_ADDR + 0x00014000)
+#define SIM1_BASE_ADDR          (SPBA0_BASE_ADDR + 0x00018000)
+#define IIM_BASE_ADDR           (SPBA0_BASE_ADDR + 0x0001C000)
+#define ATA_DMA_BASE_ADDR       (SPBA0_BASE_ADDR + 0x00020000)
+#define MSHC1_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00024000)
+#define MSHC2_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00024000)
+#define SPBA_CTRL_BASE_ADDR     (SPBA0_BASE_ADDR + 0x0003C000)
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR         0x53F00000
+#define AIPS2_BASE_ADDR_VIRT    0xFC200000
+#define AIPS2_SIZE              SZ_1M
+#define CCM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x00080000)
+#define CSPI3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00084000)
+#define FIRI_BASE_ADDR          (AIPS2_BASE_ADDR + 0x0008C000)
+#define GPT1_BASE_ADDR          (AIPS2_BASE_ADDR + 0x00090000)
+#define EPIT1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00094000)
+#define EPIT2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00098000)
+#define GPIO3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000A4000)
+#define SCC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AC000)
+#define SCM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AE000)
+#define SMN_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AF000)
+#define RNGA_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000B0000)
+#define IPU_CTRL_BASE_ADDR      (AIPS2_BASE_ADDR + 0x000C0000)
+#define AUDMUX_BASE_ADDR        (AIPS2_BASE_ADDR + 0x000C4000)
+#define MPEG4_ENC_BASE_ADDR     (AIPS2_BASE_ADDR + 0x000C8000)
+#define GPIO1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000CC000)
+#define GPIO2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000D0000)
+#define SDMA_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000D4000)
+#define RTC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000D8000)
+#define WDOG_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000DC000)
+#define PWM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000E0000)
+#define RTIC_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000EC000)
+
+/*
+ * ROMP and AVIC
+ */
+#define ROMP_BASE_ADDR          0x60000000
+#define ROMP_BASE_ADDR_VIRT     0xFC500000
+#define ROMP_SIZE               SZ_1M
+
+#define AVIC_BASE_ADDR          0x68000000
+#define AVIC_BASE_ADDR_VIRT     0xFC400000
+#define AVIC_SIZE               SZ_1M
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define X_MEMC_BASE_ADDR        0xB8000000
+#define X_MEMC_BASE_ADDR_VIRT   0xFC320000
+#define X_MEMC_SIZE             SZ_64K
+
+#define NFC_BASE_ADDR           (X_MEMC_BASE_ADDR + 0x0000)
+#define ESDCTL_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x1000)
+#define WEIM_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x2000)
+#define M3IF_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x3000)
+#define EMI_CTL_BASE_ADDR       (X_MEMC_BASE_ADDR + 0x4000)
+#define PCMCIA_CTL_BASE_ADDR    EMI_CTL_BASE_ADDR
+
+/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE_ADDR       0x70000000
+#define CSD0_BASE_ADDR          0x80000000
+#define CSD1_BASE_ADDR          0x90000000
+#define CS0_BASE_ADDR           0xA0000000
+#define CS1_BASE_ADDR           0xA8000000
+#define CS2_BASE_ADDR           0xB0000000
+#define CS3_BASE_ADDR           0xB2000000
+
+#define CS4_BASE_ADDR           0xB4000000
+#define CS4_BASE_ADDR_VIRT      0xF4000000
+#define CS4_SIZE                SZ_32M
+
+#define CS5_BASE_ADDR           0xB6000000
+#define PCMCIA_MEM_BASE_ADDR    0xBC000000
+
+/*!
+ * This macro defines the physical to virtual address mapping for all the
+ * peripheral modules. It is used by passing in the physical address as x
+ * and returning the virtual address. If the physical address is not mapped,
+ * it returns 0xDEADBEEF
+ */
+#define IO_ADDRESS(x)   \
+        (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
+        ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
+        ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
+        ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
+        ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
+        ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
+        ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
+        ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
+        ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
+        0xDEADBEEF)
+
+/*
+ * define the address mapping macros: in physical address order
+ */
+
+#define IRAM_IO_ADDRESS(x)  \
+        (((x) - IRAM_BASE_ADDR) + IRAM_BASE_ADDR_VIRT)
+
+#define L2CC_IO_ADDRESS(x)  \
+        (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
+
+#define AIPS1_IO_ADDRESS(x)  \
+        (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
+
+#define SPBA0_IO_ADDRESS(x)  \
+        (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
+
+#define AIPS2_IO_ADDRESS(x)  \
+        (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
+
+#define ROMP_IO_ADDRESS(x)  \
+        (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
+
+#define AVIC_IO_ADDRESS(x)  \
+        (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
+
+#define CS4_IO_ADDRESS(x)  \
+        (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
+
+#define X_MEMC_IO_ADDRESS(x)  \
+        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+
+#define PCMCIA_IO_ADDRESS(x) \
+        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+
+/* Start of physical RAM - On many MX31 platforms, this is the first SDRAM bank (CSD0) */
+#define PHYS_OFFSET             CSD0_BASE_ADDR
+
+/*
+ * Interrupt numbers
+ */
+#define MXC_INT_PEN_ADS7843     0
+#define MXC_INT_RESV1           1
+#define MXC_INT_CS8900A         2
+#define MXC_INT_I2C3            3
+#define MXC_INT_I2C2            4
+#define MXC_INT_MPEG4_ENCODER   5
+#define MXC_INT_RTIC            6
+#define MXC_INT_FIRI            7
+#define MXC_INT_MMC_SDHC2       8
+#define MXC_INT_MMC_SDHC1       9
+#define MXC_INT_I2C             10
+#define MXC_INT_SSI2            11
+#define MXC_INT_SSI1            12
+#define MXC_INT_CSPI2           13
+#define MXC_INT_CSPI1           14
+#define MXC_INT_ATA             15
+#define MXC_INT_MBX             16
+#define MXC_INT_CSPI3           17
+#define MXC_INT_UART3           18
+#define MXC_INT_IIM             19
+#define MXC_INT_SIM2            20
+#define MXC_INT_SIM1            21
+#define MXC_INT_RNGA            22
+#define MXC_INT_EVTMON          23
+#define MXC_INT_KPP             24
+#define MXC_INT_RTC             25
+#define MXC_INT_PWM             26
+#define MXC_INT_EPIT2           27
+#define MXC_INT_EPIT1           28
+#define MXC_INT_GPT             29
+#define MXC_INT_RESV30          30
+#define MXC_INT_RESV31          31
+#define MXC_INT_UART2           32
+#define MXC_INT_NANDFC          33
+#define MXC_INT_SDMA            34
+#define MXC_INT_USB1            35
+#define MXC_INT_USB2            36
+#define MXC_INT_USB3            37
+#define MXC_INT_USB4            38
+#define MXC_INT_MSHC1           39
+#define MXC_INT_MSHC2           40
+#define MXC_INT_IPU_ERR         41
+#define MXC_INT_IPU_SYN         42
+#define MXC_INT_RESV43          43
+#define MXC_INT_RESV44          44
+#define MXC_INT_UART1           45
+#define MXC_INT_UART4           46
+#define MXC_INT_UART5           47
+#define MXC_INT_ECT             48
+#define MXC_INT_SCC_SCM         49
+#define MXC_INT_SCC_SMN         50
+#define MXC_INT_GPIO2           51
+#define MXC_INT_GPIO1           52
+#define MXC_INT_CCM             53
+#define MXC_INT_PCMCIA          54
+#define MXC_INT_WDOG            55
+#define MXC_INT_GPIO3           56
+#define MXC_INT_RESV57          57
+#define MXC_INT_EXT_POWER       58
+#define MXC_INT_EXT_TEMPER      59
+#define MXC_INT_EXT_SENSOR60    60
+#define MXC_INT_EXT_SENSOR61    61
+#define MXC_INT_EXT_WDOG        62
+#define MXC_INT_EXT_TV          63
+
+#define MXC_MAX_INT_LINES       64
+
+#define MXC_GPIO_INT_BASE       MXC_MAX_INT_LINES
+#define MXC_MAX_GPIO_LINES      (GPIO_NUM_PIN * GPIO_PORT_NUM)
+#define MXC_MAX_VIRTUAL_INTS    16
+
+#define NR_IRQS (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES + MXC_MAX_VIRTUAL_INTS)
+
+/*!
+ * Number of GPIO port as defined in the IC Spec
+ */
+#define GPIO_PORT_NUM           3
+/*!
+ * Number of GPIO pins per port
+ */
+#define GPIO_NUM_PIN            32
+
+#define PROD_SIGNATURE          0x1     /* For MX31 */
+
+/* silicon revisions specific to i.MX31 */
+#define CHIP_REV_1_0            0x10
+#define CHIP_REV_1_1            0x11
+#define CHIP_REV_1_2            0x12
+#define CHIP_REV_1_3            0x13
+#define CHIP_REV_2_0            0x20
+#define CHIP_REV_2_1            0x21
+#define CHIP_REV_2_2            0x22
+#define CHIP_REV_2_3            0x23
+#define CHIP_REV_3_0            0x30
+#define CHIP_REV_3_1            0x31
+#define CHIP_REV_3_2            0x32
+
+#define SYSTEM_REV_MIN          CHIP_REV_1_0
+#define SYSTEM_REV_NUM          3
+
+/* gpio and gpio based interrupt handling */
+#define GPIO_DR                 0x00
+#define GPIO_GDIR               0x04
+#define GPIO_PSR                0x08
+#define GPIO_ICR1               0x0C
+#define GPIO_ICR2               0x10
+#define GPIO_IMR                0x14
+#define GPIO_ISR                0x18
+#define GPIO_INT_LOW_LEV        0x0
+#define GPIO_INT_HIGH_LEV       0x1
+#define GPIO_INT_RISE_EDGE      0x2
+#define GPIO_INT_FALL_EDGE      0x3
+#define GPIO_INT_NONE           0x4
+
+/* Mandatory defines used globally */
+
+/* this CPU supports up to 96 GPIOs */
+#define ARCH_NR_GPIOS           96
+
+#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
+
+/* this is a i.MX31 CPU */
+#define cpu_is_mx31()           (1)
+
+extern unsigned int system_rev;
+
+static inline int mx31_revision(void)
+{
+        return system_rev;
+}
+#endif
+
+#endif /*  __ASM_ARCH_MXC_MX31_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
new file mode 100644
index 000000000000..332eda4dbd3b
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_H__
+#define __ASM_ARCH_MXC_H__
+
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#error "Do not include directly."
+#endif
+
+/* clean up all things that are not used */
+#ifndef CONFIG_ARCH_MX3
+# define cpu_is_mx31() (0)
+#endif
+
+#ifndef CONFIG_MACH_MX27
+# define cpu_is_mx27() (0)
+#endif
+
+#endif /*  __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc_timer.h b/arch/arm/plat-mxc/include/mach/mxc_timer.h
new file mode 100644
index 000000000000..130aebfbe168
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mxc_timer.h
@@ -0,0 +1,158 @@
+/*
+ * mxc_timer.h
+ *
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __PLAT_MXC_TIMER_H
+#define __PLAT_MXC_TIMER_H
+
+#include <linux/clk.h>
+#include <mach/hardware.h>
+
+#ifdef CONFIG_ARCH_IMX
+#define TIMER_BASE              IO_ADDRESS(TIM1_BASE_ADDR)
+#define TIMER_INTERRUPT         TIM1_INT
+
+#define TCTL_VAL                TCTL_CLK_PCLK1
+#define TCTL_IRQEN              (1<<4)
+#define TCTL_FRR                (1<<8)
+#define TCTL_CLK_PCLK1          (1<<1)
+#define TCTL_CLK_PCLK1_4        (2<<1)
+#define TCTL_CLK_TIN            (3<<1)
+#define TCTL_CLK_32             (4<<1)
+
+#define MXC_TCTL   0x00
+#define MXC_TPRER  0x04
+#define MXC_TCMP   0x08
+#define MXC_TCR    0x0c
+#define MXC_TCN    0x10
+#define MXC_TSTAT  0x14
+#define TSTAT_CAPT              (1<<1)
+#define TSTAT_COMP              (1<<0)
+
+static inline void gpt_irq_disable(void)
+{
+        unsigned int tmp;
+
+        tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
+        __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
+}
+
+static inline void gpt_irq_enable(void)
+{
+        __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
+                                TIMER_BASE + MXC_TCTL);
+}
+
+static void gpt_irq_acknowledge(void)
+{
+        __raw_writel(0, TIMER_BASE + MXC_TSTAT);
+}
+#endif /* CONFIG_ARCH_IMX */
+
+#ifdef CONFIG_ARCH_MX2
+#define TIMER_BASE              IO_ADDRESS(GPT1_BASE_ADDR)
+#define TIMER_INTERRUPT         MXC_INT_GPT1
+
+#define MXC_TCTL   0x00
+#define TCTL_VAL                TCTL_CLK_PCLK1
+#define TCTL_CLK_PCLK1          (1<<1)
+#define TCTL_CLK_PCLK1_4        (2<<1)
+#define TCTL_IRQEN              (1<<4)
+#define TCTL_FRR                (1<<8)
+#define MXC_TPRER  0x04
+#define MXC_TCMP   0x08
+#define MXC_TCR    0x0c
+#define MXC_TCN    0x10
+#define MXC_TSTAT  0x14
+#define TSTAT_CAPT              (1<<1)
+#define TSTAT_COMP              (1<<0)
+
+static inline void gpt_irq_disable(void)
+{
+        unsigned int tmp;
+
+        tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
+        __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
+}
+
+static inline void gpt_irq_enable(void)
+{
+        __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
+                                TIMER_BASE + MXC_TCTL);
+}
+
+static void gpt_irq_acknowledge(void)
+{
+        __raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT);
+}
+#endif /* CONFIG_ARCH_MX2 */
+
+#ifdef CONFIG_ARCH_MX3
+#define TIMER_BASE              IO_ADDRESS(GPT1_BASE_ADDR)
+#define TIMER_INTERRUPT         MXC_INT_GPT
+
+#define MXC_TCTL   0x00
+#define TCTL_VAL                (TCTL_CLK_IPG | TCTL_WAITEN)
+#define TCTL_CLK_IPG            (1<<6)
+#define TCTL_FRR                (1<<9)
+#define TCTL_WAITEN             (1<<3)
+
+#define MXC_TPRER  0x04
+#define MXC_TSTAT  0x08
+#define TSTAT_OF1               (1<<0)
+#define TSTAT_OF2               (1<<1)
+#define TSTAT_OF3               (1<<2)
+#define TSTAT_IF1               (1<<3)
+#define TSTAT_IF2               (1<<4)
+#define TSTAT_ROV               (1<<5)
+#define MXC_IR     0x0c
+#define MXC_TCMP   0x10
+#define MXC_TCMP2  0x14
+#define MXC_TCMP3  0x18
+#define MXC_TCR    0x1c
+#define MXC_TCN    0x24
+
+static inline void gpt_irq_disable(void)
+{
+        __raw_writel(0, TIMER_BASE + MXC_IR);
+}
+
+static inline void gpt_irq_enable(void)
+{
+        __raw_writel(1<<0, TIMER_BASE + MXC_IR);
+}
+
+static inline void gpt_irq_acknowledge(void)
+{
+        __raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT);
+}
+#endif /* CONFIG_ARCH_MX3 */
+
+#define TCTL_SWR                (1<<15)
+#define TCTL_CC                 (1<<10)
+#define TCTL_OM                 (1<<9)
+#define TCTL_CAP_RIS            (1<<6)
+#define TCTL_CAP_FAL            (2<<6)
+#define TCTL_CAP_RIS_FAL        (3<<6)
+#define TCTL_CAP_ENA            (1<<5)
+#define TCTL_TEN                (1<<0)
+
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
new file mode 100644
index 000000000000..bbfc37465fc5
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -0,0 +1,34 @@
+/*
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_MXC_SYSTEM_H__
+#define __ASM_ARCH_MXC_SYSTEM_H__
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        cpu_reset(0);
+}
+
+#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
new file mode 100644
index 000000000000..0b0af0253e91
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -0,0 +1,25 @@
+/*
+ *  Copyright (C) 1999 ARM Limited
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_MXC_TIMEX_H__
+#define __ASM_ARCH_MXC_TIMEX_H__
+
+#include <mach/hardware.h>      /* for CLOCK_TICK_RATE */
+
+#endif                          /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
new file mode 100644
index 000000000000..de6fe0365982
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -0,0 +1,78 @@
+/*
+ *  arch/arm/plat-mxc/include/mach/uncompress.h
+ *
+ *
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
+#define __ASM_ARCH_MXC_UNCOMPRESS_H__
+
+#define __MXC_BOOT_UNCOMPRESS
+
+#include <mach/hardware.h>
+
+#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
+
+#define USR2 0x98
+#define USR2_TXFE (1<<14)
+#define TXR  0x40
+#define UCR1 0x80
+#define UCR1_UARTEN 1
+
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader.  We search for the first enabled
+ * port in the most probable order.  If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ *
+ * This does not append a newline
+ */
+
+static void putc(int ch)
+{
+        static unsigned long serial_port = 0;
+
+        if (unlikely(serial_port == 0)) {
+                do {
+                        serial_port = UART1_BASE_ADDR;
+                        if (UART(UCR1) & UCR1_UARTEN)
+                                break;
+                        serial_port = UART2_BASE_ADDR;
+                        if (UART(UCR1) & UCR1_UARTEN)
+                                break;
+                        return;
+                } while (0);
+        }
+
+        while (!(UART(USR2) & USR2_TXFE))
+                barrier();
+
+        UART(TXR) = ch;
+}
+
+#define flush() do { } while (0)
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
+
+#endif                          /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h
new file mode 100644
index 000000000000..62d97623412f
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/vmalloc.h
@@ -0,0 +1,26 @@
+/*
+ *  Copyright (C) 2000 Russell King.
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_MXC_VMALLOC_H__
+#define __ASM_ARCH_MXC_VMALLOC_H__
+
+/* vmalloc ending address */
+#define VMALLOC_END       0xF4000000
+
+#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */
diff --git a/arch/arm/plat-mxc/iomux-mx1-mx2.c b/arch/arm/plat-mxc/iomux-mx1-mx2.c
index 1204456d61a9..d97387aa9a42 100644
--- a/arch/arm/plat-mxc/iomux-mx1-mx2.c
+++ b/arch/arm/plat-mxc/iomux-mx1-mx2.c
@@ -30,9 +30,9 @@
 #include <linux/string.h>
 #include <linux/gpio.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach/map.h>
-#include <asm/arch/iomux-mx1-mx2.h>
+#include <mach/iomux-mx1-mx2.h>
 
 void mxc_gpio_mode(int gpio_mode)
 {
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 1fbe01da6925..1053b666c676 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -19,7 +19,7 @@
 
 #include <linux/irq.h>
 #include <asm/io.h>
-#include <asm/arch/common.h>
+#include <mach/common.h>
 
 #define AVIC_BASE               IO_ADDRESS(AVIC_BASE_ADDR)
 #define AVIC_INTCNTL            (AVIC_BASE + 0x00)      /* int control reg */
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index be9680a88b02..fd28f5194f71 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -26,10 +26,10 @@
 #include <linux/clockchips.h>
 #include <linux/clk.h>
 
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach/time.h>
-#include <asm/arch/common.h>
-#include <asm/arch/mxc_timer.h>
+#include <mach/common.h>
+#include <mach/mxc_timer.h>
 
 static struct clock_event_device clockevent_mxc;
 static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;