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-rw-r--r--arch/arm/plat-mxc/ehci.c100
-rw-r--r--arch/arm/plat-mxc/gpio.c5
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31moboard.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx3.h17
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx51.h34
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_ehci.h14
-rw-r--r--arch/arm/plat-mxc/time.c46
-rw-r--r--arch/arm/plat-mxc/tzic.c4
8 files changed, 179 insertions, 44 deletions
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index cb0b63874482..2a8646173c2f 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> 2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
3 * 4 *
4 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
@@ -50,7 +51,26 @@
50#define MX35_H1_TLL_BIT (1 << 5) 51#define MX35_H1_TLL_BIT (1 << 5)
51#define MX35_H1_USBTE_BIT (1 << 4) 52#define MX35_H1_USBTE_BIT (1 << 4)
52 53
53int mxc_set_usbcontrol(int port, unsigned int flags) 54#define MXC_OTG_OFFSET 0
55#define MXC_H1_OFFSET 0x200
56
57/* USB_CTRL */
58#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
59#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
60#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
61#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
62#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
63
64/* USB_PHY_CTRL_FUNC */
65#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
66#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
67
68#define MXC_USBCMD_OFFSET 0x140
69
70/* USBCMD */
71#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */
72
73int mxc_initialize_usb_hw(int port, unsigned int flags)
54{ 74{
55 unsigned int v; 75 unsigned int v;
56#ifdef CONFIG_ARCH_MX3 76#ifdef CONFIG_ARCH_MX3
@@ -186,9 +206,85 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
186 return 0; 206 return 0;
187 } 207 }
188#endif /* CONFIG_MACH_MX27 */ 208#endif /* CONFIG_MACH_MX27 */
209#ifdef CONFIG_ARCH_MX51
210 if (cpu_is_mx51()) {
211 void __iomem *usb_base;
212 u32 usbotg_base;
213 u32 usbother_base;
214 int ret = 0;
215
216 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
217
218 switch (port) {
219 case 0: /* OTG port */
220 usbotg_base = usb_base + MXC_OTG_OFFSET;
221 break;
222 case 1: /* Host 1 port */
223 usbotg_base = usb_base + MXC_H1_OFFSET;
224 break;
225 default:
226 printk(KERN_ERR"%s no such port %d\n", __func__, port);
227 ret = -ENOENT;
228 goto error;
229 }
230 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
231
232 switch (port) {
233 case 0: /*OTG port */
234 if (flags & MXC_EHCI_INTERNAL_PHY) {
235 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
236
237 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
238 v |= (MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is not used */
239 else
240 v &= ~(MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is used */
241 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
242
243 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
244 if (flags & MXC_EHCI_WAKEUP_ENABLED)
245 v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
246 else
247 v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
248 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
249 }
250 break;
251 case 1: /* Host 1 */
252 /*Host ULPI */
253 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
254 if (flags & MXC_EHCI_WAKEUP_ENABLED)
255 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */
256 else
257 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */
258
259 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
260 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
261 else
262 v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
263 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
264
265 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
266 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
267 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
268 else
269 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
270 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
271
272 v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
273 if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
274 /* Interrupt Threshold Control:Immediate (no threshold) */
275 v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
276 __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
277 break;
278 }
279
280error:
281 iounmap(usb_base);
282 return ret;
283 }
284#endif
189 printk(KERN_WARNING 285 printk(KERN_WARNING
190 "%s() unable to setup USBCONTROL for this CPU\n", __func__); 286 "%s() unable to setup USBCONTROL for this CPU\n", __func__);
191 return -EINVAL; 287 return -EINVAL;
192} 288}
193EXPORT_SYMBOL(mxc_set_usbcontrol); 289EXPORT_SYMBOL(mxc_initialize_usb_hw);
194 290
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 70b23893f094..71437c61cfd7 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -3,7 +3,7 @@
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 * 4 *
5 * Based on code from Freescale, 5 * Based on code from Freescale,
6 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. 6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License 9 * modify it under the terms of the GNU General Public License
@@ -38,7 +38,6 @@ static int gpio_table_size;
38#define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10) 38#define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10)
39#define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14) 39#define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14)
40#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18) 40#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
41#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
42 41
43#define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0) 42#define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0)
44#define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1) 43#define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1)
@@ -289,7 +288,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
289 /* its a serious configuration bug when it fails */ 288 /* its a serious configuration bug when it fails */
290 BUG_ON( gpiochip_add(&port[i].chip) < 0 ); 289 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
291 290
292 if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25()) { 291 if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) {
293 /* setup one handler for each entry */ 292 /* setup one handler for each entry */
294 set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); 293 set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
295 set_irq_data(port[i].irq, &port[i]); 294 set_irq_data(port[i].irq, &port[i]);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
index fc5fec9b55f0..36ff3cedee1a 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -26,6 +26,7 @@ enum mx31moboard_boards {
26 MX31DEVBOARD = 1, 26 MX31DEVBOARD = 1,
27 MX31MARXBOT = 2, 27 MX31MARXBOT = 2,
28 MX31SMARTBOT = 3, 28 MX31SMARTBOT = 3,
29 MX31EYEBOT = 4,
29}; 30};
30 31
31/* 32/*
@@ -35,7 +36,7 @@ enum mx31moboard_boards {
35 36
36extern void mx31moboard_devboard_init(void); 37extern void mx31moboard_devboard_init(void);
37extern void mx31moboard_marxbot_init(void); 38extern void mx31moboard_marxbot_init(void);
38extern void mx31moboard_smartbot_init(void); 39extern void mx31moboard_smartbot_init(int board);
39 40
40#endif 41#endif
41 42
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index e51465d7b224..cbaed295a2bf 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -719,6 +719,23 @@ enum iomux_pins {
719#define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC) 719#define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC)
720#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC) 720#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC)
721#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC) 721#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC)
722#define MX31_PIN_KEY_ROW0_KEY_ROW0 IOMUX_MODE(MX31_PIN_KEY_ROW0, IOMUX_CONFIG_FUNC)
723#define MX31_PIN_KEY_ROW1_KEY_ROW1 IOMUX_MODE(MX31_PIN_KEY_ROW1, IOMUX_CONFIG_FUNC)
724#define MX31_PIN_KEY_ROW2_KEY_ROW2 IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC)
725#define MX31_PIN_KEY_ROW3_KEY_ROW3 IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC)
726#define MX31_PIN_KEY_ROW4_KEY_ROW4 IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC)
727#define MX31_PIN_KEY_ROW5_KEY_ROW5 IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC)
728#define MX31_PIN_KEY_ROW6_KEY_ROW6 IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC)
729#define MX31_PIN_KEY_ROW7_KEY_ROW7 IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC)
730#define MX31_PIN_KEY_COL0_KEY_COL0 IOMUX_MODE(MX31_PIN_KEY_COL0, IOMUX_CONFIG_FUNC)
731#define MX31_PIN_KEY_COL1_KEY_COL1 IOMUX_MODE(MX31_PIN_KEY_COL1, IOMUX_CONFIG_FUNC)
732#define MX31_PIN_KEY_COL2_KEY_COL2 IOMUX_MODE(MX31_PIN_KEY_COL2, IOMUX_CONFIG_FUNC)
733#define MX31_PIN_KEY_COL3_KEY_COL3 IOMUX_MODE(MX31_PIN_KEY_COL3, IOMUX_CONFIG_FUNC)
734#define MX31_PIN_KEY_COL4_KEY_COL4 IOMUX_MODE(MX31_PIN_KEY_COL4, IOMUX_CONFIG_FUNC)
735#define MX31_PIN_KEY_COL5_KEY_COL5 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC)
736#define MX31_PIN_KEY_COL6_KEY_COL6 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC)
737#define MX31_PIN_KEY_COL7_KEY_COL7 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC)
738
722 739
723/* 740/*
724 * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0, 741 * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0,
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index b4f975e6a665..ab0f95d953d0 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> 2 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
3 * 4 *
4 * The code contained herein is licensed under the GNU General Public 5 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License 6 * License. You may obtain a copy of the GNU General Public License
@@ -37,6 +38,11 @@ typedef enum iomux_config {
37 PAD_CTL_SRE_FAST) 38 PAD_CTL_SRE_FAST)
38#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ 39#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
39 PAD_CTL_SRE_FAST) 40 PAD_CTL_SRE_FAST)
41#define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
42 PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
43 PAD_CTL_PKE | PAD_CTL_HYS)
44#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
45 PAD_CTL_SRE_FAST)
40 46
41/* 47/*
42 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> 48 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
@@ -57,6 +63,7 @@ typedef enum iomux_config {
57#define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) 63#define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL)
58#define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) 64#define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL)
59#define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL) 65#define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL)
66#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_GPIO_PAD_CTRL)
60#define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) 67#define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL)
61#define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) 68#define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL)
62 69
@@ -208,18 +215,19 @@ typedef enum iomux_config {
208#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) 215#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
209#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) 216#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
210#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) 217#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
211#define MX51_PAD_GPIO_1_25__USBH1_CLK IOMUX_PAD(0x678, 0x278, 2, 0x0, 0, NO_PAD_CTRL) 218#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
212#define MX51_PAD_GPIO_1_26__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 2, 0x0, 0, NO_PAD_CTRL) 219#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
213#define MX51_PAD_GPIO_1_27__USBH1_STP IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, NO_PAD_CTRL) 220#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
214#define MX51_PAD_GPIO_1_28__USBH1_NXT IOMUX_PAD(0x684, 0x284, 2, 0x0, 0, NO_PAD_CTRL) 221#define MX51_PAD_USBH1_STP__GPIO_1_27 IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL)
215#define MX51_PAD_GPIO_1_11__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 2, 0x0, 0, NO_PAD_CTRL) 222#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
216#define MX51_PAD_GPIO_1_12__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 2, 0x0, 0, NO_PAD_CTRL) 223#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
217#define MX51_PAD_GPIO_1_13__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 2, 0x0, 0, NO_PAD_CTRL) 224#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
218#define MX51_PAD_GPIO_1_14__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 2, 0x0, 0, NO_PAD_CTRL) 225#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
219#define MX51_PAD_GPIO_1_15__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 2, 0x0, 0, NO_PAD_CTRL) 226#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
220#define MX51_PAD_GPIO_1_16__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 2, 0x0, 0, NO_PAD_CTRL) 227#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
221#define MX51_PAD_GPIO_1_17__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 2, 0x0, 0, NO_PAD_CTRL) 228#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
222#define MX51_PAD_GPIO_1_18__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 2, 0x0, 0, NO_PAD_CTRL) 229#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
230#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
223#define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) 231#define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
224#define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) 232#define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
225#define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) 233#define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
@@ -299,7 +307,7 @@ typedef enum iomux_config {
299#define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) 307#define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
300#define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) 308#define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
301#define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL) 309#define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
302#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, NO_PAD_CTRL) 310#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
303#define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \ 311#define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
304 (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)) 312 (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS))
305#define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) 313#define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
index 4b9b8368c0c0..7fc5f9946199 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
@@ -25,6 +25,18 @@
25#define MXC_EHCI_INTERNAL_PHY (1 << 7) 25#define MXC_EHCI_INTERNAL_PHY (1 << 7)
26#define MXC_EHCI_IPPUE_DOWN (1 << 8) 26#define MXC_EHCI_IPPUE_DOWN (1 << 8)
27#define MXC_EHCI_IPPUE_UP (1 << 9) 27#define MXC_EHCI_IPPUE_UP (1 << 9)
28#define MXC_EHCI_WAKEUP_ENABLED (1 << 10)
29#define MXC_EHCI_ITC_NO_THRESHOLD (1 << 11)
30
31#define MXC_USBCTRL_OFFSET 0
32#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
33#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
34
35#define MX5_USBOTHER_REGS_OFFSET 0x800
36
37/* USB_PHY_CTRL_FUNC2*/
38#define MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK 0x3
39#define MX5_USB_UTMI_PHYCTRL1_PLLDIV_SHIFT 0
28 40
29struct mxc_usbh_platform_data { 41struct mxc_usbh_platform_data {
30 int (*init)(struct platform_device *pdev); 42 int (*init)(struct platform_device *pdev);
@@ -35,7 +47,7 @@ struct mxc_usbh_platform_data {
35 struct otg_transceiver *otg; 47 struct otg_transceiver *otg;
36}; 48};
37 49
38int mxc_set_usbcontrol(int port, unsigned int flags); 50int mxc_initialize_usb_hw(int port, unsigned int flags);
39 51
40#endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */ 52#endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */
41 53
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index c1ce51abdba6..f9a1b059a76c 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -54,14 +54,14 @@
54#define MX2_TSTAT_COMP (1 << 0) 54#define MX2_TSTAT_COMP (1 << 0)
55 55
56/* MX31, MX35, MX25, MXC91231, MX5 */ 56/* MX31, MX35, MX25, MXC91231, MX5 */
57#define MX3_TCTL_WAITEN (1 << 3) /* Wait enable mode */ 57#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
58#define MX3_TCTL_CLK_IPG (1 << 6) 58#define V2_TCTL_CLK_IPG (1 << 6)
59#define MX3_TCTL_FRR (1 << 9) 59#define V2_TCTL_FRR (1 << 9)
60#define MX3_IR 0x0c 60#define V2_IR 0x0c
61#define MX3_TSTAT 0x08 61#define V2_TSTAT 0x08
62#define MX3_TSTAT_OF1 (1 << 0) 62#define V2_TSTAT_OF1 (1 << 0)
63#define MX3_TCN 0x24 63#define V2_TCN 0x24
64#define MX3_TCMP 0x10 64#define V2_TCMP 0x10
65 65
66#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) 66#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
67#define timer_is_v2() (!timer_is_v1()) 67#define timer_is_v2() (!timer_is_v1())
@@ -76,7 +76,7 @@ static inline void gpt_irq_disable(void)
76 unsigned int tmp; 76 unsigned int tmp;
77 77
78 if (timer_is_v2()) 78 if (timer_is_v2())
79 __raw_writel(0, timer_base + MX3_IR); 79 __raw_writel(0, timer_base + V2_IR);
80 else { 80 else {
81 tmp = __raw_readl(timer_base + MXC_TCTL); 81 tmp = __raw_readl(timer_base + MXC_TCTL);
82 __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); 82 __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
@@ -86,7 +86,7 @@ static inline void gpt_irq_disable(void)
86static inline void gpt_irq_enable(void) 86static inline void gpt_irq_enable(void)
87{ 87{
88 if (timer_is_v2()) 88 if (timer_is_v2())
89 __raw_writel(1<<0, timer_base + MX3_IR); 89 __raw_writel(1<<0, timer_base + V2_IR);
90 else { 90 else {
91 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, 91 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
92 timer_base + MXC_TCTL); 92 timer_base + MXC_TCTL);
@@ -102,7 +102,7 @@ static void gpt_irq_acknowledge(void)
102 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, 102 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
103 timer_base + MX1_2_TSTAT); 103 timer_base + MX1_2_TSTAT);
104 } else if (timer_is_v2()) 104 } else if (timer_is_v2())
105 __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT); 105 __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
106} 106}
107 107
108static cycle_t mx1_2_get_cycles(struct clocksource *cs) 108static cycle_t mx1_2_get_cycles(struct clocksource *cs)
@@ -110,9 +110,9 @@ static cycle_t mx1_2_get_cycles(struct clocksource *cs)
110 return __raw_readl(timer_base + MX1_2_TCN); 110 return __raw_readl(timer_base + MX1_2_TCN);
111} 111}
112 112
113static cycle_t mx3_get_cycles(struct clocksource *cs) 113static cycle_t v2_get_cycles(struct clocksource *cs)
114{ 114{
115 return __raw_readl(timer_base + MX3_TCN); 115 return __raw_readl(timer_base + V2_TCN);
116} 116}
117 117
118static struct clocksource clocksource_mxc = { 118static struct clocksource clocksource_mxc = {
@@ -129,7 +129,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
129 unsigned int c = clk_get_rate(timer_clk); 129 unsigned int c = clk_get_rate(timer_clk);
130 130
131 if (timer_is_v2()) 131 if (timer_is_v2())
132 clocksource_mxc.read = mx3_get_cycles; 132 clocksource_mxc.read = v2_get_cycles;
133 133
134 clocksource_mxc.mult = clocksource_hz2mult(c, 134 clocksource_mxc.mult = clocksource_hz2mult(c,
135 clocksource_mxc.shift); 135 clocksource_mxc.shift);
@@ -153,16 +153,16 @@ static int mx1_2_set_next_event(unsigned long evt,
153 -ETIME : 0; 153 -ETIME : 0;
154} 154}
155 155
156static int mx3_set_next_event(unsigned long evt, 156static int v2_set_next_event(unsigned long evt,
157 struct clock_event_device *unused) 157 struct clock_event_device *unused)
158{ 158{
159 unsigned long tcmp; 159 unsigned long tcmp;
160 160
161 tcmp = __raw_readl(timer_base + MX3_TCN) + evt; 161 tcmp = __raw_readl(timer_base + V2_TCN) + evt;
162 162
163 __raw_writel(tcmp, timer_base + MX3_TCMP); 163 __raw_writel(tcmp, timer_base + V2_TCMP);
164 164
165 return (int)(tcmp - __raw_readl(timer_base + MX3_TCN)) < 0 ? 165 return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
166 -ETIME : 0; 166 -ETIME : 0;
167} 167}
168 168
@@ -192,8 +192,8 @@ static void mxc_set_mode(enum clock_event_mode mode,
192 if (mode != clockevent_mode) { 192 if (mode != clockevent_mode) {
193 /* Set event time into far-far future */ 193 /* Set event time into far-far future */
194 if (timer_is_v2()) 194 if (timer_is_v2())
195 __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3, 195 __raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
196 timer_base + MX3_TCMP); 196 timer_base + V2_TCMP);
197 else 197 else
198 __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3, 198 __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
199 timer_base + MX1_2_TCMP); 199 timer_base + MX1_2_TCMP);
@@ -245,7 +245,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
245 uint32_t tstat; 245 uint32_t tstat;
246 246
247 if (timer_is_v2()) 247 if (timer_is_v2())
248 tstat = __raw_readl(timer_base + MX3_TSTAT); 248 tstat = __raw_readl(timer_base + V2_TSTAT);
249 else 249 else
250 tstat = __raw_readl(timer_base + MX1_2_TSTAT); 250 tstat = __raw_readl(timer_base + MX1_2_TSTAT);
251 251
@@ -276,7 +276,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
276 unsigned int c = clk_get_rate(timer_clk); 276 unsigned int c = clk_get_rate(timer_clk);
277 277
278 if (timer_is_v2()) 278 if (timer_is_v2())
279 clockevent_mxc.set_next_event = mx3_set_next_event; 279 clockevent_mxc.set_next_event = v2_set_next_event;
280 280
281 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, 281 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
282 clockevent_mxc.shift); 282 clockevent_mxc.shift);
@@ -308,7 +308,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
308 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ 308 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
309 309
310 if (timer_is_v2()) 310 if (timer_is_v2())
311 tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; 311 tctl_val = V2_TCTL_CLK_IPG | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
312 else 312 else
313 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; 313 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
314 314
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index afa6709db0b3..9b86d2a60d43 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * 3 *
4 * The code contained herein is licensed under the GNU General Public 4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License 5 * License. You may obtain a copy of the GNU General Public License
@@ -19,6 +19,7 @@
19#include <asm/mach/irq.h> 19#include <asm/mach/irq.h>
20 20
21#include <mach/hardware.h> 21#include <mach/hardware.h>
22#include <mach/common.h>
22 23
23/* 24/*
24 ***************************************** 25 *****************************************
@@ -144,6 +145,7 @@ void __init tzic_init_irq(void __iomem *irqbase)
144 set_irq_handler(i, handle_level_irq); 145 set_irq_handler(i, handle_level_irq);
145 set_irq_flags(i, IRQF_VALID); 146 set_irq_flags(i, IRQF_VALID);
146 } 147 }
148 mxc_register_gpios();
147 149
148 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); 150 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
149} 151}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 16:55:04 -0500