aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-mxc
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r--arch/arm/plat-mxc/Makefile2
-rw-r--r--arch/arm/plat-mxc/avic.c12
-rw-r--r--arch/arm/plat-mxc/devices.c25
-rw-r--r--arch/arm/plat-mxc/devices/Makefile1
-rw-r--r--arch/arm/plat-mxc/devices/platform-gpio-mxc.c32
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-dma.c204
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-i2c.c3
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-keypad.c5
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-ssi.c12
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-uart.c2
-rw-r--r--arch/arm/plat-mxc/gpio.c361
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h12
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S10
-rw-r--r--arch/arm/plat-mxc/include/mach/devices-common.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/gpio.h27
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h28
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx53.h14
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v1.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v3.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux.h26
-rw-r--r--arch/arm/plat-mxc/include/mach/mx53.h54
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/sdma.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/timex.h13
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h1
-rw-r--r--arch/arm/plat-mxc/iomux-v1.c34
-rw-r--r--arch/arm/plat-mxc/irq-common.c13
-rw-r--r--arch/arm/plat-mxc/pwm.c8
-rw-r--r--arch/arm/plat-mxc/tzic.c99
29 files changed, 210 insertions, 816 deletions
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index a1387875a491..d53c35fe2ea7 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := clock.o gpio.o time.o devices.o cpu.o system.o irq-common.o 6obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
7 7
8# MX51 uses the TZIC interrupt controller, older platforms use AVIC 8# MX51 uses the TZIC interrupt controller, older platforms use AVIC
9obj-$(CONFIG_MXC_TZIC) += tzic.o 9obj-$(CONFIG_MXC_TZIC) += tzic.o
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 09e2bd0fcdca..55d2534ec727 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -46,6 +46,8 @@
46#define AVIC_FIPNDH 0x60 /* fast int pending high */ 46#define AVIC_FIPNDH 0x60 /* fast int pending high */
47#define AVIC_FIPNDL 0x64 /* fast int pending low */ 47#define AVIC_FIPNDL 0x64 /* fast int pending low */
48 48
49#define AVIC_NUM_IRQS 64
50
49void __iomem *avic_base; 51void __iomem *avic_base;
50 52
51#ifdef CONFIG_MXC_IRQ_PRIOR 53#ifdef CONFIG_MXC_IRQ_PRIOR
@@ -54,7 +56,7 @@ static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
54 unsigned int temp; 56 unsigned int temp;
55 unsigned int mask = 0x0F << irq % 8 * 4; 57 unsigned int mask = 0x0F << irq % 8 * 4;
56 58
57 if (irq >= MXC_INTERNAL_IRQS) 59 if (irq >= AVIC_NUM_IRQS)
58 return -EINVAL;; 60 return -EINVAL;;
59 61
60 temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8)); 62 temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
@@ -72,14 +74,14 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
72{ 74{
73 unsigned int irqt; 75 unsigned int irqt;
74 76
75 if (irq >= MXC_INTERNAL_IRQS) 77 if (irq >= AVIC_NUM_IRQS)
76 return -EINVAL; 78 return -EINVAL;
77 79
78 if (irq < MXC_INTERNAL_IRQS / 2) { 80 if (irq < AVIC_NUM_IRQS / 2) {
79 irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq); 81 irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
80 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL); 82 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
81 } else { 83 } else {
82 irq -= MXC_INTERNAL_IRQS / 2; 84 irq -= AVIC_NUM_IRQS / 2;
83 irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq); 85 irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
84 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH); 86 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
85 } 87 }
@@ -138,7 +140,7 @@ void __init mxc_init_irq(void __iomem *irqbase)
138 /* all IRQ no FIQ */ 140 /* all IRQ no FIQ */
139 __raw_writel(0, avic_base + AVIC_INTTYPEH); 141 __raw_writel(0, avic_base + AVIC_INTTYPEH);
140 __raw_writel(0, avic_base + AVIC_INTTYPEL); 142 __raw_writel(0, avic_base + AVIC_INTTYPEL);
141 for (i = 0; i < MXC_INTERNAL_IRQS; i++) { 143 for (i = 0; i < AVIC_NUM_IRQS; i++) {
142 irq_set_chip_and_handler(i, &mxc_avic_chip.base, 144 irq_set_chip_and_handler(i, &mxc_avic_chip.base,
143 handle_level_irq); 145 handle_level_irq);
144 set_irq_flags(i, IRQF_VALID); 146 set_irq_flags(i, IRQF_VALID);
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index eee1b6096a08..0d6ed31bdbf2 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -89,3 +89,28 @@ err:
89 89
90 return pdev; 90 return pdev;
91} 91}
92
93struct device mxc_aips_bus = {
94 .init_name = "mxc_aips",
95 .parent = &platform_bus,
96};
97
98struct device mxc_ahb_bus = {
99 .init_name = "mxc_ahb",
100 .parent = &platform_bus,
101};
102
103static int __init mxc_device_init(void)
104{
105 int ret;
106
107 ret = device_register(&mxc_aips_bus);
108 if (IS_ERR_VALUE(ret))
109 goto done;
110
111 ret = device_register(&mxc_ahb_bus);
112
113done:
114 return ret;
115}
116core_initcall(mxc_device_init);
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index ad2922acf480..b41bf972b54b 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o
2obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o 2obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
3obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o 3obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o
4obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o 4obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o
5obj-y += platform-gpio-mxc.o
5obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o 6obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
6obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o 7obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
7obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o 8obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
diff --git a/arch/arm/plat-mxc/devices/platform-gpio-mxc.c b/arch/arm/plat-mxc/devices/platform-gpio-mxc.c
new file mode 100644
index 000000000000..cf1b7fdfa20d
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-gpio-mxc.c
@@ -0,0 +1,32 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2011 Linaro Limited
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/devices-common.h>
10
11struct platform_device *__init mxc_register_gpio(int id,
12 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high)
13{
14 struct resource res[] = {
15 {
16 .start = iobase,
17 .end = iobase + iosize - 1,
18 .flags = IORESOURCE_MEM,
19 }, {
20 .start = irq,
21 .end = irq,
22 .flags = IORESOURCE_IRQ,
23 }, {
24 .start = irq_high,
25 .end = irq_high,
26 .flags = IORESOURCE_IRQ,
27 },
28 };
29
30 return platform_device_register_resndata(&mxc_aips_bus,
31 "gpio-mxc", id, res, ARRAY_SIZE(res), NULL, 0);
32}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c
index b130f60ca6b7..2b0fdb23beb8 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-dma.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c
@@ -6,207 +6,29 @@
6 * the terms of the GNU General Public License version 2 as published by the 6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation. 7 * Free Software Foundation.
8 */ 8 */
9#include <linux/compiler.h>
10#include <linux/err.h>
11#include <linux/init.h>
12
13#include <mach/hardware.h>
14#include <mach/devices-common.h> 9#include <mach/devices-common.h>
15#include <mach/sdma.h>
16
17struct imx_imx_sdma_data {
18 resource_size_t iobase;
19 resource_size_t irq;
20 struct sdma_platform_data pdata;
21};
22
23#define imx_imx_sdma_data_entry_single(soc, _sdma_version, _cpu_name, _to_version)\
24 { \
25 .iobase = soc ## _SDMA ## _BASE_ADDR, \
26 .irq = soc ## _INT_SDMA, \
27 .pdata = { \
28 .sdma_version = _sdma_version, \
29 .cpu_name = _cpu_name, \
30 .to_version = _to_version, \
31 }, \
32 }
33
34#ifdef CONFIG_SOC_IMX25
35struct imx_imx_sdma_data imx25_imx_sdma_data __initconst =
36 imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0);
37#endif /* ifdef CONFIG_SOC_IMX25 */
38 10
39#ifdef CONFIG_SOC_IMX31 11struct platform_device __init __maybe_unused *imx_add_imx_dma(void)
40struct imx_imx_sdma_data imx31_imx_sdma_data __initdata = 12{
41 imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0); 13 return platform_device_register_resndata(&mxc_ahb_bus,
42#endif /* ifdef CONFIG_SOC_IMX31 */ 14 "imx-dma", -1, NULL, 0, NULL, 0);
43 15}
44#ifdef CONFIG_SOC_IMX35
45struct imx_imx_sdma_data imx35_imx_sdma_data __initdata =
46 imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0);
47#endif /* ifdef CONFIG_SOC_IMX35 */
48
49#ifdef CONFIG_SOC_IMX51
50struct imx_imx_sdma_data imx51_imx_sdma_data __initconst =
51 imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 0);
52#endif /* ifdef CONFIG_SOC_IMX51 */
53 16
54static struct platform_device __init __maybe_unused *imx_add_imx_sdma( 17struct platform_device __init __maybe_unused *imx_add_imx_sdma(
55 const struct imx_imx_sdma_data *data) 18 resource_size_t iobase, int irq, struct sdma_platform_data *pdata)
56{ 19{
57 struct resource res[] = { 20 struct resource res[] = {
58 { 21 {
59 .start = data->iobase, 22 .start = iobase,
60 .end = data->iobase + SZ_4K - 1, 23 .end = iobase + SZ_16K - 1,
61 .flags = IORESOURCE_MEM, 24 .flags = IORESOURCE_MEM,
62 }, { 25 }, {
63 .start = data->irq, 26 .start = irq,
64 .end = data->irq, 27 .end = irq,
65 .flags = IORESOURCE_IRQ, 28 .flags = IORESOURCE_IRQ,
66 }, 29 },
67 }; 30 };
68 31
69 return imx_add_platform_device("imx-sdma", -1, 32 return platform_device_register_resndata(&mxc_ahb_bus, "imx-sdma",
70 res, ARRAY_SIZE(res), 33 -1, res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
71 &data->pdata, sizeof(data->pdata));
72}
73
74static struct platform_device __init __maybe_unused *imx_add_imx_dma(void)
75{
76 return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0);
77}
78
79#ifdef CONFIG_ARCH_MX25
80static struct sdma_script_start_addrs addr_imx25_to1 = {
81 .ap_2_ap_addr = 729,
82 .uart_2_mcu_addr = 904,
83 .per_2_app_addr = 1255,
84 .mcu_2_app_addr = 834,
85 .uartsh_2_mcu_addr = 1120,
86 .per_2_shp_addr = 1329,
87 .mcu_2_shp_addr = 1048,
88 .ata_2_mcu_addr = 1560,
89 .mcu_2_ata_addr = 1479,
90 .app_2_per_addr = 1189,
91 .app_2_mcu_addr = 770,
92 .shp_2_per_addr = 1407,
93 .shp_2_mcu_addr = 979,
94};
95#endif
96
97#ifdef CONFIG_SOC_IMX31
98static struct sdma_script_start_addrs addr_imx31_to1 = {
99 .per_2_per_addr = 1677,
100};
101
102static struct sdma_script_start_addrs addr_imx31_to2 = {
103 .ap_2_ap_addr = 423,
104 .ap_2_bp_addr = 829,
105 .bp_2_ap_addr = 1029,
106};
107#endif
108
109#ifdef CONFIG_SOC_IMX35
110static struct sdma_script_start_addrs addr_imx35_to1 = {
111 .ap_2_ap_addr = 642,
112 .uart_2_mcu_addr = 817,
113 .mcu_2_app_addr = 747,
114 .uartsh_2_mcu_addr = 1183,
115 .per_2_shp_addr = 1033,
116 .mcu_2_shp_addr = 961,
117 .ata_2_mcu_addr = 1333,
118 .mcu_2_ata_addr = 1252,
119 .app_2_mcu_addr = 683,
120 .shp_2_per_addr = 1111,
121 .shp_2_mcu_addr = 892,
122};
123
124static struct sdma_script_start_addrs addr_imx35_to2 = {
125 .ap_2_ap_addr = 729,
126 .uart_2_mcu_addr = 904,
127 .per_2_app_addr = 1597,
128 .mcu_2_app_addr = 834,
129 .uartsh_2_mcu_addr = 1270,
130 .per_2_shp_addr = 1120,
131 .mcu_2_shp_addr = 1048,
132 .ata_2_mcu_addr = 1429,
133 .mcu_2_ata_addr = 1339,
134 .app_2_per_addr = 1531,
135 .app_2_mcu_addr = 770,
136 .shp_2_per_addr = 1198,
137 .shp_2_mcu_addr = 979,
138};
139#endif
140
141#ifdef CONFIG_SOC_IMX51
142static struct sdma_script_start_addrs addr_imx51 = {
143 .ap_2_ap_addr = 642,
144 .uart_2_mcu_addr = 817,
145 .mcu_2_app_addr = 747,
146 .mcu_2_shp_addr = 961,
147 .ata_2_mcu_addr = 1473,
148 .mcu_2_ata_addr = 1392,
149 .app_2_per_addr = 1033,
150 .app_2_mcu_addr = 683,
151 .shp_2_per_addr = 1251,
152 .shp_2_mcu_addr = 892,
153};
154#endif
155
156static int __init imxXX_add_imx_dma(void)
157{
158 struct platform_device *ret;
159
160#if defined(CONFIG_SOC_IMX21) || defined(CONFIG_SOC_IMX27)
161 if (cpu_is_mx21() || cpu_is_mx27())
162 ret = imx_add_imx_dma();
163 else
164#endif
165
166#if defined(CONFIG_SOC_IMX25)
167 if (cpu_is_mx25()) {
168 imx25_imx_sdma_data.pdata.script_addrs = &addr_imx25_to1;
169 ret = imx_add_imx_sdma(&imx25_imx_sdma_data);
170 } else
171#endif
172
173#if defined(CONFIG_SOC_IMX31)
174 if (cpu_is_mx31()) {
175 int to_version = mx31_revision() >> 4;
176 imx31_imx_sdma_data.pdata.to_version = to_version;
177 if (to_version == 1)
178 imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to1;
179 else
180 imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to2;
181 ret = imx_add_imx_sdma(&imx31_imx_sdma_data);
182 } else
183#endif
184
185#if defined(CONFIG_SOC_IMX35)
186 if (cpu_is_mx35()) {
187 int to_version = mx35_revision() >> 4;
188 imx35_imx_sdma_data.pdata.to_version = to_version;
189 if (to_version == 1)
190 imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to1;
191 else
192 imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to2;
193 ret = imx_add_imx_sdma(&imx35_imx_sdma_data);
194 } else
195#endif
196
197#if defined(CONFIG_SOC_IMX51)
198 if (cpu_is_mx51()) {
199 int to_version = mx51_revision() >> 4;
200 imx51_imx_sdma_data.pdata.to_version = to_version;
201 imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51;
202 ret = imx_add_imx_sdma(&imx51_imx_sdma_data);
203 } else
204#endif
205 ret = ERR_PTR(-ENODEV);
206
207 if (IS_ERR(ret))
208 return PTR_ERR(ret);
209
210 return 0;
211} 34}
212arch_initcall(imxXX_add_imx_dma);
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
index 2ab74f0da9a6..afe60f7244a8 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -94,8 +94,9 @@ const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst = {
94 imx_imx_i2c_data_entry(MX53, _id, _hwid, SZ_4K) 94 imx_imx_i2c_data_entry(MX53, _id, _hwid, SZ_4K)
95 imx53_imx_i2c_data_entry(0, 1), 95 imx53_imx_i2c_data_entry(0, 1),
96 imx53_imx_i2c_data_entry(1, 2), 96 imx53_imx_i2c_data_entry(1, 2),
97 imx53_imx_i2c_data_entry(2, 3),
97}; 98};
98#endif /* ifdef CONFIG_SOC_IMX51 */ 99#endif /* ifdef CONFIG_SOC_IMX53 */
99 100
100struct platform_device *__init imx_add_imx_i2c( 101struct platform_device *__init imx_add_imx_i2c(
101 const struct imx_imx_i2c_data *data, 102 const struct imx_imx_i2c_data *data,
diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c
index 26366114b021..479c3e9f771f 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-keypad.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c
@@ -46,6 +46,11 @@ const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst =
46 imx_imx_keypad_data_entry_single(MX51, SZ_16); 46 imx_imx_keypad_data_entry_single(MX51, SZ_16);
47#endif /* ifdef CONFIG_SOC_IMX51 */ 47#endif /* ifdef CONFIG_SOC_IMX51 */
48 48
49#ifdef CONFIG_SOC_IMX53
50const struct imx_imx_keypad_data imx53_imx_keypad_data __initconst =
51 imx_imx_keypad_data_entry_single(MX53, SZ_16);
52#endif /* ifdef CONFIG_SOC_IMX53 */
53
49struct platform_device *__init imx_add_imx_keypad( 54struct platform_device *__init imx_add_imx_keypad(
50 const struct imx_imx_keypad_data *data, 55 const struct imx_imx_keypad_data *data,
51 const struct matrix_keymap_data *pdata) 56 const struct matrix_keymap_data *pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
index 2569c8d8a2ef..21c6f30e1017 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
@@ -69,13 +69,23 @@ const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = {
69#ifdef CONFIG_SOC_IMX51 69#ifdef CONFIG_SOC_IMX51
70const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { 70const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = {
71#define imx51_imx_ssi_data_entry(_id, _hwid) \ 71#define imx51_imx_ssi_data_entry(_id, _hwid) \
72 imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K) 72 imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_16K)
73 imx51_imx_ssi_data_entry(0, 1), 73 imx51_imx_ssi_data_entry(0, 1),
74 imx51_imx_ssi_data_entry(1, 2), 74 imx51_imx_ssi_data_entry(1, 2),
75 imx51_imx_ssi_data_entry(2, 3), 75 imx51_imx_ssi_data_entry(2, 3),
76}; 76};
77#endif /* ifdef CONFIG_SOC_IMX51 */ 77#endif /* ifdef CONFIG_SOC_IMX51 */
78 78
79#ifdef CONFIG_SOC_IMX53
80const struct imx_imx_ssi_data imx53_imx_ssi_data[] __initconst = {
81#define imx53_imx_ssi_data_entry(_id, _hwid) \
82 imx_imx_ssi_data_entry(MX53, _id, _hwid, SZ_16K)
83 imx53_imx_ssi_data_entry(0, 1),
84 imx53_imx_ssi_data_entry(1, 2),
85 imx53_imx_ssi_data_entry(2, 3),
86};
87#endif /* ifdef CONFIG_SOC_IMX53 */
88
79struct platform_device *__init imx_add_imx_ssi( 89struct platform_device *__init imx_add_imx_ssi(
80 const struct imx_imx_ssi_data *data, 90 const struct imx_imx_ssi_data *data,
81 const struct imx_ssi_platform_data *pdata) 91 const struct imx_ssi_platform_data *pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c
index 3c854c2cc6dd..cfce8c918b73 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-uart.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c
@@ -123,6 +123,8 @@ const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst = {
123 imx53_imx_uart_data_entry(0, 1), 123 imx53_imx_uart_data_entry(0, 1),
124 imx53_imx_uart_data_entry(1, 2), 124 imx53_imx_uart_data_entry(1, 2),
125 imx53_imx_uart_data_entry(2, 3), 125 imx53_imx_uart_data_entry(2, 3),
126 imx53_imx_uart_data_entry(3, 4),
127 imx53_imx_uart_data_entry(4, 5),
126}; 128};
127#endif /* ifdef CONFIG_SOC_IMX53 */ 129#endif /* ifdef CONFIG_SOC_IMX53 */
128 130
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
deleted file mode 100644
index 6cd6d7f686f6..000000000000
--- a/arch/arm/plat-mxc/gpio.c
+++ /dev/null
@@ -1,361 +0,0 @@
1/*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 */
21
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/io.h>
25#include <linux/irq.h>
26#include <linux/gpio.h>
27#include <mach/hardware.h>
28#include <asm-generic/bug.h>
29
30static struct mxc_gpio_port *mxc_gpio_ports;
31static int gpio_table_size;
32
33#define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2())
34
35#define GPIO_DR (cpu_is_mx1_mx2() ? 0x1c : 0x00)
36#define GPIO_GDIR (cpu_is_mx1_mx2() ? 0x00 : 0x04)
37#define GPIO_PSR (cpu_is_mx1_mx2() ? 0x24 : 0x08)
38#define GPIO_ICR1 (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
39#define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10)
40#define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14)
41#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
42
43#define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0)
44#define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1)
45#define GPIO_INT_RISE_EDGE (cpu_is_mx1_mx2() ? 0x0 : 0x2)
46#define GPIO_INT_FALL_EDGE (cpu_is_mx1_mx2() ? 0x1 : 0x3)
47#define GPIO_INT_NONE 0x4
48
49/* Note: This driver assumes 32 GPIOs are handled in one register */
50
51static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
52{
53 __raw_writel(1 << index, port->base + GPIO_ISR);
54}
55
56static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
57 int enable)
58{
59 u32 l;
60
61 l = __raw_readl(port->base + GPIO_IMR);
62 l = (l & (~(1 << index))) | (!!enable << index);
63 __raw_writel(l, port->base + GPIO_IMR);
64}
65
66static void gpio_ack_irq(struct irq_data *d)
67{
68 u32 gpio = irq_to_gpio(d->irq);
69 _clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f);
70}
71
72static void gpio_mask_irq(struct irq_data *d)
73{
74 u32 gpio = irq_to_gpio(d->irq);
75 _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0);
76}
77
78static void gpio_unmask_irq(struct irq_data *d)
79{
80 u32 gpio = irq_to_gpio(d->irq);
81 _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
82}
83
84static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset);
85
86static int gpio_set_irq_type(struct irq_data *d, u32 type)
87{
88 u32 gpio = irq_to_gpio(d->irq);
89 struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
90 u32 bit, val;
91 int edge;
92 void __iomem *reg = port->base;
93
94 port->both_edges &= ~(1 << (gpio & 31));
95 switch (type) {
96 case IRQ_TYPE_EDGE_RISING:
97 edge = GPIO_INT_RISE_EDGE;
98 break;
99 case IRQ_TYPE_EDGE_FALLING:
100 edge = GPIO_INT_FALL_EDGE;
101 break;
102 case IRQ_TYPE_EDGE_BOTH:
103 val = mxc_gpio_get(&port->chip, gpio & 31);
104 if (val) {
105 edge = GPIO_INT_LOW_LEV;
106 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
107 } else {
108 edge = GPIO_INT_HIGH_LEV;
109 pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
110 }
111 port->both_edges |= 1 << (gpio & 31);
112 break;
113 case IRQ_TYPE_LEVEL_LOW:
114 edge = GPIO_INT_LOW_LEV;
115 break;
116 case IRQ_TYPE_LEVEL_HIGH:
117 edge = GPIO_INT_HIGH_LEV;
118 break;
119 default:
120 return -EINVAL;
121 }
122
123 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
124 bit = gpio & 0xf;
125 val = __raw_readl(reg) & ~(0x3 << (bit << 1));
126 __raw_writel(val | (edge << (bit << 1)), reg);
127 _clear_gpio_irqstatus(port, gpio & 0x1f);
128
129 return 0;
130}
131
132static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
133{
134 void __iomem *reg = port->base;
135 u32 bit, val;
136 int edge;
137
138 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
139 bit = gpio & 0xf;
140 val = __raw_readl(reg);
141 edge = (val >> (bit << 1)) & 3;
142 val &= ~(0x3 << (bit << 1));
143 if (edge == GPIO_INT_HIGH_LEV) {
144 edge = GPIO_INT_LOW_LEV;
145 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
146 } else if (edge == GPIO_INT_LOW_LEV) {
147 edge = GPIO_INT_HIGH_LEV;
148 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
149 } else {
150 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
151 gpio, edge);
152 return;
153 }
154 __raw_writel(val | (edge << (bit << 1)), reg);
155}
156
157/* handle 32 interrupts in one status register */
158static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
159{
160 u32 gpio_irq_no_base = port->virtual_irq_start;
161
162 while (irq_stat != 0) {
163 int irqoffset = fls(irq_stat) - 1;
164
165 if (port->both_edges & (1 << irqoffset))
166 mxc_flip_edge(port, irqoffset);
167
168 generic_handle_irq(gpio_irq_no_base + irqoffset);
169
170 irq_stat &= ~(1 << irqoffset);
171 }
172}
173
174/* MX1 and MX3 has one interrupt *per* gpio port */
175static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
176{
177 u32 irq_stat;
178 struct mxc_gpio_port *port = irq_get_handler_data(irq);
179
180 irq_stat = __raw_readl(port->base + GPIO_ISR) &
181 __raw_readl(port->base + GPIO_IMR);
182
183 mxc_gpio_irq_handler(port, irq_stat);
184}
185
186/* MX2 has one interrupt *for all* gpio ports */
187static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
188{
189 int i;
190 u32 irq_msk, irq_stat;
191 struct mxc_gpio_port *port = irq_get_handler_data(irq);
192
193 /* walk through all interrupt status registers */
194 for (i = 0; i < gpio_table_size; i++) {
195 irq_msk = __raw_readl(port[i].base + GPIO_IMR);
196 if (!irq_msk)
197 continue;
198
199 irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk;
200 if (irq_stat)
201 mxc_gpio_irq_handler(&port[i], irq_stat);
202 }
203}
204
205/*
206 * Set interrupt number "irq" in the GPIO as a wake-up source.
207 * While system is running, all registered GPIO interrupts need to have
208 * wake-up enabled. When system is suspended, only selected GPIO interrupts
209 * need to have wake-up enabled.
210 * @param irq interrupt source number
211 * @param enable enable as wake-up if equal to non-zero
212 * @return This function returns 0 on success.
213 */
214static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
215{
216 u32 gpio = irq_to_gpio(d->irq);
217 u32 gpio_idx = gpio & 0x1F;
218 struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
219
220 if (enable) {
221 if (port->irq_high && (gpio_idx >= 16))
222 enable_irq_wake(port->irq_high);
223 else
224 enable_irq_wake(port->irq);
225 } else {
226 if (port->irq_high && (gpio_idx >= 16))
227 disable_irq_wake(port->irq_high);
228 else
229 disable_irq_wake(port->irq);
230 }
231
232 return 0;
233}
234
235static struct irq_chip gpio_irq_chip = {
236 .name = "GPIO",
237 .irq_ack = gpio_ack_irq,
238 .irq_mask = gpio_mask_irq,
239 .irq_unmask = gpio_unmask_irq,
240 .irq_set_type = gpio_set_irq_type,
241 .irq_set_wake = gpio_set_wake_irq,
242};
243
244static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
245 int dir)
246{
247 struct mxc_gpio_port *port =
248 container_of(chip, struct mxc_gpio_port, chip);
249 u32 l;
250 unsigned long flags;
251
252 spin_lock_irqsave(&port->lock, flags);
253 l = __raw_readl(port->base + GPIO_GDIR);
254 if (dir)
255 l |= 1 << offset;
256 else
257 l &= ~(1 << offset);
258 __raw_writel(l, port->base + GPIO_GDIR);
259 spin_unlock_irqrestore(&port->lock, flags);
260}
261
262static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
263{
264 struct mxc_gpio_port *port =
265 container_of(chip, struct mxc_gpio_port, chip);
266 void __iomem *reg = port->base + GPIO_DR;
267 u32 l;
268 unsigned long flags;
269
270 spin_lock_irqsave(&port->lock, flags);
271 l = (__raw_readl(reg) & (~(1 << offset))) | (!!value << offset);
272 __raw_writel(l, reg);
273 spin_unlock_irqrestore(&port->lock, flags);
274}
275
276static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
277{
278 struct mxc_gpio_port *port =
279 container_of(chip, struct mxc_gpio_port, chip);
280
281 return (__raw_readl(port->base + GPIO_PSR) >> offset) & 1;
282}
283
284static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
285{
286 _set_gpio_direction(chip, offset, 0);
287 return 0;
288}
289
290static int mxc_gpio_direction_output(struct gpio_chip *chip,
291 unsigned offset, int value)
292{
293 mxc_gpio_set(chip, offset, value);
294 _set_gpio_direction(chip, offset, 1);
295 return 0;
296}
297
298/*
299 * This lock class tells lockdep that GPIO irqs are in a different
300 * category than their parents, so it won't report false recursion.
301 */
302static struct lock_class_key gpio_lock_class;
303
304int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
305{
306 int i, j;
307
308 /* save for local usage */
309 mxc_gpio_ports = port;
310 gpio_table_size = cnt;
311
312 printk(KERN_INFO "MXC GPIO hardware\n");
313
314 for (i = 0; i < cnt; i++) {
315 /* disable the interrupt and clear the status */
316 __raw_writel(0, port[i].base + GPIO_IMR);
317 __raw_writel(~0, port[i].base + GPIO_ISR);
318 for (j = port[i].virtual_irq_start;
319 j < port[i].virtual_irq_start + 32; j++) {
320 irq_set_lockdep_class(j, &gpio_lock_class);
321 irq_set_chip_and_handler(j, &gpio_irq_chip,
322 handle_level_irq);
323 set_irq_flags(j, IRQF_VALID);
324 }
325
326 /* register gpio chip */
327 port[i].chip.direction_input = mxc_gpio_direction_input;
328 port[i].chip.direction_output = mxc_gpio_direction_output;
329 port[i].chip.get = mxc_gpio_get;
330 port[i].chip.set = mxc_gpio_set;
331 port[i].chip.base = i * 32;
332 port[i].chip.ngpio = 32;
333
334 spin_lock_init(&port[i].lock);
335
336 /* its a serious configuration bug when it fails */
337 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
338
339 if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) {
340 /* setup one handler for each entry */
341 irq_set_chained_handler(port[i].irq,
342 mx3_gpio_irq_handler);
343 irq_set_handler_data(port[i].irq, &port[i]);
344 if (port[i].irq_high) {
345 /* setup handler for GPIO 16 to 31 */
346 irq_set_chained_handler(port[i].irq_high,
347 mx3_gpio_irq_handler);
348 irq_set_handler_data(port[i].irq_high,
349 &port[i]);
350 }
351 }
352 }
353
354 if (cpu_is_mx2()) {
355 /* setup one handler for all GPIO interrupts */
356 irq_set_chained_handler(port[0].irq, mx2_gpio_irq_handler);
357 irq_set_handler_data(port[0].irq, port);
358 }
359
360 return 0;
361}
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index da7991832af6..91fa2632aa5e 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -43,6 +43,15 @@ extern void mx35_init_irq(void);
43extern void mx50_init_irq(void); 43extern void mx50_init_irq(void);
44extern void mx51_init_irq(void); 44extern void mx51_init_irq(void);
45extern void mx53_init_irq(void); 45extern void mx53_init_irq(void);
46extern void imx1_soc_init(void);
47extern void imx21_soc_init(void);
48extern void imx25_soc_init(void);
49extern void imx27_soc_init(void);
50extern void imx31_soc_init(void);
51extern void imx35_soc_init(void);
52extern void imx50_soc_init(void);
53extern void imx51_soc_init(void);
54extern void imx53_soc_init(void);
46extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); 55extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
47extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); 56extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
48extern int mx1_clocks_init(unsigned long fref); 57extern int mx1_clocks_init(unsigned long fref);
@@ -55,7 +64,8 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
55 unsigned long ckih1, unsigned long ckih2); 64 unsigned long ckih1, unsigned long ckih2);
56extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, 65extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
57 unsigned long ckih1, unsigned long ckih2); 66 unsigned long ckih1, unsigned long ckih2);
58extern int mxc_register_gpios(void); 67extern struct platform_device *mxc_register_gpio(int id,
68 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
59extern int mxc_register_device(struct platform_device *pdev, void *data); 69extern int mxc_register_device(struct platform_device *pdev, void *data);
60extern void mxc_set_cpu_type(unsigned int type); 70extern void mxc_set_cpu_type(unsigned int type);
61extern void mxc_arch_reset_init(void __iomem *); 71extern void mxc_arch_reset_init(void __iomem *);
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 8e8d175e5077..91fc7cdb5dc9 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -12,32 +12,32 @@
12 */ 12 */
13#include <mach/hardware.h> 13#include <mach/hardware.h>
14 14
15#ifdef CONFIG_ARCH_MX1 15#ifdef CONFIG_SOC_IMX1
16#define UART_PADDR MX1_UART1_BASE_ADDR 16#define UART_PADDR MX1_UART1_BASE_ADDR
17#endif 17#endif
18 18
19#ifdef CONFIG_ARCH_MX25 19#ifdef CONFIG_SOC_IMX25
20#ifdef UART_PADDR 20#ifdef UART_PADDR
21#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 21#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
22#endif 22#endif
23#define UART_PADDR MX25_UART1_BASE_ADDR 23#define UART_PADDR MX25_UART1_BASE_ADDR
24#endif 24#endif
25 25
26#ifdef CONFIG_ARCH_MX2 26#if defined(CONFIG_SOC_IMX21) || defined (CONFIG_SOC_IMX27)
27#ifdef UART_PADDR 27#ifdef UART_PADDR
28#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 28#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
29#endif 29#endif
30#define UART_PADDR MX2x_UART1_BASE_ADDR 30#define UART_PADDR MX2x_UART1_BASE_ADDR
31#endif 31#endif
32 32
33#ifdef CONFIG_ARCH_MX3 33#if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35)
34#ifdef UART_PADDR 34#ifdef UART_PADDR
35#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 35#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
36#endif 36#endif
37#define UART_PADDR MX3x_UART1_BASE_ADDR 37#define UART_PADDR MX3x_UART1_BASE_ADDR
38#endif 38#endif
39 39
40#ifdef CONFIG_ARCH_MX5 40#ifdef CONFIG_SOC_IMX51
41#ifdef UART_PADDR 41#ifdef UART_PADDR
42#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 42#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
43#endif 43#endif
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index fa8477337f91..bf93820ab61c 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -9,6 +9,10 @@
9#include <linux/kernel.h> 9#include <linux/kernel.h>
10#include <linux/platform_device.h> 10#include <linux/platform_device.h>
11#include <linux/init.h> 11#include <linux/init.h>
12#include <mach/sdma.h>
13
14extern struct device mxc_aips_bus;
15extern struct device mxc_ahb_bus;
12 16
13struct platform_device *imx_add_platform_device_dmamask( 17struct platform_device *imx_add_platform_device_dmamask(
14 const char *name, int id, 18 const char *name, int id,
@@ -291,3 +295,7 @@ struct imx_spi_imx_data {
291struct platform_device *__init imx_add_spi_imx( 295struct platform_device *__init imx_add_spi_imx(
292 const struct imx_spi_imx_data *data, 296 const struct imx_spi_imx_data *data,
293 const struct spi_imx_master *pdata); 297 const struct spi_imx_master *pdata);
298
299struct platform_device *imx_add_imx_dma(void);
300struct platform_device *imx_add_imx_sdma(
301 resource_size_t iobase, int irq, struct sdma_platform_data *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
index a2747f12813e..31c820c1b796 100644
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -36,31 +36,4 @@
36#define gpio_to_irq(gpio) (MXC_GPIO_IRQ_START + (gpio)) 36#define gpio_to_irq(gpio) (MXC_GPIO_IRQ_START + (gpio))
37#define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START) 37#define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START)
38 38
39struct mxc_gpio_port {
40 void __iomem *base;
41 int irq;
42 int irq_high;
43 int virtual_irq_start;
44 struct gpio_chip chip;
45 u32 both_edges;
46 spinlock_t lock;
47};
48
49#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \
50 { \
51 .chip.label = "gpio-" #_id, \
52 .irq = _irq, \
53 .irq_high = _irq_high, \
54 .base = soc ## _IO_ADDRESS( \
55 soc ## _GPIO ## _hwid ## _BASE_ADDR), \
56 .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \
57 }
58
59#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \
60 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0)
61#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \
62 DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0)
63
64int mxc_gpio_init(struct mxc_gpio_port*, int);
65
66#endif 39#endif
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 67d3e2bed065..a8bfd565dcad 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -97,35 +97,17 @@
97 97
98#include <mach/mxc.h> 98#include <mach/mxc.h>
99 99
100#ifdef CONFIG_ARCH_MX5
101#include <mach/mx50.h> 100#include <mach/mx50.h>
102#include <mach/mx51.h> 101#include <mach/mx51.h>
103#include <mach/mx53.h> 102#include <mach/mx53.h>
104#endif
105
106#ifdef CONFIG_ARCH_MX3
107#include <mach/mx3x.h> 103#include <mach/mx3x.h>
108#include <mach/mx31.h> 104#include <mach/mx31.h>
109#include <mach/mx35.h> 105#include <mach/mx35.h>
110#endif 106#include <mach/mx2x.h>
111 107#include <mach/mx21.h>
112#ifdef CONFIG_ARCH_MX2 108#include <mach/mx27.h>
113# include <mach/mx2x.h> 109#include <mach/mx1.h>
114# ifdef CONFIG_MACH_MX21 110#include <mach/mx25.h>
115# include <mach/mx21.h>
116# endif
117# ifdef CONFIG_MACH_MX27
118# include <mach/mx27.h>
119# endif
120#endif
121
122#ifdef CONFIG_ARCH_MX1
123# include <mach/mx1.h>
124#endif
125
126#ifdef CONFIG_ARCH_MX25
127# include <mach/mx25.h>
128#endif
129 111
130#define imx_map_entry(soc, name, _type) { \ 112#define imx_map_entry(soc, name, _type) { \
131 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ 113 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
index e95d9cb8aeb7..e11dd5f09c34 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
@@ -39,7 +39,7 @@
39#define _MX53_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x348, 0x20, 5, 0x0, 0, 0) 39#define _MX53_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x348, 0x20, 5, 0x0, 0, 0)
40#define _MX53_PAD_GPIO_19__FEC_TDATA_3 IOMUX_PAD(0x348, 0x20, 6, 0x0, 0, 0) 40#define _MX53_PAD_GPIO_19__FEC_TDATA_3 IOMUX_PAD(0x348, 0x20, 6, 0x0, 0, 0)
41#define _MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x20,7, 0x0, 0, 0) 41#define _MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x20,7, 0x0, 0, 0)
42#define _MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x24, o, 0x0, 0, 0) 42#define _MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x24, 0, 0x0, 0, 0)
43#define _MX53_PAD_KEY_COL0__GPIO4_6 IOMUX_PAD(0x34C, 0x24, 1, 0x0, 0, 0) 43#define _MX53_PAD_KEY_COL0__GPIO4_6 IOMUX_PAD(0x34C, 0x24, 1, 0x0, 0, 0)
44#define _MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x34C, 0x24, 2, 0x758, 0, 0) 44#define _MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x34C, 0x24, 2, 0x758, 0, 0)
45#define _MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x24, 4, 0x890, 0, 0) 45#define _MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x24, 4, 0x890, 0, 0)
@@ -697,7 +697,7 @@
697#define _MX53_PAD_EIM_DA5__GPIO3_5 IOMUX_PAD(0x500, 0x1B0, 1, 0x0, 0, 0) 697#define _MX53_PAD_EIM_DA5__GPIO3_5 IOMUX_PAD(0x500, 0x1B0, 1, 0x0, 0, 0)
698#define _MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 IOMUX_PAD(0x500, 0x1B0, 3, 0x0, 0, 0) 698#define _MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 IOMUX_PAD(0x500, 0x1B0, 3, 0x0, 0, 0)
699#define _MX53_PAD_EIM_DA5__IPU_CSI1_D_4 IOMUX_PAD(0x500, 0x1B0, 4, 0x0, 0, 0) 699#define _MX53_PAD_EIM_DA5__IPU_CSI1_D_4 IOMUX_PAD(0x500, 0x1B0, 4, 0x0, 0, 0)
700#define _MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 17, 0x0, 0, 0) 700#define _MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, 0x0, 0, 0)
701#define _MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 IOMUX_PAD(0x504, 0x1B4, 0, 0x0, 0, 0) 701#define _MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 IOMUX_PAD(0x504, 0x1B4, 0, 0x0, 0, 0)
702#define _MX53_PAD_EIM_DA6__GPIO3_6 IOMUX_PAD(0x504, 0x1B4, 1, 0x0, 0, 0) 702#define _MX53_PAD_EIM_DA6__GPIO3_6 IOMUX_PAD(0x504, 0x1B4, 1, 0x0, 0, 0)
703#define _MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 IOMUX_PAD(0x504, 0x1B4, 3, 0x0, 0, 0) 703#define _MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 IOMUX_PAD(0x504, 0x1B4, 3, 0x0, 0, 0)
@@ -958,12 +958,12 @@
958#define _MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, 0x0, 0, 0) 958#define _MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, 0x0, 0, 0)
959#define _MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, 0x0, 0, 0) 959#define _MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, 0x0, 0, 0)
960#define _MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, 0x0, 0, 0) 960#define _MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, 0x0, 0, 0)
961#define _MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) 961#define _MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 0, 0x0, 0, 0)
962#define _MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) 962#define _MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
963#define _MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) 963#define _MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 3, 0x0, 0, 0)
964#define _MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) 964#define _MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 4, 0x0, 0, 0)
965#define _MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) 965#define _MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 5, 0x0, 0, 0)
966#define _MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) 966#define _MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 6, 0x0, 0, 0)
967#define _MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, 0x0, 0, 0) 967#define _MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, 0x0, 0, 0)
968#define _MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, 0) 968#define _MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, 0)
969#define _MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, 0x0, 0, 0) 969#define _MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, 0x0, 0, 0)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h
index c07d30210c57..6fa8a707b9a0 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v1.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h
@@ -85,9 +85,6 @@
85#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) 85#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
86#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) 86#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
87 87
88/* decode irq number to use with IMR(x), ISR(x) and friends */
89#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
90
91#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x) 88#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
92#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) 89#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
93#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) 90#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
@@ -98,7 +95,6 @@
98extern int mxc_gpio_mode(int gpio_mode); 95extern int mxc_gpio_mode(int gpio_mode);
99extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, 96extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
100 const char *label); 97 const char *label);
101extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
102 98
103extern int __init imx_iomuxv1_init(void __iomem *base, int numports); 99extern int __init imx_iomuxv1_init(void __iomem *base, int numports);
104 100
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 82620af1922f..ebbce33097a7 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -66,7 +66,6 @@ typedef u64 iomux_v3_cfg_t;
66#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT) 66#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
67#define MUX_PAD_CTRL_SHIFT 41 67#define MUX_PAD_CTRL_SHIFT 41
68#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT) 68#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT)
69#define NO_PAD_CTRL ((iomux_v3_cfg_t)1 << (MUX_PAD_CTRL_SHIFT + 16))
70#define MUX_SEL_INPUT_SHIFT 58 69#define MUX_SEL_INPUT_SHIFT 58
71#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) 70#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
72 71
@@ -85,6 +84,7 @@ typedef u64 iomux_v3_cfg_t;
85 * Use to set PAD control 84 * Use to set PAD control
86 */ 85 */
87 86
87#define NO_PAD_CTRL (1 << 16)
88#define PAD_CTL_DVS (1 << 13) 88#define PAD_CTL_DVS (1 << 13)
89#define PAD_CTL_HYS (1 << 8) 89#define PAD_CTL_HYS (1 << 8)
90 90
diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h
deleted file mode 100644
index 3d226d7e7be2..000000000000
--- a/arch/arm/plat-mxc/include/mach/iomux.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (C) 2010 Uwe Kleine-Koenig, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
7 */
8#ifndef __MACH_IOMUX_H__
9#define __MACH_IOMUX_H__
10
11/* This file will go away, please include mach/iomux-mx... directly */
12
13#ifdef CONFIG_ARCH_MX1
14#include <mach/iomux-mx1.h>
15#endif
16#ifdef CONFIG_ARCH_MX2
17#include <mach/iomux-mx2x.h>
18#ifdef CONFIG_MACH_MX21
19#include <mach/iomux-mx21.h>
20#endif
21#ifdef CONFIG_MACH_MX27
22#include <mach/iomux-mx27.h>
23#endif
24#endif
25
26#endif /* __MACH_IOMUX_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index 9d2a1ef84de2..5e3c3236ebf3 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -145,14 +145,14 @@
145/* 145/*
146 * Memory regions and CS 146 * Memory regions and CS
147 */ 147 */
148#define MX53_CSD0_BASE_ADDR 0x90000000 148#define MX53_CSD0_BASE_ADDR 0x70000000
149#define MX53_CSD1_BASE_ADDR 0xA0000000 149#define MX53_CSD1_BASE_ADDR 0xB0000000
150#define MX53_CS0_BASE_ADDR 0xB0000000 150#define MX53_CS0_BASE_ADDR 0xF0000000
151#define MX53_CS1_BASE_ADDR 0xB8000000 151#define MX53_CS1_32MB_BASE_ADDR 0xF2000000
152#define MX53_CS2_BASE_ADDR 0xC0000000 152#define MX53_CS1_64MB_BASE_ADDR 0xF4000000
153#define MX53_CS3_BASE_ADDR 0xC8000000 153#define MX53_CS2_64MB_BASE_ADDR 0xF4000000
154#define MX53_CS4_BASE_ADDR 0xCC000000 154#define MX53_CS2_96MB_BASE_ADDR 0xF6000000
155#define MX53_CS5_BASE_ADDR 0xCE000000 155#define MX53_CS3_BASE_ADDR 0xF6000000
156 156
157#define MX53_IO_P2V(x) IMX_IO_P2V(x) 157#define MX53_IO_P2V(x) IMX_IO_P2V(x)
158#define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x)) 158#define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x))
@@ -176,10 +176,10 @@
176/* 176/*
177 * DMA request assignments 177 * DMA request assignments
178 */ 178 */
179#define MX53_DMA_REQ_SSI3_TX1 47 179#define MX53_DMA_REQ_SSI3_TX0 47
180#define MX53_DMA_REQ_SSI3_RX1 46 180#define MX53_DMA_REQ_SSI3_RX0 46
181#define MX53_DMA_REQ_SSI3_TX2 45 181#define MX53_DMA_REQ_SSI3_TX1 45
182#define MX53_DMA_REQ_SSI3_RX2 44 182#define MX53_DMA_REQ_SSI3_RX1 44
183#define MX53_DMA_REQ_UART3_TX 43 183#define MX53_DMA_REQ_UART3_TX 43
184#define MX53_DMA_REQ_UART3_RX 42 184#define MX53_DMA_REQ_UART3_RX 42
185#define MX53_DMA_REQ_ESAI_TX 41 185#define MX53_DMA_REQ_ESAI_TX 41
@@ -194,14 +194,14 @@
194#define MX53_DMA_REQ_ASRC_DMA1 32 194#define MX53_DMA_REQ_ASRC_DMA1 32
195#define MX53_DMA_REQ_EMI_WR 31 195#define MX53_DMA_REQ_EMI_WR 31
196#define MX53_DMA_REQ_EMI_RD 30 196#define MX53_DMA_REQ_EMI_RD 30
197#define MX53_DMA_REQ_SSI1_TX1 29 197#define MX53_DMA_REQ_SSI1_TX0 29
198#define MX53_DMA_REQ_SSI1_RX1 28 198#define MX53_DMA_REQ_SSI1_RX0 28
199#define MX53_DMA_REQ_SSI1_TX2 27 199#define MX53_DMA_REQ_SSI1_TX1 27
200#define MX53_DMA_REQ_SSI1_RX2 26 200#define MX53_DMA_REQ_SSI1_RX1 26
201#define MX53_DMA_REQ_SSI2_TX1 25 201#define MX53_DMA_REQ_SSI2_TX0 25
202#define MX53_DMA_REQ_SSI2_RX1 24 202#define MX53_DMA_REQ_SSI2_RX0 24
203#define MX53_DMA_REQ_SSI2_TX2 23 203#define MX53_DMA_REQ_SSI2_TX1 23
204#define MX53_DMA_REQ_SSI2_RX2 22 204#define MX53_DMA_REQ_SSI2_RX1 22
205#define MX53_DMA_REQ_I2C2_SDHC2 21 205#define MX53_DMA_REQ_I2C2_SDHC2 21
206#define MX53_DMA_REQ_I2C1_SDHC1 20 206#define MX53_DMA_REQ_I2C1_SDHC1 20
207#define MX53_DMA_REQ_UART1_TX 19 207#define MX53_DMA_REQ_UART1_TX 19
@@ -233,7 +233,7 @@
233#define MX53_INT_ESDHC2 2 233#define MX53_INT_ESDHC2 2
234#define MX53_INT_ESDHC3 3 234#define MX53_INT_ESDHC3 3
235#define MX53_INT_ESDHC4 4 235#define MX53_INT_ESDHC4 4
236#define MX53_INT_RESV5 5 236#define MX53_INT_DAP 5
237#define MX53_INT_SDMA 6 237#define MX53_INT_SDMA 6
238#define MX53_INT_IOMUX 7 238#define MX53_INT_IOMUX 7
239#define MX53_INT_NFC 8 239#define MX53_INT_NFC 8
@@ -241,7 +241,7 @@
241#define MX53_INT_IPU_ERR 10 241#define MX53_INT_IPU_ERR 10
242#define MX53_INT_IPU_SYN 11 242#define MX53_INT_IPU_SYN 11
243#define MX53_INT_GPU 12 243#define MX53_INT_GPU 12
244#define MX53_INT_RESV13 13 244#define MX53_INT_UART4 13
245#define MX53_INT_USB_H1 14 245#define MX53_INT_USB_H1 14
246#define MX53_INT_EMI 15 246#define MX53_INT_EMI 15
247#define MX53_INT_USB_H2 16 247#define MX53_INT_USB_H2 16
@@ -262,8 +262,8 @@
262#define MX53_INT_UART1 31 262#define MX53_INT_UART1 31
263#define MX53_INT_UART2 32 263#define MX53_INT_UART2 32
264#define MX53_INT_UART3 33 264#define MX53_INT_UART3 33
265#define MX53_INT_RESV34 34 265#define MX53_INT_RTC 34
266#define MX53_INT_RESV35 35 266#define MX53_INT_PTP 35
267#define MX53_INT_ECSPI1 36 267#define MX53_INT_ECSPI1 36
268#define MX53_INT_ECSPI2 37 268#define MX53_INT_ECSPI2 37
269#define MX53_INT_CSPI 38 269#define MX53_INT_CSPI 38
@@ -293,8 +293,8 @@
293#define MX53_INT_I2C1 62 293#define MX53_INT_I2C1 62
294#define MX53_INT_I2C2 63 294#define MX53_INT_I2C2 63
295#define MX53_INT_I2C3 64 295#define MX53_INT_I2C3 64
296#define MX53_INT_RESV65 65 296#define MX53_INT_MLB 65
297#define MX53_INT_RESV66 66 297#define MX53_INT_ASRC 66
298#define MX53_INT_SPDIF 67 298#define MX53_INT_SPDIF 67
299#define MX53_INT_SIM_DAT 68 299#define MX53_INT_SIM_DAT 68
300#define MX53_INT_IIM 69 300#define MX53_INT_IIM 69
@@ -314,7 +314,7 @@
314#define MX53_INT_CAN2 83 314#define MX53_INT_CAN2 83
315#define MX53_INT_GPU2_IRQ 84 315#define MX53_INT_GPU2_IRQ 84
316#define MX53_INT_GPU2_BUSY 85 316#define MX53_INT_GPU2_BUSY 85
317#define MX53_INT_RESV86 86 317#define MX53_INT_UART5 86
318#define MX53_INT_FEC 87 318#define MX53_INT_FEC 87
319#define MX53_INT_OWIRE 88 319#define MX53_INT_OWIRE 88
320#define MX53_INT_CTI1_TG2 89 320#define MX53_INT_CTI1_TG2 89
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 4ac53ce97c24..09879235a9f5 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -68,7 +68,7 @@
68extern unsigned int __mxc_cpu_type; 68extern unsigned int __mxc_cpu_type;
69#endif 69#endif
70 70
71#ifdef CONFIG_ARCH_MX1 71#ifdef CONFIG_SOC_IMX1
72# ifdef mxc_cpu_type 72# ifdef mxc_cpu_type
73# undef mxc_cpu_type 73# undef mxc_cpu_type
74# define mxc_cpu_type __mxc_cpu_type 74# define mxc_cpu_type __mxc_cpu_type
@@ -80,7 +80,7 @@ extern unsigned int __mxc_cpu_type;
80# define cpu_is_mx1() (0) 80# define cpu_is_mx1() (0)
81#endif 81#endif
82 82
83#ifdef CONFIG_MACH_MX21 83#ifdef CONFIG_SOC_IMX21
84# ifdef mxc_cpu_type 84# ifdef mxc_cpu_type
85# undef mxc_cpu_type 85# undef mxc_cpu_type
86# define mxc_cpu_type __mxc_cpu_type 86# define mxc_cpu_type __mxc_cpu_type
@@ -92,7 +92,7 @@ extern unsigned int __mxc_cpu_type;
92# define cpu_is_mx21() (0) 92# define cpu_is_mx21() (0)
93#endif 93#endif
94 94
95#ifdef CONFIG_ARCH_MX25 95#ifdef CONFIG_SOC_IMX25
96# ifdef mxc_cpu_type 96# ifdef mxc_cpu_type
97# undef mxc_cpu_type 97# undef mxc_cpu_type
98# define mxc_cpu_type __mxc_cpu_type 98# define mxc_cpu_type __mxc_cpu_type
@@ -104,7 +104,7 @@ extern unsigned int __mxc_cpu_type;
104# define cpu_is_mx25() (0) 104# define cpu_is_mx25() (0)
105#endif 105#endif
106 106
107#ifdef CONFIG_MACH_MX27 107#ifdef CONFIG_SOC_IMX27
108# ifdef mxc_cpu_type 108# ifdef mxc_cpu_type
109# undef mxc_cpu_type 109# undef mxc_cpu_type
110# define mxc_cpu_type __mxc_cpu_type 110# define mxc_cpu_type __mxc_cpu_type
diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/arch/arm/plat-mxc/include/mach/sdma.h
index 913e0432e40e..f495c87c113f 100644
--- a/arch/arm/plat-mxc/include/mach/sdma.h
+++ b/arch/arm/plat-mxc/include/mach/sdma.h
@@ -49,14 +49,12 @@ struct sdma_script_start_addrs {
49 * struct sdma_platform_data - platform specific data for SDMA engine 49 * struct sdma_platform_data - platform specific data for SDMA engine
50 * 50 *
51 * @sdma_version The version of this SDMA engine 51 * @sdma_version The version of this SDMA engine
52 * @cpu_name used to generate the firmware name 52 * @fw_name The firmware name
53 * @to_version CPU Tape out version
54 * @script_addrs SDMA scripts addresses in SDMA ROM 53 * @script_addrs SDMA scripts addresses in SDMA ROM
55 */ 54 */
56struct sdma_platform_data { 55struct sdma_platform_data {
57 int sdma_version; 56 int sdma_version;
58 char *cpu_name; 57 char *fw_name;
59 int to_version;
60 struct sdma_script_start_addrs *script_addrs; 58 struct sdma_script_start_addrs *script_addrs;
61}; 59};
62 60
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index d61d5c74817c..10343d1f87e1 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -16,16 +16,7 @@
16#ifndef __ASM_ARCH_MXC_TIMEX_H__ 16#ifndef __ASM_ARCH_MXC_TIMEX_H__
17#define __ASM_ARCH_MXC_TIMEX_H__ 17#define __ASM_ARCH_MXC_TIMEX_H__
18 18
19#if defined CONFIG_ARCH_MX1 19/* Bogus value */
20#define CLOCK_TICK_RATE 16000000 20#define CLOCK_TICK_RATE 12345678
21#elif defined CONFIG_ARCH_MX2
22#define CLOCK_TICK_RATE 13300000
23#elif defined CONFIG_ARCH_MX3
24#define CLOCK_TICK_RATE 16625000
25#elif defined CONFIG_ARCH_MX25
26#define CLOCK_TICK_RATE 16000000
27#elif defined CONFIG_ARCH_MX5
28#define CLOCK_TICK_RATE 8000000
29#endif
30 21
31#endif /* __ASM_ARCH_MXC_TIMEX_H__ */ 22#endif /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index d85e2d1c0324..88fd40452567 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -117,6 +117,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
117 case MACH_TYPE_MX53_EVK: 117 case MACH_TYPE_MX53_EVK:
118 case MACH_TYPE_MX53_LOCO: 118 case MACH_TYPE_MX53_LOCO:
119 case MACH_TYPE_MX53_SMD: 119 case MACH_TYPE_MX53_SMD:
120 case MACH_TYPE_MX53_ARD:
120 uart_base = MX53_UART1_BASE_ADDR; 121 uart_base = MX53_UART1_BASE_ADDR;
121 break; 122 break;
122 default: 123 default:
diff --git a/arch/arm/plat-mxc/iomux-v1.c b/arch/arm/plat-mxc/iomux-v1.c
index 3238c10d4e02..1f73963bc13e 100644
--- a/arch/arm/plat-mxc/iomux-v1.c
+++ b/arch/arm/plat-mxc/iomux-v1.c
@@ -157,7 +157,7 @@ EXPORT_SYMBOL(mxc_gpio_mode);
157static int imx_iomuxv1_setup_multiple(const int *list, unsigned count) 157static int imx_iomuxv1_setup_multiple(const int *list, unsigned count)
158{ 158{
159 size_t i; 159 size_t i;
160 int ret; 160 int ret = 0;
161 161
162 for (i = 0; i < count; ++i) { 162 for (i = 0; i < count; ++i) {
163 ret = mxc_gpio_mode(list[i]); 163 ret = mxc_gpio_mode(list[i]);
@@ -172,45 +172,13 @@ static int imx_iomuxv1_setup_multiple(const int *list, unsigned count)
172int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, 172int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
173 const char *label) 173 const char *label)
174{ 174{
175 size_t i;
176 int ret; 175 int ret;
177 176
178 for (i = 0; i < count; ++i) {
179 unsigned gpio = pin_list[i] & (GPIO_PIN_MASK | GPIO_PORT_MASK);
180
181 ret = gpio_request(gpio, label);
182 if (ret)
183 goto err_gpio_request;
184 }
185
186 ret = imx_iomuxv1_setup_multiple(pin_list, count); 177 ret = imx_iomuxv1_setup_multiple(pin_list, count);
187 if (ret)
188 goto err_setup;
189
190 return 0;
191
192err_setup:
193 BUG_ON(i != count);
194
195err_gpio_request:
196 mxc_gpio_release_multiple_pins(pin_list, i);
197
198 return ret; 178 return ret;
199} 179}
200EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins); 180EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
201 181
202void mxc_gpio_release_multiple_pins(const int *pin_list, int count)
203{
204 size_t i;
205
206 for (i = 0; i < count; ++i) {
207 unsigned gpio = pin_list[i] & (GPIO_PIN_MASK | GPIO_PORT_MASK);
208
209 gpio_free(gpio);
210 }
211}
212EXPORT_SYMBOL(mxc_gpio_release_multiple_pins);
213
214int __init imx_iomuxv1_init(void __iomem *base, int numports) 182int __init imx_iomuxv1_init(void __iomem *base, int numports)
215{ 183{
216 imx_iomuxv1_baseaddr = base; 184 imx_iomuxv1_baseaddr = base;
diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c
index e1c6eff7258a..96953e2e4f11 100644
--- a/arch/arm/plat-mxc/irq-common.c
+++ b/arch/arm/plat-mxc/irq-common.c
@@ -42,17 +42,16 @@ EXPORT_SYMBOL(imx_irq_set_priority);
42 42
43int mxc_set_irq_fiq(unsigned int irq, unsigned int type) 43int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
44{ 44{
45 struct mxc_irq_chip *chip; 45 struct irq_chip_generic *gc;
46 struct irq_chip *base; 46 int (*set_irq_fiq)(unsigned int, unsigned int);
47 int ret; 47 int ret;
48 48
49 ret = -ENOSYS; 49 ret = -ENOSYS;
50 50
51 base = irq_get_chip(irq); 51 gc = irq_get_chip_data(irq);
52 if (base) { 52 if (gc && gc->private) {
53 chip = container_of(base, struct mxc_irq_chip, base); 53 set_irq_fiq = gc->private;
54 if (chip->set_irq_fiq) 54 ret = set_irq_fiq(irq, type);
55 ret = chip->set_irq_fiq(irq, type);
56 } 55 }
57 56
58 return ret; 57 return ret;
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
index 7a61ef8f471a..761c3c940a68 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/arch/arm/plat-mxc/pwm.c
@@ -214,14 +214,14 @@ static int __devinit mxc_pwm_probe(struct platform_device *pdev)
214 goto err_free_clk; 214 goto err_free_clk;
215 } 215 }
216 216
217 r = request_mem_region(r->start, r->end - r->start + 1, pdev->name); 217 r = request_mem_region(r->start, resource_size(r), pdev->name);
218 if (r == NULL) { 218 if (r == NULL) {
219 dev_err(&pdev->dev, "failed to request memory resource\n"); 219 dev_err(&pdev->dev, "failed to request memory resource\n");
220 ret = -EBUSY; 220 ret = -EBUSY;
221 goto err_free_clk; 221 goto err_free_clk;
222 } 222 }
223 223
224 pwm->mmio_base = ioremap(r->start, r->end - r->start + 1); 224 pwm->mmio_base = ioremap(r->start, resource_size(r));
225 if (pwm->mmio_base == NULL) { 225 if (pwm->mmio_base == NULL) {
226 dev_err(&pdev->dev, "failed to ioremap() registers\n"); 226 dev_err(&pdev->dev, "failed to ioremap() registers\n");
227 ret = -ENODEV; 227 ret = -ENODEV;
@@ -236,7 +236,7 @@ static int __devinit mxc_pwm_probe(struct platform_device *pdev)
236 return 0; 236 return 0;
237 237
238err_free_mem: 238err_free_mem:
239 release_mem_region(r->start, r->end - r->start + 1); 239 release_mem_region(r->start, resource_size(r));
240err_free_clk: 240err_free_clk:
241 clk_put(pwm->clk); 241 clk_put(pwm->clk);
242err_free: 242err_free:
@@ -260,7 +260,7 @@ static int __devexit mxc_pwm_remove(struct platform_device *pdev)
260 iounmap(pwm->mmio_base); 260 iounmap(pwm->mmio_base);
261 261
262 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 262 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
263 release_mem_region(r->start, r->end - r->start + 1); 263 release_mem_region(r->start, resource_size(r));
264 264
265 clk_put(pwm->clk); 265 clk_put(pwm->clk);
266 266
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 57f9395f87ce..f257fccdc394 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -49,6 +49,8 @@
49 49
50void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ 50void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
51 51
52#define TZIC_NUM_IRQS 128
53
52#ifdef CONFIG_FIQ 54#ifdef CONFIG_FIQ
53static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) 55static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
54{ 56{
@@ -66,78 +68,34 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
66 68
67 return 0; 69 return 0;
68} 70}
71#else
72#define tzic_set_irq_fiq NULL
69#endif 73#endif
70 74
71/** 75static unsigned int *wakeup_intr[4];
72 * tzic_mask_irq() - Disable interrupt source "d" in the TZIC
73 *
74 * @param d interrupt source
75 */
76static void tzic_mask_irq(struct irq_data *d)
77{
78 int index, off;
79
80 index = d->irq >> 5;
81 off = d->irq & 0x1F;
82 __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index));
83}
84 76
85/** 77static __init void tzic_init_gc(unsigned int irq_start)
86 * tzic_unmask_irq() - Enable interrupt source "d" in the TZIC
87 *
88 * @param d interrupt source
89 */
90static void tzic_unmask_irq(struct irq_data *d)
91{ 78{
92 int index, off; 79 struct irq_chip_generic *gc;
93 80 struct irq_chip_type *ct;
94 index = d->irq >> 5; 81 int idx = irq_start >> 5;
95 off = d->irq & 0x1F; 82
96 __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index)); 83 gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
84 handle_level_irq);
85 gc->private = tzic_set_irq_fiq;
86 gc->wake_enabled = IRQ_MSK(32);
87 wakeup_intr[idx] = &gc->wake_active;
88
89 ct = gc->chip_types;
90 ct->chip.irq_mask = irq_gc_mask_disable_reg;
91 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
92 ct->chip.irq_set_wake = irq_gc_set_wake;
93 ct->regs.disable = TZIC_ENCLEAR0(idx);
94 ct->regs.enable = TZIC_ENSET0(idx);
95
96 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
97} 97}
98 98
99static unsigned int wakeup_intr[4];
100
101/**
102 * tzic_set_wake_irq() - Set interrupt source "d" in the TZIC as a wake-up source.
103 *
104 * @param d interrupt source
105 * @param enable enable as wake-up if equal to non-zero
106 * disble as wake-up if equal to zero
107 *
108 * @return This function returns 0 on success.
109 */
110static int tzic_set_wake_irq(struct irq_data *d, unsigned int enable)
111{
112 unsigned int index, off;
113
114 index = d->irq >> 5;
115 off = d->irq & 0x1F;
116
117 if (index > 3)
118 return -EINVAL;
119
120 if (enable)
121 wakeup_intr[index] |= (1 << off);
122 else
123 wakeup_intr[index] &= ~(1 << off);
124
125 return 0;
126}
127
128static struct mxc_irq_chip mxc_tzic_chip = {
129 .base = {
130 .name = "MXC_TZIC",
131 .irq_ack = tzic_mask_irq,
132 .irq_mask = tzic_mask_irq,
133 .irq_unmask = tzic_unmask_irq,
134 .irq_set_wake = tzic_set_wake_irq,
135 },
136#ifdef CONFIG_FIQ
137 .set_irq_fiq = tzic_set_irq_fiq,
138#endif
139};
140
141/* 99/*
142 * This function initializes the TZIC hardware and disables all the 100 * This function initializes the TZIC hardware and disables all the
143 * interrupts. It registers the interrupt enable and disable functions 101 * interrupts. It registers the interrupt enable and disable functions
@@ -166,11 +124,8 @@ void __init tzic_init_irq(void __iomem *irqbase)
166 124
167 /* all IRQ no FIQ Warning :: No selection */ 125 /* all IRQ no FIQ Warning :: No selection */
168 126
169 for (i = 0; i < MXC_INTERNAL_IRQS; i++) { 127 for (i = 0; i < TZIC_NUM_IRQS; i += 32)
170 irq_set_chip_and_handler(i, &mxc_tzic_chip.base, 128 tzic_init_gc(i);
171 handle_level_irq);
172 set_irq_flags(i, IRQF_VALID);
173 }
174 129
175#ifdef CONFIG_FIQ 130#ifdef CONFIG_FIQ
176 /* Initialize FIQ */ 131 /* Initialize FIQ */
@@ -197,7 +152,7 @@ int tzic_enable_wake(int is_idle)
197 152
198 for (i = 0; i < 4; i++) { 153 for (i = 0; i < 4; i++) {
199 v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) : 154 v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) :
200 wakeup_intr[i]; 155 *wakeup_intr[i];
201 __raw_writel(v, tzic_base + TZIC_WAKEUP0(i)); 156 __raw_writel(v, tzic_base + TZIC_WAKEUP0(i));
202 } 157 }
203 158
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 19:08:32 -0500