aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-mxc
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r--arch/arm/plat-mxc/Kconfig10
-rw-r--r--arch/arm/plat-mxc/Makefile4
-rw-r--r--arch/arm/plat-mxc/audmux-v1.c4
-rw-r--r--arch/arm/plat-mxc/audmux-v2.c4
-rw-r--r--arch/arm/plat-mxc/devices.c33
-rw-r--r--arch/arm/plat-mxc/devices/Kconfig11
-rw-r--r--arch/arm/plat-mxc/devices/Makefile4
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-i2c.c29
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-uart.c60
-rw-r--r--arch/arm/plat-mxc/devices/platform-mxc_nand.c44
-rw-r--r--arch/arm/plat-mxc/devices/platform-spi_imx.c30
-rw-r--r--arch/arm/plat-mxc/dma-mx1-mx2.c863
-rw-r--r--arch/arm/plat-mxc/ehci.c4
-rw-r--r--arch/arm/plat-mxc/include/mach/board-armadillo5x0.h15
-rw-r--r--arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-kzmarm11.h39
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx21ads.h52
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx27ads.h344
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx27lite.h14
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx27pdk.h14
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31_3ds.h59
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31ads.h117
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31lilly.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31lite.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31moboard.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx35pdk.h22
-rw-r--r--arch/arm/plat-mxc/include/mach/board-pcm037.h22
-rw-r--r--arch/arm/plat-mxc/include/mach/board-pcm038.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-pcm043.h22
-rw-r--r--arch/arm/plat-mxc/include/mach/board-qong.h17
-rw-r--r--arch/arm/plat-mxc/include/mach/devices-common.h42
-rw-r--r--arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h105
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mxc91231.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mx1.h28
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h36
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mx31.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3_camera.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc91231.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_nand.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/system.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/timex.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/vmalloc.h4
-rw-r--r--arch/arm/plat-mxc/irq.c3
-rw-r--r--arch/arm/plat-mxc/system.c4
-rw-r--r--arch/arm/plat-mxc/tzic.c2
48 files changed, 315 insertions, 1798 deletions
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 902ba9e42c5b..20b2e79e54f2 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -1,5 +1,7 @@
1if ARCH_MXC 1if ARCH_MXC
2 2
3source "arch/arm/plat-mxc/devices/Kconfig"
4
3menu "Freescale MXC Implementations" 5menu "Freescale MXC Implementations"
4 6
5choice 7choice
@@ -8,15 +10,12 @@ choice
8 10
9config ARCH_MX1 11config ARCH_MX1
10 bool "MX1-based" 12 bool "MX1-based"
11 select CPU_ARM920T 13 select SOC_IMX1
12 select IMX_HAVE_IOMUX_V1
13 help 14 help
14 This enables support for systems based on the Freescale i.MX1 family 15 This enables support for systems based on the Freescale i.MX1 family
15 16
16config ARCH_MX2 17config ARCH_MX2
17 bool "MX2-based" 18 bool "MX2-based"
18 select CPU_ARM926T
19 select IMX_HAVE_IOMUX_V1
20 help 19 help
21 This enables support for systems based on the Freescale i.MX2 family 20 This enables support for systems based on the Freescale i.MX2 family
22 21
@@ -49,8 +48,7 @@ config ARCH_MX5
49 48
50endchoice 49endchoice
51 50
52source "arch/arm/mach-mx1/Kconfig" 51source "arch/arm/mach-imx/Kconfig"
53source "arch/arm/mach-mx2/Kconfig"
54source "arch/arm/mach-mx3/Kconfig" 52source "arch/arm/mach-mx3/Kconfig"
55source "arch/arm/mach-mx25/Kconfig" 53source "arch/arm/mach-mx25/Kconfig"
56source "arch/arm/mach-mxc91231/Kconfig" 54source "arch/arm/mach-mxc91231/Kconfig"
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 895bc3c5e0c0..c7506a80eb31 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -8,8 +8,6 @@ obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
8# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o) 8# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)
9obj-$(CONFIG_MXC_TZIC) += tzic.o 9obj-$(CONFIG_MXC_TZIC) += tzic.o
10 10
11obj-$(CONFIG_ARCH_MX1) += dma-mx1-mx2.o
12obj-$(CONFIG_ARCH_MX2) += dma-mx1-mx2.o
13obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o 11obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
14obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o 12obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
15obj-$(CONFIG_MXC_PWM) += pwm.o 13obj-$(CONFIG_MXC_PWM) += pwm.o
@@ -21,3 +19,5 @@ ifdef CONFIG_SND_IMX_SOC
21obj-y += ssi-fiq.o 19obj-y += ssi-fiq.o
22obj-y += ssi-fiq-ksym.o 20obj-y += ssi-fiq-ksym.o
23endif 21endif
22
23obj-y += devices/
diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c
index b62917ca3f95..1180bef7664b 100644
--- a/arch/arm/plat-mxc/audmux-v1.c
+++ b/arch/arm/plat-mxc/audmux-v1.c
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */ 16 */
21 17
22#include <linux/module.h> 18#include <linux/module.h>
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index ab94d78a927f..f9e7cdbd0005 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */ 16 */
21 17
22#include <linux/module.h> 18#include <linux/module.h>
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index 56f2fb5cc456..735776d84956 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -18,6 +18,7 @@
18 18
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/err.h>
21#include <linux/platform_device.h> 22#include <linux/platform_device.h>
22#include <mach/common.h> 23#include <mach/common.h>
23 24
@@ -35,3 +36,35 @@ int __init mxc_register_device(struct platform_device *pdev, void *data)
35 return ret; 36 return ret;
36} 37}
37 38
39struct platform_device *__init imx_add_platform_device(const char *name, int id,
40 const struct resource *res, unsigned int num_resources,
41 const void *data, size_t size_data)
42{
43 int ret = -ENOMEM;
44 struct platform_device *pdev;
45
46 pdev = platform_device_alloc(name, id);
47 if (!pdev)
48 goto err;
49
50 if (res) {
51 ret = platform_device_add_resources(pdev, res, num_resources);
52 if (ret)
53 goto err;
54 }
55
56 if (data) {
57 ret = platform_device_add_data(pdev, data, size_data);
58 if (ret)
59 goto err;
60 }
61
62 ret = platform_device_add(pdev);
63 if (ret) {
64err:
65 platform_device_put(pdev);
66 return ERR_PTR(ret);
67 }
68
69 return pdev;
70}
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
new file mode 100644
index 000000000000..09230f8c802a
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -0,0 +1,11 @@
1config IMX_HAVE_PLATFORM_IMX_I2C
2 bool
3
4config IMX_HAVE_PLATFORM_IMX_UART
5 bool
6
7config IMX_HAVE_PLATFORM_MXC_NAND
8 bool
9
10config IMX_HAVE_PLATFORM_SPI_IMX
11 bool
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
new file mode 100644
index 000000000000..5ecbb244d210
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -0,0 +1,4 @@
1obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
2obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
3obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
4obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
new file mode 100644
index 000000000000..d0af9f7d8aed
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/devices-common.h>
10
11struct platform_device *__init imx_add_imx_i2c(int id,
12 resource_size_t iobase, resource_size_t iosize, int irq,
13 const struct imxi2c_platform_data *pdata)
14{
15 struct resource res[] = {
16 {
17 .start = iobase,
18 .end = iobase + iosize - 1,
19 .flags = IORESOURCE_MEM,
20 }, {
21 .start = irq,
22 .end = irq,
23 .flags = IORESOURCE_IRQ,
24 },
25 };
26
27 return imx_add_platform_device("imx-i2c", id, res, ARRAY_SIZE(res),
28 pdata, sizeof(*pdata));
29}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c
new file mode 100644
index 000000000000..fa3dff1433e8
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c
@@ -0,0 +1,60 @@
1/*
2 * Copyright (C) 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/devices-common.h>
10
11struct platform_device *__init imx_add_imx_uart_3irq(int id,
12 resource_size_t iobase, resource_size_t iosize,
13 resource_size_t irqrx, resource_size_t irqtx,
14 resource_size_t irqrts,
15 const struct imxuart_platform_data *pdata)
16{
17 struct resource res[] = {
18 {
19 .start = iobase,
20 .end = iobase + iosize - 1,
21 .flags = IORESOURCE_MEM,
22 }, {
23 .start = irqrx,
24 .end = irqrx,
25 .flags = IORESOURCE_IRQ,
26 }, {
27 .start = irqtx,
28 .end = irqtx,
29 .flags = IORESOURCE_IRQ,
30 }, {
31 .start = irqrts,
32 .end = irqrx,
33 .flags = IORESOURCE_IRQ,
34 },
35 };
36
37 return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res),
38 pdata, sizeof(*pdata));
39}
40
41struct platform_device *__init imx_add_imx_uart_1irq(int id,
42 resource_size_t iobase, resource_size_t iosize,
43 resource_size_t irq,
44 const struct imxuart_platform_data *pdata)
45{
46 struct resource res[] = {
47 {
48 .start = iobase,
49 .end = iobase + iosize - 1,
50 .flags = IORESOURCE_MEM,
51 }, {
52 .start = irq,
53 .end = irq,
54 .flags = IORESOURCE_IRQ,
55 },
56 };
57
58 return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res),
59 pdata, sizeof(*pdata));
60}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
new file mode 100644
index 000000000000..1c286418d123
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
@@ -0,0 +1,44 @@
1/*
2 * Copyright (C) 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/devices-common.h>
11
12static struct platform_device *__init imx_add_mxc_nand(resource_size_t iobase,
13 int irq, const struct mxc_nand_platform_data *pdata,
14 resource_size_t iosize)
15{
16 static int id = 0;
17
18 struct resource res[] = {
19 {
20 .start = iobase,
21 .end = iobase + iosize - 1,
22 .flags = IORESOURCE_MEM,
23 }, {
24 .start = irq,
25 .end = irq,
26 .flags = IORESOURCE_IRQ,
27 },
28 };
29
30 return imx_add_platform_device("mxc_nand", id++, res, ARRAY_SIZE(res),
31 pdata, sizeof(*pdata));
32}
33
34struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
35 int irq, const struct mxc_nand_platform_data *pdata)
36{
37 return imx_add_mxc_nand(iobase, irq, pdata, SZ_4K);
38}
39
40struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
41 int irq, const struct mxc_nand_platform_data *pdata)
42{
43 return imx_add_mxc_nand(iobase, irq, pdata, SZ_8K);
44}
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
new file mode 100644
index 000000000000..2831a6d3eb4b
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -0,0 +1,30 @@
1/*
2 * Copyright (C) 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/devices-common.h>
11
12struct platform_device *__init imx_add_spi_imx(int id,
13 resource_size_t iobase, resource_size_t iosize, int irq,
14 const struct spi_imx_master *pdata)
15{
16 struct resource res[] = {
17 {
18 .start = iobase,
19 .end = iobase + iosize - 1,
20 .flags = IORESOURCE_MEM,
21 }, {
22 .start = irq,
23 .end = irq,
24 .flags = IORESOURCE_IRQ,
25 },
26 };
27
28 return imx_add_platform_device("spi_imx", id, res, ARRAY_SIZE(res),
29 pdata, sizeof(*pdata));
30}
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c
deleted file mode 100644
index e16014b0d13c..000000000000
--- a/arch/arm/plat-mxc/dma-mx1-mx2.c
+++ /dev/null
@@ -1,863 +0,0 @@
1/*
2 * linux/arch/arm/plat-mxc/dma-mx1-mx2.c
3 *
4 * i.MX DMA registration and IRQ dispatching
5 *
6 * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
7 * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
8 * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301, USA.
23 */
24
25#include <linux/module.h>
26#include <linux/init.h>
27#include <linux/kernel.h>
28#include <linux/interrupt.h>
29#include <linux/errno.h>
30#include <linux/clk.h>
31#include <linux/scatterlist.h>
32#include <linux/io.h>
33
34#include <asm/system.h>
35#include <asm/irq.h>
36#include <mach/hardware.h>
37#include <mach/dma-mx1-mx2.h>
38
39#define DMA_DCR 0x00 /* Control Register */
40#define DMA_DISR 0x04 /* Interrupt status Register */
41#define DMA_DIMR 0x08 /* Interrupt mask Register */
42#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
43#define DMA_DRTOSR 0x10 /* Request timeout Register */
44#define DMA_DSESR 0x14 /* Transfer Error Status Register */
45#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
46#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
47#define DMA_WSRA 0x40 /* W-Size Register A */
48#define DMA_XSRA 0x44 /* X-Size Register A */
49#define DMA_YSRA 0x48 /* Y-Size Register A */
50#define DMA_WSRB 0x4c /* W-Size Register B */
51#define DMA_XSRB 0x50 /* X-Size Register B */
52#define DMA_YSRB 0x54 /* Y-Size Register B */
53#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
54#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
55#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
56#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
57#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
58#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
59#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
60#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
61#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
62
63#define DCR_DRST (1<<1)
64#define DCR_DEN (1<<0)
65#define DBTOCR_EN (1<<15)
66#define DBTOCR_CNT(x) ((x) & 0x7fff)
67#define CNTR_CNT(x) ((x) & 0xffffff)
68#define CCR_ACRPT (1<<14)
69#define CCR_DMOD_LINEAR (0x0 << 12)
70#define CCR_DMOD_2D (0x1 << 12)
71#define CCR_DMOD_FIFO (0x2 << 12)
72#define CCR_DMOD_EOBFIFO (0x3 << 12)
73#define CCR_SMOD_LINEAR (0x0 << 10)
74#define CCR_SMOD_2D (0x1 << 10)
75#define CCR_SMOD_FIFO (0x2 << 10)
76#define CCR_SMOD_EOBFIFO (0x3 << 10)
77#define CCR_MDIR_DEC (1<<9)
78#define CCR_MSEL_B (1<<8)
79#define CCR_DSIZ_32 (0x0 << 6)
80#define CCR_DSIZ_8 (0x1 << 6)
81#define CCR_DSIZ_16 (0x2 << 6)
82#define CCR_SSIZ_32 (0x0 << 4)
83#define CCR_SSIZ_8 (0x1 << 4)
84#define CCR_SSIZ_16 (0x2 << 4)
85#define CCR_REN (1<<3)
86#define CCR_RPT (1<<2)
87#define CCR_FRC (1<<1)
88#define CCR_CEN (1<<0)
89#define RTOR_EN (1<<15)
90#define RTOR_CLK (1<<14)
91#define RTOR_PSC (1<<13)
92
93/*
94 * struct imx_dma_channel - i.MX specific DMA extension
95 * @name: name specified by DMA client
96 * @irq_handler: client callback for end of transfer
97 * @err_handler: client callback for error condition
98 * @data: clients context data for callbacks
99 * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
100 * @sg: pointer to the actual read/written chunk for scatter-gather emulation
101 * @resbytes: total residual number of bytes to transfer
102 * (it can be lower or same as sum of SG mapped chunk sizes)
103 * @sgcount: number of chunks to be read/written
104 *
105 * Structure is used for IMX DMA processing. It would be probably good
106 * @struct dma_struct in the future for external interfacing and use
107 * @struct imx_dma_channel only as extension to it.
108 */
109
110struct imx_dma_channel {
111 const char *name;
112 void (*irq_handler) (int, void *);
113 void (*err_handler) (int, void *, int errcode);
114 void (*prog_handler) (int, void *, struct scatterlist *);
115 void *data;
116 unsigned int dma_mode;
117 struct scatterlist *sg;
118 unsigned int resbytes;
119 int dma_num;
120
121 int in_use;
122
123 u32 ccr_from_device;
124 u32 ccr_to_device;
125
126 struct timer_list watchdog;
127
128 int hw_chaining;
129};
130
131static void __iomem *imx_dmav1_baseaddr;
132
133static void imx_dmav1_writel(unsigned val, unsigned offset)
134{
135 __raw_writel(val, imx_dmav1_baseaddr + offset);
136}
137
138static unsigned imx_dmav1_readl(unsigned offset)
139{
140 return __raw_readl(imx_dmav1_baseaddr + offset);
141}
142
143static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
144
145static struct clk *dma_clk;
146
147static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
148{
149 if (cpu_is_mx27())
150 return imxdma->hw_chaining;
151 else
152 return 0;
153}
154
155/*
156 * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
157 */
158static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
159{
160 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
161 unsigned long now;
162
163 if (!imxdma->name) {
164 printk(KERN_CRIT "%s: called for not allocated channel %d\n",
165 __func__, channel);
166 return 0;
167 }
168
169 now = min(imxdma->resbytes, sg->length);
170 if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
171 imxdma->resbytes -= now;
172
173 if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
174 imx_dmav1_writel(sg->dma_address, DMA_DAR(channel));
175 else
176 imx_dmav1_writel(sg->dma_address, DMA_SAR(channel));
177
178 imx_dmav1_writel(now, DMA_CNTR(channel));
179
180 pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
181 "size 0x%08x\n", channel,
182 imx_dmav1_readl(DMA_DAR(channel)),
183 imx_dmav1_readl(DMA_SAR(channel)),
184 imx_dmav1_readl(DMA_CNTR(channel)));
185
186 return now;
187}
188
189/**
190 * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from
191 * device transfer
192 *
193 * @channel: i.MX DMA channel number
194 * @dma_address: the DMA/physical memory address of the linear data block
195 * to transfer
196 * @dma_length: length of the data block in bytes
197 * @dev_addr: physical device port address
198 * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
199 * or %DMA_MODE_WRITE from memory to the device
200 *
201 * Return value: if incorrect parameters are provided -%EINVAL.
202 * Zero indicates success.
203 */
204int
205imx_dma_setup_single(int channel, dma_addr_t dma_address,
206 unsigned int dma_length, unsigned int dev_addr,
207 unsigned int dmamode)
208{
209 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
210
211 imxdma->sg = NULL;
212 imxdma->dma_mode = dmamode;
213
214 if (!dma_address) {
215 printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
216 channel);
217 return -EINVAL;
218 }
219
220 if (!dma_length) {
221 printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
222 channel);
223 return -EINVAL;
224 }
225
226 if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
227 pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
228 "dev_addr=0x%08x for read\n",
229 channel, __func__, (unsigned int)dma_address,
230 dma_length, dev_addr);
231
232 imx_dmav1_writel(dev_addr, DMA_SAR(channel));
233 imx_dmav1_writel(dma_address, DMA_DAR(channel));
234 imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
235 } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
236 pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
237 "dev_addr=0x%08x for write\n",
238 channel, __func__, (unsigned int)dma_address,
239 dma_length, dev_addr);
240
241 imx_dmav1_writel(dma_address, DMA_SAR(channel));
242 imx_dmav1_writel(dev_addr, DMA_DAR(channel));
243 imx_dmav1_writel(imxdma->ccr_to_device,
244 DMA_CCR(channel));
245 } else {
246 printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
247 channel);
248 return -EINVAL;
249 }
250
251 imx_dmav1_writel(dma_length, DMA_CNTR(channel));
252
253 return 0;
254}
255EXPORT_SYMBOL(imx_dma_setup_single);
256
257/**
258 * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
259 * @channel: i.MX DMA channel number
260 * @sg: pointer to the scatter-gather list/vector
261 * @sgcount: scatter-gather list hungs count
262 * @dma_length: total length of the transfer request in bytes
263 * @dev_addr: physical device port address
264 * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
265 * or %DMA_MODE_WRITE from memory to the device
266 *
267 * The function sets up DMA channel state and registers to be ready for
268 * transfer specified by provided parameters. The scatter-gather emulation
269 * is set up according to the parameters.
270 *
271 * The full preparation of the transfer requires setup of more register
272 * by the caller before imx_dma_enable() can be called.
273 *
274 * %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes
275 *
276 * %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx
277 *
278 * %CCR(channel) has to specify transfer parameters, the next settings is
279 * typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is
280 * specified
281 *
282 * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
283 *
284 * The typical setup for %DMA_MODE_WRITE is specified by next options
285 * combination
286 *
287 * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
288 *
289 * Be careful here and do not mistakenly mix source and target device
290 * port sizes constants, they are really different:
291 * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
292 * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
293 *
294 * Return value: if incorrect parameters are provided -%EINVAL.
295 * Zero indicates success.
296 */
297int
298imx_dma_setup_sg(int channel,
299 struct scatterlist *sg, unsigned int sgcount,
300 unsigned int dma_length, unsigned int dev_addr,
301 unsigned int dmamode)
302{
303 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
304
305 if (imxdma->in_use)
306 return -EBUSY;
307
308 imxdma->sg = sg;
309 imxdma->dma_mode = dmamode;
310 imxdma->resbytes = dma_length;
311
312 if (!sg || !sgcount) {
313 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n",
314 channel);
315 return -EINVAL;
316 }
317
318 if (!sg->length) {
319 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
320 channel);
321 return -EINVAL;
322 }
323
324 if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
325 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
326 "dev_addr=0x%08x for read\n",
327 channel, __func__, sg, sgcount, dma_length, dev_addr);
328
329 imx_dmav1_writel(dev_addr, DMA_SAR(channel));
330 imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
331 } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
332 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
333 "dev_addr=0x%08x for write\n",
334 channel, __func__, sg, sgcount, dma_length, dev_addr);
335
336 imx_dmav1_writel(dev_addr, DMA_DAR(channel));
337 imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel));
338 } else {
339 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
340 channel);
341 return -EINVAL;
342 }
343
344 imx_dma_sg_next(channel, sg);
345
346 return 0;
347}
348EXPORT_SYMBOL(imx_dma_setup_sg);
349
350int
351imx_dma_config_channel(int channel, unsigned int config_port,
352 unsigned int config_mem, unsigned int dmareq, int hw_chaining)
353{
354 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
355 u32 dreq = 0;
356
357 imxdma->hw_chaining = 0;
358
359 if (hw_chaining) {
360 imxdma->hw_chaining = 1;
361 if (!imx_dma_hw_chain(imxdma))
362 return -EINVAL;
363 }
364
365 if (dmareq)
366 dreq = CCR_REN;
367
368 imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
369 imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
370
371 imx_dmav1_writel(dmareq, DMA_RSSR(channel));
372
373 return 0;
374}
375EXPORT_SYMBOL(imx_dma_config_channel);
376
377void imx_dma_config_burstlen(int channel, unsigned int burstlen)
378{
379 imx_dmav1_writel(burstlen, DMA_BLR(channel));
380}
381EXPORT_SYMBOL(imx_dma_config_burstlen);
382
383/**
384 * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification
385 * handlers
386 * @channel: i.MX DMA channel number
387 * @irq_handler: the pointer to the function called if the transfer
388 * ends successfully
389 * @err_handler: the pointer to the function called if the premature
390 * end caused by error occurs
391 * @data: user specified value to be passed to the handlers
392 */
393int
394imx_dma_setup_handlers(int channel,
395 void (*irq_handler) (int, void *),
396 void (*err_handler) (int, void *, int),
397 void *data)
398{
399 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
400 unsigned long flags;
401
402 if (!imxdma->name) {
403 printk(KERN_CRIT "%s: called for not allocated channel %d\n",
404 __func__, channel);
405 return -ENODEV;
406 }
407
408 local_irq_save(flags);
409 imx_dmav1_writel(1 << channel, DMA_DISR);
410 imxdma->irq_handler = irq_handler;
411 imxdma->err_handler = err_handler;
412 imxdma->data = data;
413 local_irq_restore(flags);
414 return 0;
415}
416EXPORT_SYMBOL(imx_dma_setup_handlers);
417
418/**
419 * imx_dma_setup_progression_handler - setup i.MX DMA channel progression
420 * handlers
421 * @channel: i.MX DMA channel number
422 * @prog_handler: the pointer to the function called if the transfer progresses
423 */
424int
425imx_dma_setup_progression_handler(int channel,
426 void (*prog_handler) (int, void*, struct scatterlist*))
427{
428 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
429 unsigned long flags;
430
431 if (!imxdma->name) {
432 printk(KERN_CRIT "%s: called for not allocated channel %d\n",
433 __func__, channel);
434 return -ENODEV;
435 }
436
437 local_irq_save(flags);
438 imxdma->prog_handler = prog_handler;
439 local_irq_restore(flags);
440 return 0;
441}
442EXPORT_SYMBOL(imx_dma_setup_progression_handler);
443
444/**
445 * imx_dma_enable - function to start i.MX DMA channel operation
446 * @channel: i.MX DMA channel number
447 *
448 * The channel has to be allocated by driver through imx_dma_request()
449 * or imx_dma_request_by_prio() function.
450 * The transfer parameters has to be set to the channel registers through
451 * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
452 * and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to
453 * be set prior this function call by the channel user.
454 */
455void imx_dma_enable(int channel)
456{
457 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
458 unsigned long flags;
459
460 pr_debug("imxdma%d: imx_dma_enable\n", channel);
461
462 if (!imxdma->name) {
463 printk(KERN_CRIT "%s: called for not allocated channel %d\n",
464 __func__, channel);
465 return;
466 }
467
468 if (imxdma->in_use)
469 return;
470
471 local_irq_save(flags);
472
473 imx_dmav1_writel(1 << channel, DMA_DISR);
474 imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
475 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
476 CCR_ACRPT, DMA_CCR(channel));
477
478#ifdef CONFIG_ARCH_MX2
479 if ((cpu_is_mx21() || cpu_is_mx27()) &&
480 imxdma->sg && imx_dma_hw_chain(imxdma)) {
481 imxdma->sg = sg_next(imxdma->sg);
482 if (imxdma->sg) {
483 u32 tmp;
484 imx_dma_sg_next(channel, imxdma->sg);
485 tmp = imx_dmav1_readl(DMA_CCR(channel));
486 imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
487 DMA_CCR(channel));
488 }
489 }
490#endif
491 imxdma->in_use = 1;
492
493 local_irq_restore(flags);
494}
495EXPORT_SYMBOL(imx_dma_enable);
496
497/**
498 * imx_dma_disable - stop, finish i.MX DMA channel operatin
499 * @channel: i.MX DMA channel number
500 */
501void imx_dma_disable(int channel)
502{
503 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
504 unsigned long flags;
505
506 pr_debug("imxdma%d: imx_dma_disable\n", channel);
507
508 if (imx_dma_hw_chain(imxdma))
509 del_timer(&imxdma->watchdog);
510
511 local_irq_save(flags);
512 imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
513 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
514 DMA_CCR(channel));
515 imx_dmav1_writel(1 << channel, DMA_DISR);
516 imxdma->in_use = 0;
517 local_irq_restore(flags);
518}
519EXPORT_SYMBOL(imx_dma_disable);
520
521#ifdef CONFIG_ARCH_MX2
522static void imx_dma_watchdog(unsigned long chno)
523{
524 struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
525
526 imx_dmav1_writel(0, DMA_CCR(chno));
527 imxdma->in_use = 0;
528 imxdma->sg = NULL;
529
530 if (imxdma->err_handler)
531 imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
532}
533#endif
534
535static irqreturn_t dma_err_handler(int irq, void *dev_id)
536{
537 int i, disr;
538 struct imx_dma_channel *imxdma;
539 unsigned int err_mask;
540 int errcode;
541
542 disr = imx_dmav1_readl(DMA_DISR);
543
544 err_mask = imx_dmav1_readl(DMA_DBTOSR) |
545 imx_dmav1_readl(DMA_DRTOSR) |
546 imx_dmav1_readl(DMA_DSESR) |
547 imx_dmav1_readl(DMA_DBOSR);
548
549 if (!err_mask)
550 return IRQ_HANDLED;
551
552 imx_dmav1_writel(disr & err_mask, DMA_DISR);
553
554 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
555 if (!(err_mask & (1 << i)))
556 continue;
557 imxdma = &imx_dma_channels[i];
558 errcode = 0;
559
560 if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
561 imx_dmav1_writel(1 << i, DMA_DBTOSR);
562 errcode |= IMX_DMA_ERR_BURST;
563 }
564 if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
565 imx_dmav1_writel(1 << i, DMA_DRTOSR);
566 errcode |= IMX_DMA_ERR_REQUEST;
567 }
568 if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
569 imx_dmav1_writel(1 << i, DMA_DSESR);
570 errcode |= IMX_DMA_ERR_TRANSFER;
571 }
572 if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
573 imx_dmav1_writel(1 << i, DMA_DBOSR);
574 errcode |= IMX_DMA_ERR_BUFFER;
575 }
576 if (imxdma->name && imxdma->err_handler) {
577 imxdma->err_handler(i, imxdma->data, errcode);
578 continue;
579 }
580
581 imx_dma_channels[i].sg = NULL;
582
583 printk(KERN_WARNING
584 "DMA timeout on channel %d (%s) -%s%s%s%s\n",
585 i, imxdma->name,
586 errcode & IMX_DMA_ERR_BURST ? " burst" : "",
587 errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
588 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
589 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
590 }
591 return IRQ_HANDLED;
592}
593
594static void dma_irq_handle_channel(int chno)
595{
596 struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
597
598 if (!imxdma->name) {
599 /*
600 * IRQ for an unregistered DMA channel:
601 * let's clear the interrupts and disable it.
602 */
603 printk(KERN_WARNING
604 "spurious IRQ for DMA channel %d\n", chno);
605 return;
606 }
607
608 if (imxdma->sg) {
609 u32 tmp;
610 struct scatterlist *current_sg = imxdma->sg;
611 imxdma->sg = sg_next(imxdma->sg);
612
613 if (imxdma->sg) {
614 imx_dma_sg_next(chno, imxdma->sg);
615
616 tmp = imx_dmav1_readl(DMA_CCR(chno));
617
618 if (imx_dma_hw_chain(imxdma)) {
619 /* FIXME: The timeout should probably be
620 * configurable
621 */
622 mod_timer(&imxdma->watchdog,
623 jiffies + msecs_to_jiffies(500));
624
625 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
626 imx_dmav1_writel(tmp, DMA_CCR(chno));
627 } else {
628 imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
629 tmp |= CCR_CEN;
630 }
631
632 imx_dmav1_writel(tmp, DMA_CCR(chno));
633
634 if (imxdma->prog_handler)
635 imxdma->prog_handler(chno, imxdma->data,
636 current_sg);
637
638 return;
639 }
640
641 if (imx_dma_hw_chain(imxdma)) {
642 del_timer(&imxdma->watchdog);
643 return;
644 }
645 }
646
647 imx_dmav1_writel(0, DMA_CCR(chno));
648 imxdma->in_use = 0;
649 if (imxdma->irq_handler)
650 imxdma->irq_handler(chno, imxdma->data);
651}
652
653static irqreturn_t dma_irq_handler(int irq, void *dev_id)
654{
655 int i, disr;
656
657#ifdef CONFIG_ARCH_MX2
658 if (cpu_is_mx21() || cpu_is_mx27())
659 dma_err_handler(irq, dev_id);
660#endif
661
662 disr = imx_dmav1_readl(DMA_DISR);
663
664 pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
665 disr);
666
667 imx_dmav1_writel(disr, DMA_DISR);
668 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
669 if (disr & (1 << i))
670 dma_irq_handle_channel(i);
671 }
672
673 return IRQ_HANDLED;
674}
675
676/**
677 * imx_dma_request - request/allocate specified channel number
678 * @channel: i.MX DMA channel number
679 * @name: the driver/caller own non-%NULL identification
680 */
681int imx_dma_request(int channel, const char *name)
682{
683 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
684 unsigned long flags;
685 int ret = 0;
686
687 /* basic sanity checks */
688 if (!name)
689 return -EINVAL;
690
691 if (channel >= IMX_DMA_CHANNELS) {
692 printk(KERN_CRIT "%s: called for non-existed channel %d\n",
693 __func__, channel);
694 return -EINVAL;
695 }
696
697 local_irq_save(flags);
698 if (imxdma->name) {
699 local_irq_restore(flags);
700 return -EBUSY;
701 }
702 memset(imxdma, 0, sizeof(imxdma));
703 imxdma->name = name;
704 local_irq_restore(flags); /* request_irq() can block */
705
706#ifdef CONFIG_ARCH_MX2
707 if (cpu_is_mx21() || cpu_is_mx27()) {
708 ret = request_irq(MX2x_INT_DMACH0 + channel,
709 dma_irq_handler, 0, "DMA", NULL);
710 if (ret) {
711 imxdma->name = NULL;
712 pr_crit("Can't register IRQ %d for DMA channel %d\n",
713 MX2x_INT_DMACH0 + channel, channel);
714 return ret;
715 }
716 init_timer(&imxdma->watchdog);
717 imxdma->watchdog.function = &imx_dma_watchdog;
718 imxdma->watchdog.data = channel;
719 }
720#endif
721
722 return ret;
723}
724EXPORT_SYMBOL(imx_dma_request);
725
726/**
727 * imx_dma_free - release previously acquired channel
728 * @channel: i.MX DMA channel number
729 */
730void imx_dma_free(int channel)
731{
732 unsigned long flags;
733 struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
734
735 if (!imxdma->name) {
736 printk(KERN_CRIT
737 "%s: trying to free free channel %d\n",
738 __func__, channel);
739 return;
740 }
741
742 local_irq_save(flags);
743 /* Disable interrupts */
744 imx_dma_disable(channel);
745 imxdma->name = NULL;
746
747#ifdef CONFIG_ARCH_MX2
748 if (cpu_is_mx21() || cpu_is_mx27())
749 free_irq(MX2x_INT_DMACH0 + channel, NULL);
750#endif
751
752 local_irq_restore(flags);
753}
754EXPORT_SYMBOL(imx_dma_free);
755
756/**
757 * imx_dma_request_by_prio - find and request some of free channels best
758 * suiting requested priority
759 * @channel: i.MX DMA channel number
760 * @name: the driver/caller own non-%NULL identification
761 *
762 * This function tries to find a free channel in the specified priority group
763 * This function tries to find a free channel in the specified priority group
764 * if the priority cannot be achieved it tries to look for free channel
765 * in the higher and then even lower priority groups.
766 *
767 * Return value: If there is no free channel to allocate, -%ENODEV is returned.
768 * On successful allocation channel is returned.
769 */
770int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio)
771{
772 int i;
773 int best;
774
775 switch (prio) {
776 case (DMA_PRIO_HIGH):
777 best = 8;
778 break;
779 case (DMA_PRIO_MEDIUM):
780 best = 4;
781 break;
782 case (DMA_PRIO_LOW):
783 default:
784 best = 0;
785 break;
786 }
787
788 for (i = best; i < IMX_DMA_CHANNELS; i++)
789 if (!imx_dma_request(i, name))
790 return i;
791
792 for (i = best - 1; i >= 0; i--)
793 if (!imx_dma_request(i, name))
794 return i;
795
796 printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
797
798 return -ENODEV;
799}
800EXPORT_SYMBOL(imx_dma_request_by_prio);
801
802static int __init imx_dma_init(void)
803{
804 int ret = 0;
805 int i;
806
807#ifdef CONFIG_ARCH_MX1
808 if (cpu_is_mx1())
809 imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
810 else
811#endif
812#ifdef CONFIG_MACH_MX21
813 if (cpu_is_mx21())
814 imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
815 else
816#endif
817#ifdef CONFIG_MACH_MX27
818 if (cpu_is_mx27())
819 imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
820 else
821#endif
822 BUG();
823
824 dma_clk = clk_get(NULL, "dma");
825 clk_enable(dma_clk);
826
827 /* reset DMA module */
828 imx_dmav1_writel(DCR_DRST, DMA_DCR);
829
830#ifdef CONFIG_ARCH_MX1
831 if (cpu_is_mx1()) {
832 ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
833 if (ret) {
834 pr_crit("Wow! Can't register IRQ for DMA\n");
835 return ret;
836 }
837
838 ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL);
839 if (ret) {
840 pr_crit("Wow! Can't register ERRIRQ for DMA\n");
841 free_irq(MX1_DMA_INT, NULL);
842 return ret;
843 }
844 }
845#endif
846 /* enable DMA module */
847 imx_dmav1_writel(DCR_DEN, DMA_DCR);
848
849 /* clear all interrupts */
850 imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
851
852 /* disable interrupts */
853 imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
854
855 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
856 imx_dma_channels[i].sg = NULL;
857 imx_dma_channels[i].dma_num = i;
858 }
859
860 return ret;
861}
862
863arch_initcall(imx_dma_init);
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 618479258bb6..35a064ff02ba 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -11,10 +11,6 @@
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details. 13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */ 14 */
19 15
20#include <linux/platform_device.h> 16#include <linux/platform_device.h>
diff --git a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
deleted file mode 100644
index 0376c133c9f4..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>.
3 * All Rights Reserved.
4 */
5
6/*
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
13#define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
14
15#endif
diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
index a1fd5830af48..45b2fb8bed61 100644
--- a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
+++ b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
@@ -25,7 +25,7 @@
25#ifndef __ASSEMBLY__ 25#ifndef __ASSEMBLY__
26/* 26/*
27 * This CPU module needs a baseboard to work. After basic initializing 27 * This CPU module needs a baseboard to work. After basic initializing
28 * its own devices, it calls baseboard's init function. 28 * its own devices, it calls the baseboard's init function.
29 * TODO: Add your own baseboard init function and call it from 29 * TODO: Add your own baseboard init function and call it from
30 * inside eukrea_cpuimx27_init(). 30 * inside eukrea_cpuimx27_init().
31 * 31 *
diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
deleted file mode 100644
index 93cc66f104c7..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18#ifndef __ARM_ARCH_BOARD_KZM_ARM11_H
19#define __ARM_ARCH_BOARD_KZM_ARM11_H
20
21/*
22 * KZM-ARM11-01 Board Control Registers on FPGA
23 */
24#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000)
25#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001)
26#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002)
27#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004)
28#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008)
29#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010)
30#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020)
31#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003)
32
33/*
34 * External UART for touch panel on FPGA
35 */
36#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
37
38#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */
39
diff --git a/arch/arm/plat-mxc/include/mach/board-mx21ads.h b/arch/arm/plat-mxc/include/mach/board-mx21ads.h
deleted file mode 100644
index 0cf4fa29510c..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx21ads.h
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__
15#define __ASM_ARCH_MXC_BOARD_MX21ADS_H__
16
17/*
18 * Memory-mapped I/O on MX21ADS base board
19 */
20#define MX21ADS_MMIO_BASE_ADDR 0xF5000000
21#define MX21ADS_MMIO_SIZE SZ_16M
22
23#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \
24 (MX21ADS_MMIO_BASE_ADDR + (offset))
25
26#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11)
27#define MX21ADS_CS8900A_IOBASE_REG MX21ADS_REG_ADDR(0x000000)
28#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
29#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000)
30#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000)
31
32/* MX21ADS_IO_REG bit definitions */
33#define MX21ADS_IO_SD_WP 0x0001 /* read */
34#define MX21ADS_IO_TP6 0x0001 /* write */
35#define MX21ADS_IO_SW_SEL 0x0002 /* read */
36#define MX21ADS_IO_TP7 0x0002 /* write */
37#define MX21ADS_IO_RESET_E_UART 0x0004
38#define MX21ADS_IO_RESET_BASE 0x0008
39#define MX21ADS_IO_CSI_CTL2 0x0010
40#define MX21ADS_IO_CSI_CTL1 0x0020
41#define MX21ADS_IO_CSI_CTL0 0x0040
42#define MX21ADS_IO_UART1_EN 0x0080
43#define MX21ADS_IO_UART4_EN 0x0100
44#define MX21ADS_IO_LCDON 0x0200
45#define MX21ADS_IO_IRDA_EN 0x0400
46#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
47#define MX21ADS_IO_IRDA_MD0_B 0x1000
48#define MX21ADS_IO_IRDA_MD1 0x2000
49#define MX21ADS_IO_LED4_ON 0x4000
50#define MX21ADS_IO_LED3_ON 0x8000
51
52#endif /* __ASM_ARCH_MXC_BOARD_MX21ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
deleted file mode 100644
index 7776d230327f..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h
+++ /dev/null
@@ -1,344 +0,0 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
15#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
16
17/* external interrupt multiplexer */
18#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
19
20#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
21#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE
22#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1)
23#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2)
24
25#define MXC_MAX_BOARD_INTS (MXC_MAX_EXP_IO_LINES + \
26 MXC_MAX_VIRTUAL_INTS)
27
28/*
29 * @name Memory Size parameters
30 */
31
32/*
33 * Size of SDRAM memory
34 */
35#define SDRAM_MEM_SIZE SZ_128M
36
37/*
38 * PBC Controller parameters
39 */
40
41/*
42 * Base address of PBC controller, CS4
43 */
44#define PBC_BASE_ADDRESS 0xf4300000
45#define PBC_REG_ADDR(offset) (void __force __iomem *) \
46 (PBC_BASE_ADDRESS + (offset))
47
48/*
49 * PBC Interupt name definitions
50 */
51#define PBC_GPIO1_0 0
52#define PBC_GPIO1_1 1
53#define PBC_GPIO1_2 2
54#define PBC_GPIO1_3 3
55#define PBC_GPIO1_4 4
56#define PBC_GPIO1_5 5
57
58#define PBC_INTR_MAX_NUM 6
59#define PBC_INTR_SHARED_MAX_NUM 8
60
61/* When the PBC address connection is fixed in h/w, defined as 1 */
62#define PBC_ADDR_SH 0
63
64/* Offsets for the PBC Controller register */
65/*
66 * PBC Board version register offset
67 */
68#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
69/*
70 * PBC Board control register 1 set address.
71 */
72#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
73/*
74 * PBC Board control register 1 clear address.
75 */
76#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
77/*
78 * PBC Board control register 2 set address.
79 */
80#define PBC_BCTRL2_SET_REG PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
81/*
82 * PBC Board control register 2 clear address.
83 */
84#define PBC_BCTRL2_CLEAR_REG PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
85/*
86 * PBC Board control register 3 set address.
87 */
88#define PBC_BCTRL3_SET_REG PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
89/*
90 * PBC Board control register 3 clear address.
91 */
92#define PBC_BCTRL3_CLEAR_REG PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
93/*
94 * PBC Board control register 3 set address.
95 */
96#define PBC_BCTRL4_SET_REG PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
97/*
98 * PBC Board control register 4 clear address.
99 */
100#define PBC_BCTRL4_CLEAR_REG PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
101/*PBC_ADDR_SH
102 * PBC Board status register 1.
103 */
104#define PBC_BSTAT1_REG PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
105/*
106 * PBC Board interrupt status register.
107 */
108#define PBC_INTSTATUS_REG PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
109/*
110 * PBC Board interrupt current status register.
111 */
112#define PBC_INTCURR_STATUS_REG PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
113/*
114 * PBC Interrupt mask register set address.
115 */
116#define PBC_INTMASK_SET_REG PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
117/*
118 * PBC Interrupt mask register clear address.
119 */
120#define PBC_INTMASK_CLEAR_REG PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
121/*
122 * External UART A.
123 */
124#define PBC_SC16C652_UARTA_REG PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
125/*
126 * UART 4 Expanding Signal Status.
127 */
128#define PBC_UART_STATUS_REG PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
129/*
130 * UART 4 Expanding Signal Control Set.
131 */
132#define PBC_UCTRL_SET_REG PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
133/*
134 * UART 4 Expanding Signal Control Clear.
135 */
136#define PBC_UCTRL_CLR_REG PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
137/*
138 * Ethernet Controller IO base address.
139 */
140#define PBC_CS8900A_IOBASE_REG PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
141/*
142 * Ethernet Controller Memory base address.
143 */
144#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
145/*
146 * Ethernet Controller DMA base address.
147 */
148#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
149
150/* PBC Board Version Register bit definition */
151#define PBC_VERSION_ADS 0x8000 /* Bit15=1 means version for ads */
152#define PBC_VERSION_EVB_REVB 0x4000 /* BIT14=1 means version for evb revb */
153
154/* PBC Board Control Register 1 bit definitions */
155#define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */
156#define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */
157#define PBC_BCTRL1_FRST 0x0004 /* FEC Reset */
158#define PBC_BCTRL1_ESLEEP 0x0010 /* Enable ethernet Sleep */
159#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
160
161/* PBC Board Control Register 2 bit definitions */
162#define PBC_BCTRL2_VCC_EN 0x0004 /* Enable VCC */
163#define PBC_BCTRL2_VPP_EN 0x0008 /* Enable Vpp */
164#define PBC_BCTRL2_ATAFEC_EN 0X0010
165#define PBC_BCTRL2_ATAFEC_SEL 0X0020
166#define PBC_BCTRL2_ATA_EN 0X0040
167#define PBC_BCTRL2_IRDA_SD 0X0080
168#define PBC_BCTRL2_IRDA_EN 0X0100
169#define PBC_BCTRL2_CCTL10 0X0200
170#define PBC_BCTRL2_CCTL11 0X0400
171
172/* PBC Board Control Register 3 bit definitions */
173#define PBC_BCTRL3_HSH_EN 0X0020
174#define PBC_BCTRL3_FSH_MOD 0X0040
175#define PBC_BCTRL3_OTG_HS_EN 0X0080
176#define PBC_BCTRL3_OTG_VBUS_EN 0X0100
177#define PBC_BCTRL3_FSH_VBUS_EN 0X0200
178#define PBC_BCTRL3_USB_OTG_ON 0X0800
179#define PBC_BCTRL3_USB_FSH_ON 0X1000
180
181/* PBC Board Control Register 4 bit definitions */
182#define PBC_BCTRL4_REGEN_SEL 0X0001
183#define PBC_BCTRL4_USER_OFF 0X0002
184#define PBC_BCTRL4_VIB_EN 0X0004
185#define PBC_BCTRL4_PWRGT1_EN 0X0008
186#define PBC_BCTRL4_PWRGT2_EN 0X0010
187#define PBC_BCTRL4_STDBY_PRI 0X0020
188
189#ifndef __ASSEMBLY__
190/*
191 * Enumerations for SD cards and memory stick card. This corresponds to
192 * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
193 */
194enum mxc_card_no {
195 MXC_CARD_SD2 = 0,
196 MXC_CARD_SD3,
197 MXC_CARD_MS,
198 MXC_CARD_SD1,
199 MXC_CARD_MIN = MXC_CARD_SD2,
200 MXC_CARD_MAX = MXC_CARD_SD1,
201};
202#endif
203
204#define MXC_CPLD_VER_1_50 0x01
205
206/*
207 * PBC BSTAT Register bit definitions
208 */
209#define PBC_BSTAT_PRI_INT 0X0001
210#define PBC_BSTAT_USB_BYP 0X0002
211#define PBC_BSTAT_ATA_IOCS16 0X0004
212#define PBC_BSTAT_ATA_CBLID 0X0008
213#define PBC_BSTAT_ATA_DASP 0X0010
214#define PBC_BSTAT_PWR_RDY 0X0020
215#define PBC_BSTAT_SD3_WP 0X0100
216#define PBC_BSTAT_SD2_WP 0X0200
217#define PBC_BSTAT_SD1_WP 0X0400
218#define PBC_BSTAT_SD3_DET 0X0800
219#define PBC_BSTAT_SD2_DET 0X1000
220#define PBC_BSTAT_SD1_DET 0X2000
221#define PBC_BSTAT_MS_DET 0X4000
222#define PBC_BSTAT_SD3_DET_BIT 11
223#define PBC_BSTAT_SD2_DET_BIT 12
224#define PBC_BSTAT_SD1_DET_BIT 13
225#define PBC_BSTAT_MS_DET_BIT 14
226#define MXC_BSTAT_BIT(n) ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
227 ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
228 ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
229 ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
230 0x0))))
231
232/*
233 * PBC UART Control Register bit definitions
234 */
235#define PBC_UCTRL_DCE_DCD 0X0001
236#define PBC_UCTRL_DCE_DSR 0X0002
237#define PBC_UCTRL_DCE_RI 0X0004
238#define PBC_UCTRL_DTE_DTR 0X0100
239
240/*
241 * PBC UART Status Register bit definitions
242 */
243#define PBC_USTAT_DTE_DCD 0X0001
244#define PBC_USTAT_DTE_DSR 0X0002
245#define PBC_USTAT_DTE_RI 0X0004
246#define PBC_USTAT_DCE_DTR 0X0100
247
248/*
249 * PBC Interupt mask register bit definitions
250 */
251#define PBC_INTR_SD3_R_EN_BIT 4
252#define PBC_INTR_SD2_R_EN_BIT 0
253#define PBC_INTR_SD1_R_EN_BIT 6
254#define PBC_INTR_MS_R_EN_BIT 5
255#define PBC_INTR_SD3_EN_BIT 13
256#define PBC_INTR_SD2_EN_BIT 12
257#define PBC_INTR_MS_EN_BIT 14
258#define PBC_INTR_SD1_EN_BIT 15
259
260#define PBC_INTR_SD2_R_EN 0x0001
261#define PBC_INTR_LOW_BAT 0X0002
262#define PBC_INTR_OTG_FSOVER 0X0004
263#define PBC_INTR_FSH_OVER 0X0008
264#define PBC_INTR_SD3_R_EN 0x0010
265#define PBC_INTR_MS_R_EN 0x0020
266#define PBC_INTR_SD1_R_EN 0x0040
267#define PBC_INTR_FEC_INT 0X0080
268#define PBC_INTR_ENET_INT 0X0100
269#define PBC_INTR_OTGFS_INT 0X0200
270#define PBC_INTR_XUART_INT 0X0400
271#define PBC_INTR_CCTL12 0X0800
272#define PBC_INTR_SD2_EN 0x1000
273#define PBC_INTR_SD3_EN 0x2000
274#define PBC_INTR_MS_EN 0x4000
275#define PBC_INTR_SD1_EN 0x8000
276
277
278
279/* For interrupts like xuart, enet etc */
280#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX27_PIN_TIN)
281#define MXC_MAX_EXP_IO_LINES 16
282
283/*
284 * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
285 *
286 */
287#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 1)
288#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
289#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
290#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
291#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
292#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
293#define EXPIO_INT_FEC (MXC_EXP_IO_BASE + 7)
294#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
295#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
296#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
297#define EXPIO_INT_CCTL12_INT (MXC_EXP_IO_BASE + 11)
298#define EXPIO_INT_SD2_EN (MXC_EXP_IO_BASE + 12)
299#define EXPIO_INT_SD3_EN (MXC_EXP_IO_BASE + 13)
300#define EXPIO_INT_MS_EN (MXC_EXP_IO_BASE + 14)
301#define EXPIO_INT_SD1_EN (MXC_EXP_IO_BASE + 15)
302
303/*
304 * This is System IRQ used by CS8900A for interrupt generation
305 * taken from platform.h
306 */
307#define CS8900AIRQ EXPIO_INT_ENET_INT
308/* This is I/O Base address used to access registers of CS8900A on MXC ADS */
309#define CS8900A_BASE_ADDRESS (PBC_CS8900A_IOBASE_REG + 0x300)
310
311#define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX27_PIN_TOUT)
312
313/*
314* This is used to detect if the CPLD version is for mx27 evb board rev-a
315*/
316#define PBC_CPLD_VERSION_IS_REVA() \
317 ((__raw_readw(PBC_VERSION_REG) & \
318 (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
319 == 0)
320
321/* This is used to active or inactive ata signal in CPLD .
322 * It is dependent with hardware
323 */
324#define PBC_ATA_SIGNAL_ACTIVE() \
325 __raw_writew( \
326 PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
327 PBC_BCTRL2_CLEAR_REG)
328
329#define PBC_ATA_SIGNAL_INACTIVE() \
330 __raw_writew( \
331 PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
332 PBC_BCTRL2_SET_REG)
333
334#define MXC_BD_LED1 (1 << 5)
335#define MXC_BD_LED2 (1 << 6)
336#define MXC_BD_LED_ON(led) \
337 __raw_writew(led, PBC_BCTRL1_SET_REG)
338#define MXC_BD_LED_OFF(led) \
339 __raw_writew(led, PBC_BCTRL1_CLEAR_REG)
340
341/* to determine the correct external crystal reference */
342#define CKIH_27MHZ_BIT_SET (1 << 3)
343
344#endif /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27lite.h b/arch/arm/plat-mxc/include/mach/board-mx27lite.h
deleted file mode 100644
index ea87551d2736..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27lite.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__
12#define __ASM_ARCH_MXC_BOARD_MX27LITE_H__
13
14#endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
deleted file mode 100644
index fec1bcfa9164..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__
12#define __ASM_ARCH_MXC_BOARD_MX27PDK_H__
13
14#endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
deleted file mode 100644
index da92933a233b..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
12#define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
13
14/* Definitions for components on the Debug board */
15
16/* Base address of CPLD controller on the Debug board */
17#define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(CS5_BASE_ADDR)
18
19/* LAN9217 ethernet base address */
20#define LAN9217_BASE_ADDR CS5_BASE_ADDR
21
22/* CPLD config and interrupt base address */
23#define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000)
24
25/* LED switchs */
26#define CPLD_LED_REG (CPLD_ADDR + 0x00)
27/* buttons */
28#define CPLD_SWITCH_BUTTONS_REG (EXPIO_ADDR + 0x08)
29/* status, interrupt */
30#define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10)
31#define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38)
32#define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20)
33/* magic word for debug CPLD */
34#define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40)
35#define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48)
36/* CPLD code version */
37#define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50)
38/* magic word for debug CPLD */
39#define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58)
40/* module reset register */
41#define CPLD_MODULE_RESET_REG (CPLD_ADDR + 0x60)
42/* CPU ID and Personality ID */
43#define CPLD_MCU_BOARD_ID_REG (CPLD_ADDR + 0x68)
44
45/* CPLD IRQ line for external uart, external ethernet etc */
46#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
47
48#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
49#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
50
51#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0)
52#define EXPIO_INT_XUART_A (MXC_EXP_IO_BASE + 1)
53#define EXPIO_INT_XUART_B (MXC_EXP_IO_BASE + 2)
54#define EXPIO_INT_BUTTON_A (MXC_EXP_IO_BASE + 3)
55#define EXPIO_INT_BUTTON_B (MXC_EXP_IO_BASE + 4)
56
57#define MXC_MAX_EXP_IO_LINES 16
58
59#endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
deleted file mode 100644
index 095a199591c6..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
12#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
13
14#include <mach/hardware.h>
15
16/* Base address of PBC controller */
17#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
18/* Offsets for the PBC Controller register */
19
20/* PBC Board status register offset */
21#define PBC_BSTAT 0x000002
22
23/* PBC Board control register 1 set address */
24#define PBC_BCTRL1_SET 0x000004
25
26/* PBC Board control register 1 clear address */
27#define PBC_BCTRL1_CLEAR 0x000006
28
29/* PBC Board control register 2 set address */
30#define PBC_BCTRL2_SET 0x000008
31
32/* PBC Board control register 2 clear address */
33#define PBC_BCTRL2_CLEAR 0x00000A
34
35/* PBC Board control register 3 set address */
36#define PBC_BCTRL3_SET 0x00000C
37
38/* PBC Board control register 3 clear address */
39#define PBC_BCTRL3_CLEAR 0x00000E
40
41/* PBC Board control register 4 set address */
42#define PBC_BCTRL4_SET 0x000010
43
44/* PBC Board control register 4 clear address */
45#define PBC_BCTRL4_CLEAR 0x000012
46
47/* PBC Board status register 1 */
48#define PBC_BSTAT1 0x000014
49
50/* PBC Board interrupt status register */
51#define PBC_INTSTATUS 0x000016
52
53/* PBC Board interrupt current status register */
54#define PBC_INTCURR_STATUS 0x000018
55
56/* PBC Interrupt mask register set address */
57#define PBC_INTMASK_SET 0x00001A
58
59/* PBC Interrupt mask register clear address */
60#define PBC_INTMASK_CLEAR 0x00001C
61
62/* External UART A */
63#define PBC_SC16C652_UARTA 0x010000
64
65/* External UART B */
66#define PBC_SC16C652_UARTB 0x010010
67
68/* Ethernet Controller IO base address */
69#define PBC_CS8900A_IOBASE 0x020000
70
71/* Ethernet Controller Memory base address */
72#define PBC_CS8900A_MEMBASE 0x021000
73
74/* Ethernet Controller DMA base address */
75#define PBC_CS8900A_DMABASE 0x022000
76
77/* External chip select 0 */
78#define PBC_XCS0 0x040000
79
80/* LCD Display enable */
81#define PBC_LCD_EN_B 0x060000
82
83/* Code test debug enable */
84#define PBC_CODE_B 0x070000
85
86/* PSRAM memory select */
87#define PBC_PSRAM_B 0x5000000
88
89#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
90#define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
91#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
92#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
93#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
94
95#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
96#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
97
98#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0)
99#define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1)
100#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
101#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
102#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
103#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
104#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
105#define EXPIO_INT_RES7 (MXC_EXP_IO_BASE + 7)
106#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
107#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
108#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
109#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
110#define EXPIO_INT_SYNTH_IRQ (MXC_EXP_IO_BASE + 12)
111#define EXPIO_INT_CE_INT1 (MXC_EXP_IO_BASE + 13)
112#define EXPIO_INT_CE_INT2 (MXC_EXP_IO_BASE + 14)
113#define EXPIO_INT_RES15 (MXC_EXP_IO_BASE + 15)
114
115#define MXC_MAX_EXP_IO_LINES 16
116
117#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
index eb5a5024622e..0df71bfefbb1 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
@@ -31,7 +31,7 @@ enum mx31lilly_boards {
31 31
32/* 32/*
33 * This CPU module needs a baseboard to work. After basic initializing 33 * This CPU module needs a baseboard to work. After basic initializing
34 * its own devices, it calls baseboard's init function. 34 * its own devices, it calls the baseboard's init function.
35 */ 35 */
36 36
37extern void mx31lilly_db_init(void); 37extern void mx31lilly_db_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index 2b2da0367578..c1ad0ae807cc 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -32,7 +32,7 @@ enum mx31lite_boards {
32 32
33/* 33/*
34 * This CPU module needs a baseboard to work. After basic initializing 34 * This CPU module needs a baseboard to work. After basic initializing
35 * its own devices, it calls baseboard's init function. 35 * its own devices, it calls the baseboard's init function.
36 */ 36 */
37 37
38extern void mx31lite_db_init(void); 38extern void mx31lite_db_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
index 36ff3cedee1a..de14543891cf 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -31,7 +31,7 @@ enum mx31moboard_boards {
31 31
32/* 32/*
33 * This CPU module needs a baseboard to work. After basic initializing 33 * This CPU module needs a baseboard to work. After basic initializing
34 * its own devices, it calls baseboard's init function. 34 * its own devices, it calls the baseboard's init function.
35 */ 35 */
36 36
37extern void mx31moboard_devboard_init(void); 37extern void mx31moboard_devboard_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
deleted file mode 100644
index 383f1c04df06..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__
20#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__
21
22#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm037.h b/arch/arm/plat-mxc/include/mach/board-pcm037.h
deleted file mode 100644
index 13411709b13a..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-pcm037.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
20#define __ASM_ARCH_MXC_BOARD_PCM037_H__
21
22#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h
index 410f9786ed22..6f371e35753d 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm038.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h
@@ -22,7 +22,7 @@
22#ifndef __ASSEMBLY__ 22#ifndef __ASSEMBLY__
23/* 23/*
24 * This CPU module needs a baseboard to work. After basic initializing 24 * This CPU module needs a baseboard to work. After basic initializing
25 * its own devices, it calls baseboard's init function. 25 * its own devices, it calls the baseboard's init function.
26 * TODO: Add your own baseboard init function and call it from 26 * TODO: Add your own baseboard init function and call it from
27 * inside pcm038_init(). 27 * inside pcm038_init().
28 * 28 *
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm043.h b/arch/arm/plat-mxc/include/mach/board-pcm043.h
deleted file mode 100644
index 1ac4e1682e5c..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-pcm043.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__
20#define __ASM_ARCH_MXC_BOARD_PCM043_H__
21
22#endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h
deleted file mode 100644
index 6d88c7af4b23..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-qong.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_QONG_H__
12#define __ASM_ARCH_MXC_BOARD_QONG_H__
13
14/* NOR FLASH */
15#define QONG_NOR_SIZE (128*1024*1024)
16
17#endif /* __ASM_ARCH_MXC_BOARD_QONG_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
new file mode 100644
index 000000000000..05c8d3f0a08f
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -0,0 +1,42 @@
1/*
2 * Copyright (C) 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <linux/kernel.h>
10#include <linux/platform_device.h>
11#include <linux/init.h>
12
13struct platform_device *imx_add_platform_device(const char *name, int id,
14 const struct resource *res, unsigned int num_resources,
15 const void *data, size_t size_data);
16
17#include <mach/i2c.h>
18struct platform_device *__init imx_add_imx_i2c(int id,
19 resource_size_t iobase, resource_size_t iosize, int irq,
20 const struct imxi2c_platform_data *pdata);
21
22#include <mach/imx-uart.h>
23struct platform_device *__init imx_add_imx_uart_3irq(int id,
24 resource_size_t iobase, resource_size_t iosize,
25 resource_size_t irqrx, resource_size_t irqtx,
26 resource_size_t irqrts,
27 const struct imxuart_platform_data *pdata);
28struct platform_device *__init imx_add_imx_uart_1irq(int id,
29 resource_size_t iobase, resource_size_t iosize,
30 resource_size_t irq,
31 const struct imxuart_platform_data *pdata);
32
33#include <mach/mxc_nand.h>
34struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
35 int irq, const struct mxc_nand_platform_data *pdata);
36struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
37 int irq, const struct mxc_nand_platform_data *pdata);
38
39#include <mach/spi.h>
40struct platform_device *__init imx_add_spi_imx(int id,
41 resource_size_t iobase, resource_size_t iosize, int irq,
42 const struct spi_imx_master *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
deleted file mode 100644
index 7c4870bd5a21..000000000000
--- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * linux/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
3 *
4 * i.MX DMA registration and IRQ dispatching
5 *
6 * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
7 * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
8 * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301, USA.
23 */
24
25#ifndef __ASM_ARCH_MXC_DMA_H
26#define __ASM_ARCH_MXC_DMA_H
27
28#define IMX_DMA_CHANNELS 16
29
30#define DMA_MODE_READ 0
31#define DMA_MODE_WRITE 1
32#define DMA_MODE_MASK 1
33
34#define MX1_DMA_REG(offset) MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
35
36/* DMA Interrupt Mask Register */
37#define MX1_DMA_DIMR MX1_DMA_REG(0x08)
38
39/* Channel Control Register */
40#define MX1_DMA_CCR(x) MX1_DMA_REG(0x8c + ((x) << 6))
41
42#define IMX_DMA_MEMSIZE_32 (0 << 4)
43#define IMX_DMA_MEMSIZE_8 (1 << 4)
44#define IMX_DMA_MEMSIZE_16 (2 << 4)
45#define IMX_DMA_TYPE_LINEAR (0 << 10)
46#define IMX_DMA_TYPE_2D (1 << 10)
47#define IMX_DMA_TYPE_FIFO (2 << 10)
48
49#define IMX_DMA_ERR_BURST (1 << 0)
50#define IMX_DMA_ERR_REQUEST (1 << 1)
51#define IMX_DMA_ERR_TRANSFER (1 << 2)
52#define IMX_DMA_ERR_BUFFER (1 << 3)
53#define IMX_DMA_ERR_TIMEOUT (1 << 4)
54
55int
56imx_dma_config_channel(int channel, unsigned int config_port,
57 unsigned int config_mem, unsigned int dmareq, int hw_chaining);
58
59void
60imx_dma_config_burstlen(int channel, unsigned int burstlen);
61
62int
63imx_dma_setup_single(int channel, dma_addr_t dma_address,
64 unsigned int dma_length, unsigned int dev_addr,
65 unsigned int dmamode);
66
67
68/*
69 * Use this flag as the dma_length argument to imx_dma_setup_sg()
70 * to create an endless running dma loop. The end of the scatterlist
71 * must be linked to the beginning for this to work.
72 */
73#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
74
75int
76imx_dma_setup_sg(int channel, struct scatterlist *sg,
77 unsigned int sgcount, unsigned int dma_length,
78 unsigned int dev_addr, unsigned int dmamode);
79
80int
81imx_dma_setup_handlers(int channel,
82 void (*irq_handler) (int, void *),
83 void (*err_handler) (int, void *, int), void *data);
84
85int
86imx_dma_setup_progression_handler(int channel,
87 void (*prog_handler) (int, void*, struct scatterlist*));
88
89void imx_dma_enable(int channel);
90
91void imx_dma_disable(int channel);
92
93int imx_dma_request(int channel, const char *name);
94
95void imx_dma_free(int channel);
96
97enum imx_dma_prio {
98 DMA_PRIO_HIGH = 0,
99 DMA_PRIO_MEDIUM = 1,
100 DMA_PRIO_LOW = 2
101};
102
103int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
104
105#endif /* _ASM_ARCH_MXC_DMA_H */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
index 3887f3fe29d4..15d59510f597 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 15 */
20 16
21#ifndef __MACH_IOMUX_MXC91231_H__ 17#ifndef __MACH_IOMUX_MXC91231_H__
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 5eba7e6785de..641b24618239 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -91,24 +91,24 @@
91#define MX1_SIM_DATA_INT 16 91#define MX1_SIM_DATA_INT 16
92#define MX1_RTC_INT 17 92#define MX1_RTC_INT 17
93#define MX1_RTC_SAMINT 18 93#define MX1_RTC_SAMINT 18
94#define MX1_UART2_MINT_PFERR 19 94#define MX1_INT_UART2PFERR 19
95#define MX1_UART2_MINT_RTS 20 95#define MX1_INT_UART2RTS 20
96#define MX1_UART2_MINT_DTR 21 96#define MX1_INT_UART2DTR 21
97#define MX1_UART2_MINT_UARTC 22 97#define MX1_INT_UART2UARTC 22
98#define MX1_UART2_MINT_TX 23 98#define MX1_INT_UART2TX 23
99#define MX1_UART2_MINT_RX 24 99#define MX1_INT_UART2RX 24
100#define MX1_UART1_MINT_PFERR 25 100#define MX1_INT_UART1PFERR 25
101#define MX1_UART1_MINT_RTS 26 101#define MX1_INT_UART1RTS 26
102#define MX1_UART1_MINT_DTR 27 102#define MX1_INT_UART1DTR 27
103#define MX1_UART1_MINT_UARTC 28 103#define MX1_INT_UART1UARTC 28
104#define MX1_UART1_MINT_TX 29 104#define MX1_INT_UART1TX 29
105#define MX1_UART1_MINT_RX 30 105#define MX1_INT_UART1RX 30
106#define MX1_VOICE_DAC_INT 31 106#define MX1_VOICE_DAC_INT 31
107#define MX1_VOICE_ADC_INT 32 107#define MX1_VOICE_ADC_INT 32
108#define MX1_PEN_DATA_INT 33 108#define MX1_PEN_DATA_INT 33
109#define MX1_PWM_INT 34 109#define MX1_PWM_INT 34
110#define MX1_SDHC_INT 35 110#define MX1_SDHC_INT 35
111#define MX1_I2C_INT 39 111#define MX1_INT_I2C 39
112#define MX1_CSPI_INT 41 112#define MX1_CSPI_INT 41
113#define MX1_SSI_TX_INT 42 113#define MX1_SSI_TX_INT 42
114#define MX1_SSI_TX_ERR_INT 43 114#define MX1_SSI_TX_ERR_INT 43
@@ -245,7 +245,7 @@
245#define PEN_DATA_INT MX1_PEN_DATA_INT 245#define PEN_DATA_INT MX1_PEN_DATA_INT
246#define PWM_INT MX1_PWM_INT 246#define PWM_INT MX1_PWM_INT
247#define SDHC_INT MX1_SDHC_INT 247#define SDHC_INT MX1_SDHC_INT
248#define I2C_INT MX1_I2C_INT 248#define I2C_INT MX1_INT_I2C
249#define CSPI_INT MX1_CSPI_INT 249#define CSPI_INT MX1_CSPI_INT
250#define SSI_TX_INT MX1_SSI_TX_INT 250#define SSI_TX_INT MX1_SSI_TX_INT
251#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT 251#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 7516f2949afe..2f2aad1032c1 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -11,6 +11,10 @@
11#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000 11#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000
12#define MX25_AVIC_SIZE SZ_1M 12#define MX25_AVIC_SIZE SZ_1M
13 13
14#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
15#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
16#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
17#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
14#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) 18#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
15 19
16#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) 20#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
@@ -30,7 +34,12 @@
30#define MX25_UART1_BASE_ADDR 0x43f90000 34#define MX25_UART1_BASE_ADDR 0x43f90000
31#define MX25_UART2_BASE_ADDR 0x43f94000 35#define MX25_UART2_BASE_ADDR 0x43f94000
32#define MX25_AUDMUX_BASE_ADDR 0x43fb0000 36#define MX25_AUDMUX_BASE_ADDR 0x43fb0000
37#define MX25_UART3_BASE_ADDR 0x5000c000
38#define MX25_UART4_BASE_ADDR 0x50008000
39#define MX25_UART5_BASE_ADDR 0x5002c000
33 40
41#define MX25_CSPI3_BASE_ADDR 0x50004000
42#define MX25_CSPI2_BASE_ADDR 0x50010000
34#define MX25_FEC_BASE_ADDR 0x50038000 43#define MX25_FEC_BASE_ADDR 0x50038000
35#define MX25_SSI2_BASE_ADDR 0x50014000 44#define MX25_SSI2_BASE_ADDR 0x50014000
36#define MX25_SSI1_BASE_ADDR 0x50034000 45#define MX25_SSI1_BASE_ADDR 0x50034000
@@ -41,14 +50,25 @@
41#define MX25_OTG_BASE_ADDR 0x53ff4000 50#define MX25_OTG_BASE_ADDR 0x53ff4000
42#define MX25_CSI_BASE_ADDR 0x53ff8000 51#define MX25_CSI_BASE_ADDR 0x53ff8000
43 52
44#define MX25_INT_SSI2 11 53#define MX25_INT_CSPI3 0
45#define MX25_INT_SSI1 12 54#define MX25_INT_I2C1 3
46#define MX25_INT_CSI 17 55#define MX25_INT_I2C2 4
47#define MX25_INT_DRYICE 25 56#define MX25_INT_UART4 5
48#define MX25_INT_NANDFC 33 57#define MX25_INT_I2C3 10
49#define MX25_INT_LCDC 39 58#define MX25_INT_SSI2 11
50#define MX25_INT_KPP 24 59#define MX25_INT_SSI1 12
51#define MX25_INT_FEC 57 60#define MX25_INT_CSPI2 13
61#define MX25_INT_CSPI1 14
62#define MX25_INT_CSI 17
63#define MX25_INT_UART3 18
64#define MX25_INT_KPP 24
65#define MX25_INT_DRYICE 25
66#define MX25_INT_UART2 32
67#define MX25_INT_NANDFC 33
68#define MX25_INT_LCDC 39
69#define MX25_INT_UART5 40
70#define MX25_INT_UART1 45
71#define MX25_INT_FEC 57
52 72
53#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS) 73#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS)
54#define UART1_BASE_ADDR MX25_UART1_BASE_ADDR 74#define UART1_BASE_ADDR MX25_UART1_BASE_ADDR
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index bae9cd75beee..a8ab2e02a8ca 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -48,7 +48,7 @@
48#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) 48#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
49#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) 49#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
50#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) 50#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
51#define MX27_I2C_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) 51#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
52#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) 52#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
53#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) 53#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
54#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) 54#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
@@ -150,7 +150,7 @@ static inline void mx27_setup_weimcs(size_t cs,
150#define MX27_INT_SDHC3 9 150#define MX27_INT_SDHC3 9
151#define MX27_INT_SDHC2 10 151#define MX27_INT_SDHC2 10
152#define MX27_INT_SDHC1 11 152#define MX27_INT_SDHC1 11
153#define MX27_INT_I2C 12 153#define MX27_INT_I2C1 12
154#define MX27_INT_SSI2 13 154#define MX27_INT_SSI2 13
155#define MX27_INT_SSI1 14 155#define MX27_INT_SSI1 14
156#define MX27_INT_CSPI2 15 156#define MX27_INT_CSPI2 15
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index fb90e119c2b5..afee3ab9d62e 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -23,7 +23,7 @@
23#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000) 23#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
24#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000) 24#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
25#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) 25#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
26#define MX31_I2C_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) 26#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
27#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) 27#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
28#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) 28#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
29#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) 29#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
@@ -145,7 +145,7 @@ static inline void mx31_setup_weimcs(size_t cs,
145#define MX31_INT_FIRI 7 145#define MX31_INT_FIRI 7
146#define MX31_INT_MMC_SDHC2 8 146#define MX31_INT_MMC_SDHC2 8
147#define MX31_INT_MMC_SDHC1 9 147#define MX31_INT_MMC_SDHC1 9
148#define MX31_INT_I2C 10 148#define MX31_INT_I2C1 10
149#define MX31_INT_SSI2 11 149#define MX31_INT_SSI2 11
150#define MX31_INT_SSI1 12 150#define MX31_INT_SSI1 12
151#define MX31_INT_CSPI2 13 151#define MX31_INT_CSPI2 13
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 526a55842ae5..cda60c715127 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -18,7 +18,7 @@
18#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000) 18#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
19#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000) 19#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
20#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000) 20#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
21#define MX35_I2C_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) 21#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
22#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000) 22#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000)
23#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000) 23#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000)
24#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000) 24#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000)
@@ -123,7 +123,7 @@
123#define MX35_INT_MMC_SDHC1 7 123#define MX35_INT_MMC_SDHC1 7
124#define MX35_INT_MMC_SDHC2 8 124#define MX35_INT_MMC_SDHC2 8
125#define MX35_INT_MMC_SDHC3 9 125#define MX35_INT_MMC_SDHC3 9
126#define MX35_INT_I2C 10 126#define MX35_INT_I2C1 10
127#define MX35_INT_SSI1 11 127#define MX35_INT_SSI1 11
128#define MX35_INT_SSI2 12 128#define MX35_INT_SSI2 12
129#define MX35_INT_CSPI2 13 129#define MX35_INT_CSPI2 13
diff --git a/arch/arm/plat-mxc/include/mach/mx3_camera.h b/arch/arm/plat-mxc/include/mach/mx3_camera.h
index 36d7ff27b5e2..f226ee3777e1 100644
--- a/arch/arm/plat-mxc/include/mach/mx3_camera.h
+++ b/arch/arm/plat-mxc/include/mach/mx3_camera.h
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */ 15 */
20 16
21#ifndef _MX3_CAMERA_H_ 17#ifndef _MX3_CAMERA_H_
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
index 5182b986b785..0ca3101ebf36 100644
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 16 */
21#ifndef __MACH_MXC91231_H__ 17#ifndef __MACH_MXC91231_H__
22#define __MACH_MXC91231_H__ 18#define __MACH_MXC91231_H__
diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h
index 2d74748c5db7..04c0d060d814 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_nand.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h
@@ -23,9 +23,9 @@
23#include <linux/mtd/partitions.h> 23#include <linux/mtd/partitions.h>
24 24
25struct mxc_nand_platform_data { 25struct mxc_nand_platform_data {
26 int width; /* data bus width in bytes */ 26 unsigned int width; /* data bus width in bytes */
27 int hw_ecc:1; /* 0 if supress hardware ECC */ 27 unsigned int hw_ecc:1; /* 0 if supress hardware ECC */
28 int flash_bbt:1; /* set to 1 to use a flash based bbt */ 28 unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
29 struct mtd_partition *parts; /* partition table */ 29 struct mtd_partition *parts; /* partition table */
30 int nr_parts; /* size of parts */ 30 int nr_parts; /* size of parts */
31}; 31};
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index ef00199568de..4acd1143a9bd 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 15 */
20 16
21#ifndef __ASM_ARCH_MXC_SYSTEM_H__ 17#ifndef __ASM_ARCH_MXC_SYSTEM_H__
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 024416ed11cd..2d9624697cc9 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */ 14 */
19 15
20#ifndef __ASM_ARCH_MXC_TIMEX_H__ 16#ifndef __ASM_ARCH_MXC_TIMEX_H__
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index b6d3d0fddc48..d9bd37e4667a 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 16 */
21#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__ 17#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
22#define __ASM_ARCH_MXC_UNCOMPRESS_H__ 18#define __ASM_ARCH_MXC_UNCOMPRESS_H__
diff --git a/arch/arm/plat-mxc/include/mach/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h
index 44243a278434..ef6379c474be 100644
--- a/arch/arm/plat-mxc/include/mach/vmalloc.h
+++ b/arch/arm/plat-mxc/include/mach/vmalloc.h
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */ 14 */
19 15
20#ifndef __ASM_ARCH_MXC_VMALLOC_H__ 16#ifndef __ASM_ARCH_MXC_VMALLOC_H__
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 778ddfe57d89..7331f2ace5fe 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -142,9 +142,6 @@ void __init mxc_init_irq(void __iomem *irqbase)
142 for (i = 0; i < 8; i++) 142 for (i = 0; i < 8; i++)
143 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i)); 143 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
144 144
145 /* init architectures chained interrupt handler */
146 mxc_register_gpios();
147
148#ifdef CONFIG_FIQ 145#ifdef CONFIG_FIQ
149 /* Initialize FIQ */ 146 /* Initialize FIQ */
150 init_FIQ(); 147 init_FIQ();
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 97f42799fa58..925bce4607e7 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -14,10 +14,6 @@
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */ 17 */
22 18
23#include <linux/kernel.h> 19#include <linux/kernel.h>
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 9b86d2a60d43..b3da9aad4295 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -145,8 +145,6 @@ void __init tzic_init_irq(void __iomem *irqbase)
145 set_irq_handler(i, handle_level_irq); 145 set_irq_handler(i, handle_level_irq);
146 set_irq_flags(i, IRQF_VALID); 146 set_irq_flags(i, IRQF_VALID);
147 } 147 }
148 mxc_register_gpios();
149
150 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); 148 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
151} 149}
152 150
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 20:36:36 -0500