diff options
Diffstat (limited to 'arch/arm/plat-mxc/tzic.c')
-rw-r--r-- | arch/arm/plat-mxc/tzic.c | 99 |
1 files changed, 27 insertions, 72 deletions
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index 57f9395f87ce..f257fccdc394 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c | |||
@@ -49,6 +49,8 @@ | |||
49 | 49 | ||
50 | void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ | 50 | void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ |
51 | 51 | ||
52 | #define TZIC_NUM_IRQS 128 | ||
53 | |||
52 | #ifdef CONFIG_FIQ | 54 | #ifdef CONFIG_FIQ |
53 | static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) | 55 | static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) |
54 | { | 56 | { |
@@ -66,78 +68,34 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) | |||
66 | 68 | ||
67 | return 0; | 69 | return 0; |
68 | } | 70 | } |
71 | #else | ||
72 | #define tzic_set_irq_fiq NULL | ||
69 | #endif | 73 | #endif |
70 | 74 | ||
71 | /** | 75 | static unsigned int *wakeup_intr[4]; |
72 | * tzic_mask_irq() - Disable interrupt source "d" in the TZIC | ||
73 | * | ||
74 | * @param d interrupt source | ||
75 | */ | ||
76 | static void tzic_mask_irq(struct irq_data *d) | ||
77 | { | ||
78 | int index, off; | ||
79 | |||
80 | index = d->irq >> 5; | ||
81 | off = d->irq & 0x1F; | ||
82 | __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index)); | ||
83 | } | ||
84 | 76 | ||
85 | /** | 77 | static __init void tzic_init_gc(unsigned int irq_start) |
86 | * tzic_unmask_irq() - Enable interrupt source "d" in the TZIC | ||
87 | * | ||
88 | * @param d interrupt source | ||
89 | */ | ||
90 | static void tzic_unmask_irq(struct irq_data *d) | ||
91 | { | 78 | { |
92 | int index, off; | 79 | struct irq_chip_generic *gc; |
93 | 80 | struct irq_chip_type *ct; | |
94 | index = d->irq >> 5; | 81 | int idx = irq_start >> 5; |
95 | off = d->irq & 0x1F; | 82 | |
96 | __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index)); | 83 | gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base, |
84 | handle_level_irq); | ||
85 | gc->private = tzic_set_irq_fiq; | ||
86 | gc->wake_enabled = IRQ_MSK(32); | ||
87 | wakeup_intr[idx] = &gc->wake_active; | ||
88 | |||
89 | ct = gc->chip_types; | ||
90 | ct->chip.irq_mask = irq_gc_mask_disable_reg; | ||
91 | ct->chip.irq_unmask = irq_gc_unmask_enable_reg; | ||
92 | ct->chip.irq_set_wake = irq_gc_set_wake; | ||
93 | ct->regs.disable = TZIC_ENCLEAR0(idx); | ||
94 | ct->regs.enable = TZIC_ENSET0(idx); | ||
95 | |||
96 | irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); | ||
97 | } | 97 | } |
98 | 98 | ||
99 | static unsigned int wakeup_intr[4]; | ||
100 | |||
101 | /** | ||
102 | * tzic_set_wake_irq() - Set interrupt source "d" in the TZIC as a wake-up source. | ||
103 | * | ||
104 | * @param d interrupt source | ||
105 | * @param enable enable as wake-up if equal to non-zero | ||
106 | * disble as wake-up if equal to zero | ||
107 | * | ||
108 | * @return This function returns 0 on success. | ||
109 | */ | ||
110 | static int tzic_set_wake_irq(struct irq_data *d, unsigned int enable) | ||
111 | { | ||
112 | unsigned int index, off; | ||
113 | |||
114 | index = d->irq >> 5; | ||
115 | off = d->irq & 0x1F; | ||
116 | |||
117 | if (index > 3) | ||
118 | return -EINVAL; | ||
119 | |||
120 | if (enable) | ||
121 | wakeup_intr[index] |= (1 << off); | ||
122 | else | ||
123 | wakeup_intr[index] &= ~(1 << off); | ||
124 | |||
125 | return 0; | ||
126 | } | ||
127 | |||
128 | static struct mxc_irq_chip mxc_tzic_chip = { | ||
129 | .base = { | ||
130 | .name = "MXC_TZIC", | ||
131 | .irq_ack = tzic_mask_irq, | ||
132 | .irq_mask = tzic_mask_irq, | ||
133 | .irq_unmask = tzic_unmask_irq, | ||
134 | .irq_set_wake = tzic_set_wake_irq, | ||
135 | }, | ||
136 | #ifdef CONFIG_FIQ | ||
137 | .set_irq_fiq = tzic_set_irq_fiq, | ||
138 | #endif | ||
139 | }; | ||
140 | |||
141 | /* | 99 | /* |
142 | * This function initializes the TZIC hardware and disables all the | 100 | * This function initializes the TZIC hardware and disables all the |
143 | * interrupts. It registers the interrupt enable and disable functions | 101 | * interrupts. It registers the interrupt enable and disable functions |
@@ -166,11 +124,8 @@ void __init tzic_init_irq(void __iomem *irqbase) | |||
166 | 124 | ||
167 | /* all IRQ no FIQ Warning :: No selection */ | 125 | /* all IRQ no FIQ Warning :: No selection */ |
168 | 126 | ||
169 | for (i = 0; i < MXC_INTERNAL_IRQS; i++) { | 127 | for (i = 0; i < TZIC_NUM_IRQS; i += 32) |
170 | irq_set_chip_and_handler(i, &mxc_tzic_chip.base, | 128 | tzic_init_gc(i); |
171 | handle_level_irq); | ||
172 | set_irq_flags(i, IRQF_VALID); | ||
173 | } | ||
174 | 129 | ||
175 | #ifdef CONFIG_FIQ | 130 | #ifdef CONFIG_FIQ |
176 | /* Initialize FIQ */ | 131 | /* Initialize FIQ */ |
@@ -197,7 +152,7 @@ int tzic_enable_wake(int is_idle) | |||
197 | 152 | ||
198 | for (i = 0; i < 4; i++) { | 153 | for (i = 0; i < 4; i++) { |
199 | v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) : | 154 | v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) : |
200 | wakeup_intr[i]; | 155 | *wakeup_intr[i]; |
201 | __raw_writel(v, tzic_base + TZIC_WAKEUP0(i)); | 156 | __raw_writel(v, tzic_base + TZIC_WAKEUP0(i)); |
202 | } | 157 | } |
203 | 158 | ||