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Diffstat (limited to 'arch/arm/plat-mxc/irq.c')
-rw-r--r--arch/arm/plat-mxc/irq.c34
1 files changed, 22 insertions, 12 deletions
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index c6b837893d87..d862c9e5f8db 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -30,14 +30,7 @@
30#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */ 30#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
31#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */ 31#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
32#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */ 32#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
33#define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */ 33#define AVIC_NIPRIORITY(x) (AVIC_BASE + (0x20 + 4 * (7 - (x)))) /* int priority */
34#define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */
35#define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */
36#define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */
37#define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */
38#define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */
39#define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */
40#define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */
41#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */ 34#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
42#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */ 35#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
43#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */ 36#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
@@ -54,6 +47,24 @@
54#define IIM_PROD_REV_SH 3 47#define IIM_PROD_REV_SH 3
55#define IIM_PROD_REV_LEN 5 48#define IIM_PROD_REV_LEN 5
56 49
50#ifdef CONFIG_MXC_IRQ_PRIOR
51void imx_irq_set_priority(unsigned char irq, unsigned char prio)
52{
53 unsigned int temp;
54 unsigned int mask = 0x0F << irq % 8 * 4;
55
56 if (irq > 63)
57 return;
58
59 temp = __raw_readl(AVIC_NIPRIORITY(irq / 8));
60 temp &= ~mask;
61 temp |= prio & mask;
62
63 __raw_writel(temp, AVIC_NIPRIORITY(irq / 8));
64}
65EXPORT_SYMBOL(imx_irq_set_priority);
66#endif
67
57/* Disable interrupt number "irq" in the AVIC */ 68/* Disable interrupt number "irq" in the AVIC */
58static void mxc_mask_irq(unsigned int irq) 69static void mxc_mask_irq(unsigned int irq)
59{ 70{
@@ -101,10 +112,9 @@ void __init mxc_init_irq(void)
101 set_irq_flags(i, IRQF_VALID); 112 set_irq_flags(i, IRQF_VALID);
102 } 113 }
103 114
104 /* Set WDOG2's interrupt the highest priority level (bit 28-31) */ 115 /* Set default priority value (0) for all IRQ's */
105 reg = __raw_readl(AVIC_NIPRIORITY6); 116 for (i = 0; i < 8; i++)
106 reg |= (0xF << 28); 117 __raw_writel(0, AVIC_NIPRIORITY(i));
107 __raw_writel(reg, AVIC_NIPRIORITY6);
108 118
109 /* init architectures chained interrupt handler */ 119 /* init architectures chained interrupt handler */
110 mxc_register_gpios(); 120 mxc_register_gpios();