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-rw-r--r--arch/arm/plat-mxc/include/mach/3ds_debugboard.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/cpuidle.h22
-rw-r--r--arch/arm/plat-mxc/include/mach/devices-common.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h27
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx3.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx51.h14
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v1.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/ipu.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h44
-rw-r--r--arch/arm/plat-mxc/include/mach/mx1.h111
-rw-r--r--arch/arm/plat-mxc/include/mach/mx21.h107
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h72
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h127
-rw-r--r--arch/arm/plat-mxc/include/mach/mx2x.h87
-rw-r--r--arch/arm/plat-mxc/include/mach/mx31.h118
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h109
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3x.h77
-rw-r--r--arch/arm/plat-mxc/include/mach/mx50.h187
-rw-r--r--arch/arm/plat-mxc/include/mach/mx51.h209
-rw-r--r--arch/arm/plat-mxc/include/mach/mx53.h217
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_ehci.h16
22 files changed, 786 insertions, 785 deletions
diff --git a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
index a384fdd49c62..9fd6cb3f8fad 100644
--- a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
+++ b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
@@ -13,6 +13,6 @@
13#ifndef __ASM_ARCH_MXC_3DS_DB_H__ 13#ifndef __ASM_ARCH_MXC_3DS_DB_H__
14#define __ASM_ARCH_MXC_3DS_DB_H__ 14#define __ASM_ARCH_MXC_3DS_DB_H__
15 15
16extern int __init mxc_expio_init(u32 base, u32 p_irq); 16extern int __init mxc_expio_init(u32 base, u32 intr_gpio);
17 17
18#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */ 18#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index e429ca1b814a..7128e9710417 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -54,6 +54,7 @@ extern void imx50_soc_init(void);
54extern void imx51_soc_init(void); 54extern void imx51_soc_init(void);
55extern void imx53_soc_init(void); 55extern void imx53_soc_init(void);
56extern void imx51_init_late(void); 56extern void imx51_init_late(void);
57extern void imx53_init_late(void);
57extern void epit_timer_init(void __iomem *base, int irq); 58extern void epit_timer_init(void __iomem *base, int irq);
58extern void mxc_timer_init(void __iomem *, int); 59extern void mxc_timer_init(void __iomem *, int);
59extern int mx1_clocks_init(unsigned long fref); 60extern int mx1_clocks_init(unsigned long fref);
@@ -67,6 +68,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
67extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, 68extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
68 unsigned long ckih1, unsigned long ckih2); 69 unsigned long ckih1, unsigned long ckih2);
69extern int mx27_clocks_init_dt(void); 70extern int mx27_clocks_init_dt(void);
71extern int mx31_clocks_init_dt(void);
70extern int mx51_clocks_init_dt(void); 72extern int mx51_clocks_init_dt(void);
71extern int mx53_clocks_init_dt(void); 73extern int mx53_clocks_init_dt(void);
72extern int mx6q_clocks_init(void); 74extern int mx6q_clocks_init(void);
@@ -95,7 +97,6 @@ enum mx3_cpu_pwr_mode {
95}; 97};
96 98
97extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode); 99extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
98extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
99extern void imx_print_silicon_rev(const char *cpu, int srev); 100extern void imx_print_silicon_rev(const char *cpu, int srev);
100 101
101void avic_handle_irq(struct pt_regs *); 102void avic_handle_irq(struct pt_regs *);
@@ -146,8 +147,12 @@ extern void imx6q_clock_map_io(void);
146 147
147#ifdef CONFIG_PM 148#ifdef CONFIG_PM
148extern void imx6q_pm_init(void); 149extern void imx6q_pm_init(void);
150extern void imx51_pm_init(void);
151extern void imx53_pm_init(void);
149#else 152#else
150static inline void imx6q_pm_init(void) {} 153static inline void imx6q_pm_init(void) {}
154static inline void imx51_pm_init(void) {}
155static inline void imx53_pm_init(void) {}
151#endif 156#endif
152 157
153#ifdef CONFIG_NEON 158#ifdef CONFIG_NEON
diff --git a/arch/arm/plat-mxc/include/mach/cpuidle.h b/arch/arm/plat-mxc/include/mach/cpuidle.h
new file mode 100644
index 000000000000..bc932d1af372
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/cpuidle.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/cpuidle.h>
14
15#ifdef CONFIG_CPU_IDLE
16extern int imx_cpuidle_init(struct cpuidle_driver *drv);
17#else
18static inline int imx_cpuidle_init(struct cpuidle_driver *drv)
19{
20 return -ENODEV;
21}
22#endif
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 1b2258daa05b..a7f5bb1084d7 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -183,7 +183,6 @@ struct platform_device *__init imx_add_imx_udc(
183 const struct imx_imx_udc_data *data, 183 const struct imx_imx_udc_data *data,
184 const struct imxusb_platform_data *pdata); 184 const struct imxusb_platform_data *pdata);
185 185
186#include <mach/ipu.h>
187#include <mach/mx3fb.h> 186#include <mach/mx3fb.h>
188#include <mach/mx3_camera.h> 187#include <mach/mx3_camera.h>
189struct imx_ipu_core_data { 188struct imx_ipu_core_data {
@@ -192,8 +191,7 @@ struct imx_ipu_core_data {
192 resource_size_t errirq; 191 resource_size_t errirq;
193}; 192};
194struct platform_device *__init imx_add_ipu_core( 193struct platform_device *__init imx_add_ipu_core(
195 const struct imx_ipu_core_data *data, 194 const struct imx_ipu_core_data *data);
196 const struct ipu_platform_data *pdata);
197struct platform_device *__init imx_alloc_mx3_camera( 195struct platform_device *__init imx_alloc_mx3_camera(
198 const struct imx_ipu_core_data *data, 196 const struct imx_ipu_core_data *data,
199 const struct mx3_camera_pdata *pdata); 197 const struct mx3_camera_pdata *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 0630513554de..ebf10654bb42 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -50,7 +50,7 @@
50 * IO 0x00200000+0x100000 -> 0xf4000000+0x100000 50 * IO 0x00200000+0x100000 -> 0xf4000000+0x100000
51 * mx21: 51 * mx21:
52 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 52 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
53 * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000 53 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
54 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000 54 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
55 * mx25: 55 * mx25:
56 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 56 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
@@ -58,47 +58,50 @@
58 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 58 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
59 * mx27: 59 * mx27:
60 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 60 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
61 * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000 61 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
62 * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000 62 * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000
63 * mx31: 63 * mx31:
64 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 64 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
65 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 65 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
66 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 66 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
67 * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 67 * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000
68 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 68 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
69 * mx35: 69 * mx35:
70 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 70 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
71 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 71 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
72 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 72 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
73 * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 73 * X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000
74 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 74 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
75 * mx50: 75 * mx50:
76 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 76 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
77 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
78 * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 77 * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
78 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
79 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 79 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
80 * mx51: 80 * mx51:
81 * TZIC 0xe0000000+0x004000 -> 0xf5000000+0x004000 81 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
82 * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 82 * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
83 * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000
83 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 84 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
84 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 85 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
85 * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 86 * AIPS2 0x83f00000+0x100000 -> 0xf5300000+0x100000
86 * mx53: 87 * mx53:
87 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 88 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
89 * DEBUG 0x40000000+0x100000 -> 0xf5000000+0x100000
88 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 90 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
89 * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 91 * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
90 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 92 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
91 * mx6q: 93 * mx6q:
92 * SCU 0x00a00000+0x001000 -> 0xf4000000+0x001000 94 * SCU 0x00a00000+0x004000 -> 0xf4000000+0x004000
93 * CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000 95 * CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000
94 * ANATOP 0x020c8000+0x001000 -> 0xf42c8000+0x001000 96 * ANATOP 0x020c8000+0x004000 -> 0xf42c8000+0x004000
95 * UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000 97 * UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000
96 */ 98 */
97#define IMX_IO_P2V(x) ( \ 99#define IMX_IO_P2V(x) ( \
98 0xf4000000 + \ 100 (((x) & 0x80000000) >> 7) | \
101 (0xf4000000 + \
99 (((x) & 0x50000000) >> 6) + \ 102 (((x) & 0x50000000) >> 6) + \
100 (((x) & 0x0b000000) >> 4) + \ 103 (((x) & 0x0b000000) >> 4) + \
101 (((x) & 0x000fffff))) 104 (((x) & 0x000fffff))))
102 105
103#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) 106#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
104 107
@@ -128,6 +131,4 @@
128/* range e.g. GPIO_1_5 is gpio 5 under linux */ 131/* range e.g. GPIO_1_5 is gpio 5 under linux */
129#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) 132#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
130 133
131#define IMX_GPIO_TO_IRQ(gpio) (MXC_GPIO_IRQ_START + (gpio))
132
133#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ 134#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index 63f22a009a65..d8b65b51f2a9 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -160,9 +160,6 @@ int mxc_iomux_mode(unsigned int pin_mode);
160 160
161#define IOMUX_TO_GPIO(iomux_pin) \ 161#define IOMUX_TO_GPIO(iomux_pin) \
162 ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) 162 ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
163#define IOMUX_TO_IRQ(iomux_pin) \
164 (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \
165 MXC_GPIO_IRQ_START)
166 163
167/* 164/*
168 * This enumeration is constructed based on the Section 165 * This enumeration is constructed based on the Section
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index 36c8989d9de6..2623e7a2e190 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -107,11 +107,13 @@
107#define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL) 107#define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL)
108#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL) 108#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL)
109#define MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL) 109#define MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
110#define MX51_PAD_EIM_D25__GPT_CMPOUT1 IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
110#define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL) 111#define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
111#define MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL) 112#define MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL)
112#define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL) 113#define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL)
113#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL) 114#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL)
114#define MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL) 115#define MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
116#define MX51_PAD_EIM_D26__GPT_CMPOUT2 IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
115#define MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL) 117#define MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL)
116#define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL) 118#define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
117#define MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) 119#define MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
@@ -228,6 +230,7 @@
228#define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL) 230#define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
229#define MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL) 231#define MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL)
230#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL) 232#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
233#define MX51_PAD_DRAM_CS1__CCM_CLKO IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
231#define MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL) 234#define MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL)
232#define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL) 235#define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
233#define MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL) 236#define MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
@@ -256,12 +259,14 @@
256#define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) 259#define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
257#define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL) 260#define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
258#define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL) 261#define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
262#define MX51_PAD_NANDF_RB1__GPT_CMPOUT2 IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL)
259#define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) 263#define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)
260#define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL) 264#define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL)
261#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) 265#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
262#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2) 266#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2)
263#define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) 267#define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
264#define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL) 268#define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
269#define MX51_PAD_NANDF_RB2__GPT_CMPOUT3 IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL)
265#define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL) 270#define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL)
266#define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL) 271#define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL)
267#define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL) 272#define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
@@ -637,7 +642,9 @@
637#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL) 642#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
638#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL) 643#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
639#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL) 644#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL)
645#define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
640#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL) 646#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL)
647#define MX51_PAD_DI1_PIN15__DI1_PIN15 IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
641#define MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL) 648#define MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL)
642#define MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL) 649#define MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL)
643#define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL) 650#define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL)
@@ -780,6 +787,8 @@
780#define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL) 787#define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL)
781#define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) 788#define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
782#define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL) 789#define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL)
790#define MX51_PAD_GPIO1_3__CCM_CLKO2 IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL)
791#define MX51_PAD_GPIO1_3__GPT_CLKIN IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL)
783#define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL) 792#define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL)
784#define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL) 793#define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL)
785#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL) 794#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL)
@@ -788,13 +797,16 @@
788#define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL) 797#define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL)
789#define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) 798#define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
790#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL) 799#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL)
800#define MX51_PAD_GPIO1_4__GPT_CAPIN1 IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL)
791#define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL) 801#define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL)
792#define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL) 802#define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL)
793#define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) 803#define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
794#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL) 804#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL)
805#define MX51_PAD_GPIO1_5__CCM_CLKO IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL)
795#define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL) 806#define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL)
796#define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) 807#define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
797#define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL) 808#define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL)
809#define MX51_PAD_GPIO1_6__GPT_CAPIN2 IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL)
798#define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL) 810#define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL)
799#define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) 811#define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
800#define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) 812#define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
@@ -803,11 +815,13 @@
803#define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) 815#define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
804#define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) 816#define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
805#define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL) 817#define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL)
818#define MX51_PAD_GPIO1_8__CCM_CLKO2 IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL)
806#define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL) 819#define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL)
807#define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL) 820#define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL)
808#define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL) 821#define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL)
809#define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) 822#define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
810#define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL) 823#define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL)
811#define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL) 824#define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL)
825#define MX51_PAD_GPIO1_9__CCM_CLKO IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL)
812 826
813#endif /* __MACH_IOMUX_MX51_H__ */ 827#endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h
index f7d18046c04f..02651a40fe23 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v1.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h
@@ -85,13 +85,6 @@
85#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) 85#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
86#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) 86#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
87 87
88#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
89#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
90#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
91#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
92#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
93#define IRQ_GPIOF(x) (IRQ_GPIOE(32) + x)
94
95extern int mxc_gpio_mode(int gpio_mode); 88extern int mxc_gpio_mode(int gpio_mode);
96extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, 89extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
97 const char *label); 90 const char *label);
diff --git a/arch/arm/plat-mxc/include/mach/ipu.h b/arch/arm/plat-mxc/include/mach/ipu.h
index a9221f1cc1a0..539e559d18b2 100644
--- a/arch/arm/plat-mxc/include/mach/ipu.h
+++ b/arch/arm/plat-mxc/include/mach/ipu.h
@@ -110,10 +110,6 @@ enum ipu_rotate_mode {
110 IPU_ROTATE_90_LEFT = 7, 110 IPU_ROTATE_90_LEFT = 7,
111}; 111};
112 112
113struct ipu_platform_data {
114 unsigned int irq_base;
115};
116
117/* 113/*
118 * Enumeration of DI ports for ADC. 114 * Enumeration of DI ports for ADC.
119 */ 115 */
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index fd9efb044656..d73f5e8ea9cb 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -11,50 +11,6 @@
11#ifndef __ASM_ARCH_MXC_IRQS_H__ 11#ifndef __ASM_ARCH_MXC_IRQS_H__
12#define __ASM_ARCH_MXC_IRQS_H__ 12#define __ASM_ARCH_MXC_IRQS_H__
13 13
14#include <asm-generic/gpio.h>
15
16/*
17 * SoCs with GIC interrupt controller have 160 IRQs, those with TZIC
18 * have 128 IRQs, and those with AVIC have 64.
19 *
20 * To support single image, the biggest number should be defined on
21 * top of the list.
22 */
23#if defined CONFIG_ARM_GIC
24#define MXC_INTERNAL_IRQS 160
25#elif defined CONFIG_MXC_TZIC
26#define MXC_INTERNAL_IRQS 128
27#else
28#define MXC_INTERNAL_IRQS 64
29#endif
30
31#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
32
33/*
34 * The next 16 interrupts are for board specific purposes. Since
35 * the kernel can only run on one machine at a time, we can re-use
36 * these. If you need more, increase MXC_BOARD_IRQS, but keep it
37 * within sensible limits.
38 */
39#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + ARCH_NR_GPIOS)
40
41#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
42#define MXC_BOARD_IRQS 80
43#else
44#define MXC_BOARD_IRQS 16
45#endif
46
47#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
48
49#ifdef CONFIG_MX3_IPU_IRQS
50#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS
51#else
52#define MX3_IPU_IRQS 0
53#endif
54/* REVISIT: Add IPU irqs on IMX51 */
55
56#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
57
58extern int imx_irq_set_priority(unsigned char irq, unsigned char prio); 14extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
59 15
60/* all normal IRQs can be FIQs */ 16/* all normal IRQs can be FIQs */
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 2b7c08d13e89..45bd31cc34d6 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -78,61 +78,62 @@
78#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x)) 78#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
79 79
80/* fixed interrput numbers */ 80/* fixed interrput numbers */
81#define MX1_INT_SOFTINT 0 81#include <asm/irq.h>
82#define MX1_INT_CSI 6 82#define MX1_INT_SOFTINT (NR_IRQS_LEGACY + 0)
83#define MX1_DSPA_MAC_INT 7 83#define MX1_INT_CSI (NR_IRQS_LEGACY + 6)
84#define MX1_DSPA_INT 8 84#define MX1_DSPA_MAC_INT (NR_IRQS_LEGACY + 7)
85#define MX1_COMP_INT 9 85#define MX1_DSPA_INT (NR_IRQS_LEGACY + 8)
86#define MX1_MSHC_XINT 10 86#define MX1_COMP_INT (NR_IRQS_LEGACY + 9)
87#define MX1_GPIO_INT_PORTA 11 87#define MX1_MSHC_XINT (NR_IRQS_LEGACY + 10)
88#define MX1_GPIO_INT_PORTB 12 88#define MX1_GPIO_INT_PORTA (NR_IRQS_LEGACY + 11)
89#define MX1_GPIO_INT_PORTC 13 89#define MX1_GPIO_INT_PORTB (NR_IRQS_LEGACY + 12)
90#define MX1_INT_LCDC 14 90#define MX1_GPIO_INT_PORTC (NR_IRQS_LEGACY + 13)
91#define MX1_SIM_INT 15 91#define MX1_INT_LCDC (NR_IRQS_LEGACY + 14)
92#define MX1_SIM_DATA_INT 16 92#define MX1_SIM_INT (NR_IRQS_LEGACY + 15)
93#define MX1_RTC_INT 17 93#define MX1_SIM_DATA_INT (NR_IRQS_LEGACY + 16)
94#define MX1_RTC_SAMINT 18 94#define MX1_RTC_INT (NR_IRQS_LEGACY + 17)
95#define MX1_INT_UART2PFERR 19 95#define MX1_RTC_SAMINT (NR_IRQS_LEGACY + 18)
96#define MX1_INT_UART2RTS 20 96#define MX1_INT_UART2PFERR (NR_IRQS_LEGACY + 19)
97#define MX1_INT_UART2DTR 21 97#define MX1_INT_UART2RTS (NR_IRQS_LEGACY + 20)
98#define MX1_INT_UART2UARTC 22 98#define MX1_INT_UART2DTR (NR_IRQS_LEGACY + 21)
99#define MX1_INT_UART2TX 23 99#define MX1_INT_UART2UARTC (NR_IRQS_LEGACY + 22)
100#define MX1_INT_UART2RX 24 100#define MX1_INT_UART2TX (NR_IRQS_LEGACY + 23)
101#define MX1_INT_UART1PFERR 25 101#define MX1_INT_UART2RX (NR_IRQS_LEGACY + 24)
102#define MX1_INT_UART1RTS 26 102#define MX1_INT_UART1PFERR (NR_IRQS_LEGACY + 25)
103#define MX1_INT_UART1DTR 27 103#define MX1_INT_UART1RTS (NR_IRQS_LEGACY + 26)
104#define MX1_INT_UART1UARTC 28 104#define MX1_INT_UART1DTR (NR_IRQS_LEGACY + 27)
105#define MX1_INT_UART1TX 29 105#define MX1_INT_UART1UARTC (NR_IRQS_LEGACY + 28)
106#define MX1_INT_UART1RX 30 106#define MX1_INT_UART1TX (NR_IRQS_LEGACY + 29)
107#define MX1_VOICE_DAC_INT 31 107#define MX1_INT_UART1RX (NR_IRQS_LEGACY + 30)
108#define MX1_VOICE_ADC_INT 32 108#define MX1_VOICE_DAC_INT (NR_IRQS_LEGACY + 31)
109#define MX1_PEN_DATA_INT 33 109#define MX1_VOICE_ADC_INT (NR_IRQS_LEGACY + 32)
110#define MX1_PWM_INT 34 110#define MX1_PEN_DATA_INT (NR_IRQS_LEGACY + 33)
111#define MX1_SDHC_INT 35 111#define MX1_PWM_INT (NR_IRQS_LEGACY + 34)
112#define MX1_INT_I2C 39 112#define MX1_SDHC_INT (NR_IRQS_LEGACY + 35)
113#define MX1_INT_CSPI2 40 113#define MX1_INT_I2C (NR_IRQS_LEGACY + 39)
114#define MX1_INT_CSPI1 41 114#define MX1_INT_CSPI2 (NR_IRQS_LEGACY + 40)
115#define MX1_SSI_TX_INT 42 115#define MX1_INT_CSPI1 (NR_IRQS_LEGACY + 41)
116#define MX1_SSI_TX_ERR_INT 43 116#define MX1_SSI_TX_INT (NR_IRQS_LEGACY + 42)
117#define MX1_SSI_RX_INT 44 117#define MX1_SSI_TX_ERR_INT (NR_IRQS_LEGACY + 43)
118#define MX1_SSI_RX_ERR_INT 45 118#define MX1_SSI_RX_INT (NR_IRQS_LEGACY + 44)
119#define MX1_TOUCH_INT 46 119#define MX1_SSI_RX_ERR_INT (NR_IRQS_LEGACY + 45)
120#define MX1_INT_USBD0 47 120#define MX1_TOUCH_INT (NR_IRQS_LEGACY + 46)
121#define MX1_INT_USBD1 48 121#define MX1_INT_USBD0 (NR_IRQS_LEGACY + 47)
122#define MX1_INT_USBD2 49 122#define MX1_INT_USBD1 (NR_IRQS_LEGACY + 48)
123#define MX1_INT_USBD3 50 123#define MX1_INT_USBD2 (NR_IRQS_LEGACY + 49)
124#define MX1_INT_USBD4 51 124#define MX1_INT_USBD3 (NR_IRQS_LEGACY + 50)
125#define MX1_INT_USBD5 52 125#define MX1_INT_USBD4 (NR_IRQS_LEGACY + 51)
126#define MX1_INT_USBD6 53 126#define MX1_INT_USBD5 (NR_IRQS_LEGACY + 52)
127#define MX1_BTSYS_INT 55 127#define MX1_INT_USBD6 (NR_IRQS_LEGACY + 53)
128#define MX1_BTTIM_INT 56 128#define MX1_BTSYS_INT (NR_IRQS_LEGACY + 55)
129#define MX1_BTWUI_INT 57 129#define MX1_BTTIM_INT (NR_IRQS_LEGACY + 56)
130#define MX1_TIM2_INT 58 130#define MX1_BTWUI_INT (NR_IRQS_LEGACY + 57)
131#define MX1_TIM1_INT 59 131#define MX1_TIM2_INT (NR_IRQS_LEGACY + 58)
132#define MX1_DMA_ERR 60 132#define MX1_TIM1_INT (NR_IRQS_LEGACY + 59)
133#define MX1_DMA_INT 61 133#define MX1_DMA_ERR (NR_IRQS_LEGACY + 60)
134#define MX1_GPIO_INT_PORTD 62 134#define MX1_DMA_INT (NR_IRQS_LEGACY + 61)
135#define MX1_WDT_INT 63 135#define MX1_GPIO_INT_PORTD (NR_IRQS_LEGACY + 62)
136#define MX1_WDT_INT (NR_IRQS_LEGACY + 63)
136 137
137/* DMA */ 138/* DMA */
138#define MX1_DMA_REQ_UART3_T 2 139#define MX1_DMA_REQ_UART3_T 2
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index 6cd049ebbd8d..468738aa997f 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -99,59 +99,60 @@
99#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x)) 99#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x))
100 100
101/* fixed interrupt numbers */ 101/* fixed interrupt numbers */
102#define MX21_INT_CSPI3 6 102#include <asm/irq.h>
103#define MX21_INT_GPIO 8 103#define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6)
104#define MX21_INT_FIRI 9 104#define MX21_INT_GPIO (NR_IRQS_LEGACY + 8)
105#define MX21_INT_SDHC2 10 105#define MX21_INT_FIRI (NR_IRQS_LEGACY + 9)
106#define MX21_INT_SDHC1 11 106#define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10)
107#define MX21_INT_I2C 12 107#define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11)
108#define MX21_INT_SSI2 13 108#define MX21_INT_I2C (NR_IRQS_LEGACY + 12)
109#define MX21_INT_SSI1 14 109#define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13)
110#define MX21_INT_CSPI2 15 110#define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14)
111#define MX21_INT_CSPI1 16 111#define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15)
112#define MX21_INT_UART4 17 112#define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16)
113#define MX21_INT_UART3 18 113#define MX21_INT_UART4 (NR_IRQS_LEGACY + 17)
114#define MX21_INT_UART2 19 114#define MX21_INT_UART3 (NR_IRQS_LEGACY + 18)
115#define MX21_INT_UART1 20 115#define MX21_INT_UART2 (NR_IRQS_LEGACY + 19)
116#define MX21_INT_KPP 21 116#define MX21_INT_UART1 (NR_IRQS_LEGACY + 20)
117#define MX21_INT_RTC 22 117#define MX21_INT_KPP (NR_IRQS_LEGACY + 21)
118#define MX21_INT_PWM 23 118#define MX21_INT_RTC (NR_IRQS_LEGACY + 22)
119#define MX21_INT_GPT3 24 119#define MX21_INT_PWM (NR_IRQS_LEGACY + 23)
120#define MX21_INT_GPT2 25 120#define MX21_INT_GPT3 (NR_IRQS_LEGACY + 24)
121#define MX21_INT_GPT1 26 121#define MX21_INT_GPT2 (NR_IRQS_LEGACY + 25)
122#define MX21_INT_WDOG 27 122#define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26)
123#define MX21_INT_PCMCIA 28 123#define MX21_INT_WDOG (NR_IRQS_LEGACY + 27)
124#define MX21_INT_NFC 29 124#define MX21_INT_PCMCIA (NR_IRQS_LEGACY + 28)
125#define MX21_INT_BMI 30 125#define MX21_INT_NFC (NR_IRQS_LEGACY + 29)
126#define MX21_INT_CSI 31 126#define MX21_INT_BMI (NR_IRQS_LEGACY + 30)
127#define MX21_INT_DMACH0 32 127#define MX21_INT_CSI (NR_IRQS_LEGACY + 31)
128#define MX21_INT_DMACH1 33 128#define MX21_INT_DMACH0 (NR_IRQS_LEGACY + 32)
129#define MX21_INT_DMACH2 34 129#define MX21_INT_DMACH1 (NR_IRQS_LEGACY + 33)
130#define MX21_INT_DMACH3 35 130#define MX21_INT_DMACH2 (NR_IRQS_LEGACY + 34)
131#define MX21_INT_DMACH4 36 131#define MX21_INT_DMACH3 (NR_IRQS_LEGACY + 35)
132#define MX21_INT_DMACH5 37 132#define MX21_INT_DMACH4 (NR_IRQS_LEGACY + 36)
133#define MX21_INT_DMACH6 38 133#define MX21_INT_DMACH5 (NR_IRQS_LEGACY + 37)
134#define MX21_INT_DMACH7 39 134#define MX21_INT_DMACH6 (NR_IRQS_LEGACY + 38)
135#define MX21_INT_DMACH8 40 135#define MX21_INT_DMACH7 (NR_IRQS_LEGACY + 39)
136#define MX21_INT_DMACH9 41 136#define MX21_INT_DMACH8 (NR_IRQS_LEGACY + 40)
137#define MX21_INT_DMACH10 42 137#define MX21_INT_DMACH9 (NR_IRQS_LEGACY + 41)
138#define MX21_INT_DMACH11 43 138#define MX21_INT_DMACH10 (NR_IRQS_LEGACY + 42)
139#define MX21_INT_DMACH12 44 139#define MX21_INT_DMACH11 (NR_IRQS_LEGACY + 43)
140#define MX21_INT_DMACH13 45 140#define MX21_INT_DMACH12 (NR_IRQS_LEGACY + 44)
141#define MX21_INT_DMACH14 46 141#define MX21_INT_DMACH13 (NR_IRQS_LEGACY + 45)
142#define MX21_INT_DMACH15 47 142#define MX21_INT_DMACH14 (NR_IRQS_LEGACY + 46)
143#define MX21_INT_EMMAENC 49 143#define MX21_INT_DMACH15 (NR_IRQS_LEGACY + 47)
144#define MX21_INT_EMMADEC 50 144#define MX21_INT_EMMAENC (NR_IRQS_LEGACY + 49)
145#define MX21_INT_EMMAPRP 51 145#define MX21_INT_EMMADEC (NR_IRQS_LEGACY + 50)
146#define MX21_INT_EMMAPP 52 146#define MX21_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
147#define MX21_INT_USBWKUP 53 147#define MX21_INT_EMMAPP (NR_IRQS_LEGACY + 52)
148#define MX21_INT_USBDMA 54 148#define MX21_INT_USBWKUP (NR_IRQS_LEGACY + 53)
149#define MX21_INT_USBHOST 55 149#define MX21_INT_USBDMA (NR_IRQS_LEGACY + 54)
150#define MX21_INT_USBFUNC 56 150#define MX21_INT_USBHOST (NR_IRQS_LEGACY + 55)
151#define MX21_INT_USBMNP 57 151#define MX21_INT_USBFUNC (NR_IRQS_LEGACY + 56)
152#define MX21_INT_USBCTRL 58 152#define MX21_INT_USBMNP (NR_IRQS_LEGACY + 57)
153#define MX21_INT_SLCDC 60 153#define MX21_INT_USBCTRL (NR_IRQS_LEGACY + 58)
154#define MX21_INT_LCDC 61 154#define MX21_INT_SLCDC (NR_IRQS_LEGACY + 60)
155#define MX21_INT_LCDC (NR_IRQS_LEGACY + 61)
155 156
156/* fixed DMA request numbers */ 157/* fixed DMA request numbers */
157#define MX21_DMA_REQ_CSPI3_RX 1 158#define MX21_DMA_REQ_CSPI3_RX 1
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index ccebf5ba12f0..627d94f1b010 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -61,40 +61,44 @@
61#define MX25_IO_P2V(x) IMX_IO_P2V(x) 61#define MX25_IO_P2V(x) IMX_IO_P2V(x)
62#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x)) 62#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
63 63
64#define MX25_INT_CSPI3 0 64/*
65#define MX25_INT_I2C1 3 65 * Interrupt numbers
66#define MX25_INT_I2C2 4 66 */
67#define MX25_INT_UART4 5 67#include <asm/irq.h>
68#define MX25_INT_ESDHC2 8 68#define MX25_INT_CSPI3 (NR_IRQS_LEGACY + 0)
69#define MX25_INT_ESDHC1 9 69#define MX25_INT_I2C1 (NR_IRQS_LEGACY + 3)
70#define MX25_INT_I2C3 10 70#define MX25_INT_I2C2 (NR_IRQS_LEGACY + 4)
71#define MX25_INT_SSI2 11 71#define MX25_INT_UART4 (NR_IRQS_LEGACY + 5)
72#define MX25_INT_SSI1 12 72#define MX25_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
73#define MX25_INT_CSPI2 13 73#define MX25_INT_ESDHC1 (NR_IRQS_LEGACY + 9)
74#define MX25_INT_CSPI1 14 74#define MX25_INT_I2C3 (NR_IRQS_LEGACY + 10)
75#define MX25_INT_GPIO3 16 75#define MX25_INT_SSI2 (NR_IRQS_LEGACY + 11)
76#define MX25_INT_CSI 17 76#define MX25_INT_SSI1 (NR_IRQS_LEGACY + 12)
77#define MX25_INT_UART3 18 77#define MX25_INT_CSPI2 (NR_IRQS_LEGACY + 13)
78#define MX25_INT_GPIO4 23 78#define MX25_INT_CSPI1 (NR_IRQS_LEGACY + 14)
79#define MX25_INT_KPP 24 79#define MX25_INT_GPIO3 (NR_IRQS_LEGACY + 16)
80#define MX25_INT_DRYICE 25 80#define MX25_INT_CSI (NR_IRQS_LEGACY + 17)
81#define MX25_INT_PWM1 26 81#define MX25_INT_UART3 (NR_IRQS_LEGACY + 18)
82#define MX25_INT_UART2 32 82#define MX25_INT_GPIO4 (NR_IRQS_LEGACY + 23)
83#define MX25_INT_NFC 33 83#define MX25_INT_KPP (NR_IRQS_LEGACY + 24)
84#define MX25_INT_SDMA 34 84#define MX25_INT_DRYICE (NR_IRQS_LEGACY + 25)
85#define MX25_INT_USB_HS 35 85#define MX25_INT_PWM1 (NR_IRQS_LEGACY + 26)
86#define MX25_INT_PWM2 36 86#define MX25_INT_UART2 (NR_IRQS_LEGACY + 32)
87#define MX25_INT_USB_OTG 37 87#define MX25_INT_NFC (NR_IRQS_LEGACY + 33)
88#define MX25_INT_LCDC 39 88#define MX25_INT_SDMA (NR_IRQS_LEGACY + 34)
89#define MX25_INT_UART5 40 89#define MX25_INT_USB_HS (NR_IRQS_LEGACY + 35)
90#define MX25_INT_PWM3 41 90#define MX25_INT_PWM2 (NR_IRQS_LEGACY + 36)
91#define MX25_INT_PWM4 42 91#define MX25_INT_USB_OTG (NR_IRQS_LEGACY + 37)
92#define MX25_INT_CAN1 43 92#define MX25_INT_LCDC (NR_IRQS_LEGACY + 39)
93#define MX25_INT_CAN2 44 93#define MX25_INT_UART5 (NR_IRQS_LEGACY + 40)
94#define MX25_INT_UART1 45 94#define MX25_INT_PWM3 (NR_IRQS_LEGACY + 41)
95#define MX25_INT_GPIO2 51 95#define MX25_INT_PWM4 (NR_IRQS_LEGACY + 42)
96#define MX25_INT_GPIO1 52 96#define MX25_INT_CAN1 (NR_IRQS_LEGACY + 43)
97#define MX25_INT_FEC 57 97#define MX25_INT_CAN2 (NR_IRQS_LEGACY + 44)
98#define MX25_INT_UART1 (NR_IRQS_LEGACY + 45)
99#define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51)
100#define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52)
101#define MX25_INT_FEC (NR_IRQS_LEGACY + 57)
98 102
99#define MX25_DMA_REQ_SSI2_RX1 22 103#define MX25_DMA_REQ_SSI2_RX1 22
100#define MX25_DMA_REQ_SSI2_TX1 23 104#define MX25_DMA_REQ_SSI2_TX1 23
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 6265357284d7..e074616d54ca 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -128,69 +128,70 @@
128#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) 128#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
129 129
130/* fixed interrupt numbers */ 130/* fixed interrupt numbers */
131#define MX27_INT_I2C2 1 131#include <asm/irq.h>
132#define MX27_INT_GPT6 2 132#define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1)
133#define MX27_INT_GPT5 3 133#define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2)
134#define MX27_INT_GPT4 4 134#define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3)
135#define MX27_INT_RTIC 5 135#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4)
136#define MX27_INT_CSPI3 6 136#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5)
137#define MX27_INT_SDHC 7 137#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6)
138#define MX27_INT_GPIO 8 138#define MX27_INT_SDHC (NR_IRQS_LEGACY + 7)
139#define MX27_INT_SDHC3 9 139#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8)
140#define MX27_INT_SDHC2 10 140#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9)
141#define MX27_INT_SDHC1 11 141#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10)
142#define MX27_INT_I2C1 12 142#define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11)
143#define MX27_INT_SSI2 13 143#define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12)
144#define MX27_INT_SSI1 14 144#define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13)
145#define MX27_INT_CSPI2 15 145#define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14)
146#define MX27_INT_CSPI1 16 146#define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15)
147#define MX27_INT_UART4 17 147#define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16)
148#define MX27_INT_UART3 18 148#define MX27_INT_UART4 (NR_IRQS_LEGACY + 17)
149#define MX27_INT_UART2 19 149#define MX27_INT_UART3 (NR_IRQS_LEGACY + 18)
150#define MX27_INT_UART1 20 150#define MX27_INT_UART2 (NR_IRQS_LEGACY + 19)
151#define MX27_INT_KPP 21 151#define MX27_INT_UART1 (NR_IRQS_LEGACY + 20)
152#define MX27_INT_RTC 22 152#define MX27_INT_KPP (NR_IRQS_LEGACY + 21)
153#define MX27_INT_PWM 23 153#define MX27_INT_RTC (NR_IRQS_LEGACY + 22)
154#define MX27_INT_GPT3 24 154#define MX27_INT_PWM (NR_IRQS_LEGACY + 23)
155#define MX27_INT_GPT2 25 155#define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24)
156#define MX27_INT_GPT1 26 156#define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25)
157#define MX27_INT_WDOG 27 157#define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26)
158#define MX27_INT_PCMCIA 28 158#define MX27_INT_WDOG (NR_IRQS_LEGACY + 27)
159#define MX27_INT_NFC 29 159#define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28)
160#define MX27_INT_ATA 30 160#define MX27_INT_NFC (NR_IRQS_LEGACY + 29)
161#define MX27_INT_CSI 31 161#define MX27_INT_ATA (NR_IRQS_LEGACY + 30)
162#define MX27_INT_DMACH0 32 162#define MX27_INT_CSI (NR_IRQS_LEGACY + 31)
163#define MX27_INT_DMACH1 33 163#define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32)
164#define MX27_INT_DMACH2 34 164#define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33)
165#define MX27_INT_DMACH3 35 165#define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34)
166#define MX27_INT_DMACH4 36 166#define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35)
167#define MX27_INT_DMACH5 37 167#define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36)
168#define MX27_INT_DMACH6 38 168#define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37)
169#define MX27_INT_DMACH7 39 169#define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38)
170#define MX27_INT_DMACH8 40 170#define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39)
171#define MX27_INT_DMACH9 41 171#define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40)
172#define MX27_INT_DMACH10 42 172#define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41)
173#define MX27_INT_DMACH11 43 173#define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42)
174#define MX27_INT_DMACH12 44 174#define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43)
175#define MX27_INT_DMACH13 45 175#define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44)
176#define MX27_INT_DMACH14 46 176#define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45)
177#define MX27_INT_DMACH15 47 177#define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46)
178#define MX27_INT_UART6 48 178#define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47)
179#define MX27_INT_UART5 49 179#define MX27_INT_UART6 (NR_IRQS_LEGACY + 48)
180#define MX27_INT_FEC 50 180#define MX27_INT_UART5 (NR_IRQS_LEGACY + 49)
181#define MX27_INT_EMMAPRP 51 181#define MX27_INT_FEC (NR_IRQS_LEGACY + 50)
182#define MX27_INT_EMMAPP 52 182#define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
183#define MX27_INT_VPU 53 183#define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52)
184#define MX27_INT_USB_HS1 54 184#define MX27_INT_VPU (NR_IRQS_LEGACY + 53)
185#define MX27_INT_USB_HS2 55 185#define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54)
186#define MX27_INT_USB_OTG 56 186#define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55)
187#define MX27_INT_SCC_SMN 57 187#define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56)
188#define MX27_INT_SCC_SCM 58 188#define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57)
189#define MX27_INT_SAHARA 59 189#define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58)
190#define MX27_INT_SLCDC 60 190#define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59)
191#define MX27_INT_LCDC 61 191#define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60)
192#define MX27_INT_IIM 62 192#define MX27_INT_LCDC (NR_IRQS_LEGACY + 61)
193#define MX27_INT_CCM 63 193#define MX27_INT_IIM (NR_IRQS_LEGACY + 62)
194#define MX27_INT_CCM (NR_IRQS_LEGACY + 63)
194 195
195/* fixed DMA request numbers */ 196/* fixed DMA request numbers */
196#define MX27_DMA_REQ_CSPI3_RX 1 197#define MX27_DMA_REQ_CSPI3_RX 1
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index 6d07839fdec2..11642f5b224c 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -68,49 +68,50 @@
68#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) 68#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
69 69
70/* fixed interrupt numbers */ 70/* fixed interrupt numbers */
71#define MX2x_INT_CSPI3 6 71#include <asm/irq.h>
72#define MX2x_INT_GPIO 8 72#define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6)
73#define MX2x_INT_SDHC2 10 73#define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8)
74#define MX2x_INT_SDHC1 11 74#define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10)
75#define MX2x_INT_I2C 12 75#define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11)
76#define MX2x_INT_SSI2 13 76#define MX2x_INT_I2C (NR_IRQS_LEGACY + 12)
77#define MX2x_INT_SSI1 14 77#define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13)
78#define MX2x_INT_CSPI2 15 78#define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14)
79#define MX2x_INT_CSPI1 16 79#define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15)
80#define MX2x_INT_UART4 17 80#define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16)
81#define MX2x_INT_UART3 18 81#define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17)
82#define MX2x_INT_UART2 19 82#define MX2x_INT_UART3 (NR_IRQS_LEGACY + 18)
83#define MX2x_INT_UART1 20 83#define MX2x_INT_UART2 (NR_IRQS_LEGACY + 19)
84#define MX2x_INT_KPP 21 84#define MX2x_INT_UART1 (NR_IRQS_LEGACY + 20)
85#define MX2x_INT_RTC 22 85#define MX2x_INT_KPP (NR_IRQS_LEGACY + 21)
86#define MX2x_INT_PWM 23 86#define MX2x_INT_RTC (NR_IRQS_LEGACY + 22)
87#define MX2x_INT_GPT3 24 87#define MX2x_INT_PWM (NR_IRQS_LEGACY + 23)
88#define MX2x_INT_GPT2 25 88#define MX2x_INT_GPT3 (NR_IRQS_LEGACY + 24)
89#define MX2x_INT_GPT1 26 89#define MX2x_INT_GPT2 (NR_IRQS_LEGACY + 25)
90#define MX2x_INT_WDOG 27 90#define MX2x_INT_GPT1 (NR_IRQS_LEGACY + 26)
91#define MX2x_INT_PCMCIA 28 91#define MX2x_INT_WDOG (NR_IRQS_LEGACY + 27)
92#define MX2x_INT_NANDFC 29 92#define MX2x_INT_PCMCIA (NR_IRQS_LEGACY + 28)
93#define MX2x_INT_CSI 31 93#define MX2x_INT_NANDFC (NR_IRQS_LEGACY + 29)
94#define MX2x_INT_DMACH0 32 94#define MX2x_INT_CSI (NR_IRQS_LEGACY + 31)
95#define MX2x_INT_DMACH1 33 95#define MX2x_INT_DMACH0 (NR_IRQS_LEGACY + 32)
96#define MX2x_INT_DMACH2 34 96#define MX2x_INT_DMACH1 (NR_IRQS_LEGACY + 33)
97#define MX2x_INT_DMACH3 35 97#define MX2x_INT_DMACH2 (NR_IRQS_LEGACY + 34)
98#define MX2x_INT_DMACH4 36 98#define MX2x_INT_DMACH3 (NR_IRQS_LEGACY + 35)
99#define MX2x_INT_DMACH5 37 99#define MX2x_INT_DMACH4 (NR_IRQS_LEGACY + 36)
100#define MX2x_INT_DMACH6 38 100#define MX2x_INT_DMACH5 (NR_IRQS_LEGACY + 37)
101#define MX2x_INT_DMACH7 39 101#define MX2x_INT_DMACH6 (NR_IRQS_LEGACY + 38)
102#define MX2x_INT_DMACH8 40 102#define MX2x_INT_DMACH7 (NR_IRQS_LEGACY + 39)
103#define MX2x_INT_DMACH9 41 103#define MX2x_INT_DMACH8 (NR_IRQS_LEGACY + 40)
104#define MX2x_INT_DMACH10 42 104#define MX2x_INT_DMACH9 (NR_IRQS_LEGACY + 41)
105#define MX2x_INT_DMACH11 43 105#define MX2x_INT_DMACH10 (NR_IRQS_LEGACY + 42)
106#define MX2x_INT_DMACH12 44 106#define MX2x_INT_DMACH11 (NR_IRQS_LEGACY + 43)
107#define MX2x_INT_DMACH13 45 107#define MX2x_INT_DMACH12 (NR_IRQS_LEGACY + 44)
108#define MX2x_INT_DMACH14 46 108#define MX2x_INT_DMACH13 (NR_IRQS_LEGACY + 45)
109#define MX2x_INT_DMACH15 47 109#define MX2x_INT_DMACH14 (NR_IRQS_LEGACY + 46)
110#define MX2x_INT_EMMAPRP 51 110#define MX2x_INT_DMACH15 (NR_IRQS_LEGACY + 47)
111#define MX2x_INT_EMMAPP 52 111#define MX2x_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
112#define MX2x_INT_SLCDC 60 112#define MX2x_INT_EMMAPP (NR_IRQS_LEGACY + 52)
113#define MX2x_INT_LCDC 61 113#define MX2x_INT_SLCDC (NR_IRQS_LEGACY + 60)
114#define MX2x_INT_LCDC (NR_IRQS_LEGACY + 61)
114 115
115/* fixed DMA request numbers */ 116/* fixed DMA request numbers */
116#define MX2x_DMA_REQ_CSPI3_RX 1 117#define MX2x_DMA_REQ_CSPI3_RX 1
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index e27619e442c0..dbced61d9fda 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -118,63 +118,67 @@
118#define MX31_IO_P2V(x) IMX_IO_P2V(x) 118#define MX31_IO_P2V(x) IMX_IO_P2V(x)
119#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) 119#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x))
120 120
121#define MX31_INT_I2C3 3 121/*
122#define MX31_INT_I2C2 4 122 * Interrupt numbers
123#define MX31_INT_MPEG4_ENCODER 5 123 */
124#define MX31_INT_RTIC 6 124#include <asm/irq.h>
125#define MX31_INT_FIRI 7 125#define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3)
126#define MX31_INT_SDHC2 8 126#define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4)
127#define MX31_INT_SDHC1 9 127#define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5)
128#define MX31_INT_I2C1 10 128#define MX31_INT_RTIC (NR_IRQS_LEGACY + 6)
129#define MX31_INT_SSI2 11 129#define MX31_INT_FIRI (NR_IRQS_LEGACY + 7)
130#define MX31_INT_SSI1 12 130#define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8)
131#define MX31_INT_CSPI2 13 131#define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9)
132#define MX31_INT_CSPI1 14 132#define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10)
133#define MX31_INT_ATA 15 133#define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11)
134#define MX31_INT_MBX 16 134#define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12)
135#define MX31_INT_CSPI3 17 135#define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13)
136#define MX31_INT_UART3 18 136#define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14)
137#define MX31_INT_IIM 19 137#define MX31_INT_ATA (NR_IRQS_LEGACY + 15)
138#define MX31_INT_SIM2 20 138#define MX31_INT_MBX (NR_IRQS_LEGACY + 16)
139#define MX31_INT_SIM1 21 139#define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17)
140#define MX31_INT_RNGA 22 140#define MX31_INT_UART3 (NR_IRQS_LEGACY + 18)
141#define MX31_INT_EVTMON 23 141#define MX31_INT_IIM (NR_IRQS_LEGACY + 19)
142#define MX31_INT_KPP 24 142#define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20)
143#define MX31_INT_RTC 25 143#define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21)
144#define MX31_INT_PWM 26 144#define MX31_INT_RNGA (NR_IRQS_LEGACY + 22)
145#define MX31_INT_EPIT2 27 145#define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23)
146#define MX31_INT_EPIT1 28 146#define MX31_INT_KPP (NR_IRQS_LEGACY + 24)
147#define MX31_INT_GPT 29 147#define MX31_INT_RTC (NR_IRQS_LEGACY + 25)
148#define MX31_INT_POWER_FAIL 30 148#define MX31_INT_PWM (NR_IRQS_LEGACY + 26)
149#define MX31_INT_CCM_DVFS 31 149#define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27)
150#define MX31_INT_UART2 32 150#define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28)
151#define MX31_INT_NFC 33 151#define MX31_INT_GPT (NR_IRQS_LEGACY + 29)
152#define MX31_INT_SDMA 34 152#define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
153#define MX31_INT_USB_HS1 35 153#define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31)
154#define MX31_INT_USB_HS2 36 154#define MX31_INT_UART2 (NR_IRQS_LEGACY + 32)
155#define MX31_INT_USB_OTG 37 155#define MX31_INT_NFC (NR_IRQS_LEGACY + 33)
156#define MX31_INT_MSHC1 39 156#define MX31_INT_SDMA (NR_IRQS_LEGACY + 34)
157#define MX31_INT_MSHC2 40 157#define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35)
158#define MX31_INT_IPU_ERR 41 158#define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36)
159#define MX31_INT_IPU_SYN 42 159#define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37)
160#define MX31_INT_UART1 45 160#define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39)
161#define MX31_INT_UART4 46 161#define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40)
162#define MX31_INT_UART5 47 162#define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
163#define MX31_INT_ECT 48 163#define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
164#define MX31_INT_SCC_SCM 49 164#define MX31_INT_UART1 (NR_IRQS_LEGACY + 45)
165#define MX31_INT_SCC_SMN 50 165#define MX31_INT_UART4 (NR_IRQS_LEGACY + 46)
166#define MX31_INT_GPIO2 51 166#define MX31_INT_UART5 (NR_IRQS_LEGACY + 47)
167#define MX31_INT_GPIO1 52 167#define MX31_INT_ECT (NR_IRQS_LEGACY + 48)
168#define MX31_INT_CCM 53 168#define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
169#define MX31_INT_PCMCIA 54 169#define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
170#define MX31_INT_WDOG 55 170#define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51)
171#define MX31_INT_GPIO3 56 171#define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52)
172#define MX31_INT_EXT_POWER 58 172#define MX31_INT_CCM (NR_IRQS_LEGACY + 53)
173#define MX31_INT_EXT_TEMPER 59 173#define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54)
174#define MX31_INT_EXT_SENSOR60 60 174#define MX31_INT_WDOG (NR_IRQS_LEGACY + 55)
175#define MX31_INT_EXT_SENSOR61 61 175#define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56)
176#define MX31_INT_EXT_WDOG 62 176#define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
177#define MX31_INT_EXT_TV 63 177#define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
178#define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
179#define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
180#define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
181#define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63)
178 182
179#define MX31_DMA_REQ_SDHC1 20 183#define MX31_DMA_REQ_SDHC1 20
180#define MX31_DMA_REQ_SDHC2 21 184#define MX31_DMA_REQ_SDHC2 21
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 80965a99aa55..2af5d3a699c7 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -120,60 +120,61 @@
120/* 120/*
121 * Interrupt numbers 121 * Interrupt numbers
122 */ 122 */
123#define MX35_INT_OWIRE 2 123#include <asm/irq.h>
124#define MX35_INT_I2C3 3 124#define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2)
125#define MX35_INT_I2C2 4 125#define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3)
126#define MX35_INT_RTIC 6 126#define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4)
127#define MX35_INT_ESDHC1 7 127#define MX35_INT_RTIC (NR_IRQS_LEGACY + 6)
128#define MX35_INT_ESDHC2 8 128#define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7)
129#define MX35_INT_ESDHC3 9 129#define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
130#define MX35_INT_I2C1 10 130#define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9)
131#define MX35_INT_SSI1 11 131#define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10)
132#define MX35_INT_SSI2 12 132#define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11)
133#define MX35_INT_CSPI2 13 133#define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12)
134#define MX35_INT_CSPI1 14 134#define MX35_INT_CSPI2 (NR_IRQS_LEGACY + 13)
135#define MX35_INT_ATA 15 135#define MX35_INT_CSPI1 (NR_IRQS_LEGACY + 14)
136#define MX35_INT_GPU2D 16 136#define MX35_INT_ATA (NR_IRQS_LEGACY + 15)
137#define MX35_INT_ASRC 17 137#define MX35_INT_GPU2D (NR_IRQS_LEGACY + 16)
138#define MX35_INT_UART3 18 138#define MX35_INT_ASRC (NR_IRQS_LEGACY + 17)
139#define MX35_INT_IIM 19 139#define MX35_INT_UART3 (NR_IRQS_LEGACY + 18)
140#define MX35_INT_RNGA 22 140#define MX35_INT_IIM (NR_IRQS_LEGACY + 19)
141#define MX35_INT_EVTMON 23 141#define MX35_INT_RNGA (NR_IRQS_LEGACY + 22)
142#define MX35_INT_KPP 24 142#define MX35_INT_EVTMON (NR_IRQS_LEGACY + 23)
143#define MX35_INT_RTC 25 143#define MX35_INT_KPP (NR_IRQS_LEGACY + 24)
144#define MX35_INT_PWM 26 144#define MX35_INT_RTC (NR_IRQS_LEGACY + 25)
145#define MX35_INT_EPIT2 27 145#define MX35_INT_PWM (NR_IRQS_LEGACY + 26)
146#define MX35_INT_EPIT1 28 146#define MX35_INT_EPIT2 (NR_IRQS_LEGACY + 27)
147#define MX35_INT_GPT 29 147#define MX35_INT_EPIT1 (NR_IRQS_LEGACY + 28)
148#define MX35_INT_POWER_FAIL 30 148#define MX35_INT_GPT (NR_IRQS_LEGACY + 29)
149#define MX35_INT_UART2 32 149#define MX35_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
150#define MX35_INT_NFC 33 150#define MX35_INT_UART2 (NR_IRQS_LEGACY + 32)
151#define MX35_INT_SDMA 34 151#define MX35_INT_NFC (NR_IRQS_LEGACY + 33)
152#define MX35_INT_USB_HS 35 152#define MX35_INT_SDMA (NR_IRQS_LEGACY + 34)
153#define MX35_INT_USB_OTG 37 153#define MX35_INT_USB_HS (NR_IRQS_LEGACY + 35)
154#define MX35_INT_MSHC1 39 154#define MX35_INT_USB_OTG (NR_IRQS_LEGACY + 37)
155#define MX35_INT_ESAI 40 155#define MX35_INT_MSHC1 (NR_IRQS_LEGACY + 39)
156#define MX35_INT_IPU_ERR 41 156#define MX35_INT_ESAI (NR_IRQS_LEGACY + 40)
157#define MX35_INT_IPU_SYN 42 157#define MX35_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
158#define MX35_INT_CAN1 43 158#define MX35_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
159#define MX35_INT_CAN2 44 159#define MX35_INT_CAN1 (NR_IRQS_LEGACY + 43)
160#define MX35_INT_UART1 45 160#define MX35_INT_CAN2 (NR_IRQS_LEGACY + 44)
161#define MX35_INT_MLB 46 161#define MX35_INT_UART1 (NR_IRQS_LEGACY + 45)
162#define MX35_INT_SPDIF 47 162#define MX35_INT_MLB (NR_IRQS_LEGACY + 46)
163#define MX35_INT_ECT 48 163#define MX35_INT_SPDIF (NR_IRQS_LEGACY + 47)
164#define MX35_INT_SCC_SCM 49 164#define MX35_INT_ECT (NR_IRQS_LEGACY + 48)
165#define MX35_INT_SCC_SMN 50 165#define MX35_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
166#define MX35_INT_GPIO2 51 166#define MX35_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
167#define MX35_INT_GPIO1 52 167#define MX35_INT_GPIO2 (NR_IRQS_LEGACY + 51)
168#define MX35_INT_WDOG 55 168#define MX35_INT_GPIO1 (NR_IRQS_LEGACY + 52)
169#define MX35_INT_GPIO3 56 169#define MX35_INT_WDOG (NR_IRQS_LEGACY + 55)
170#define MX35_INT_FEC 57 170#define MX35_INT_GPIO3 (NR_IRQS_LEGACY + 56)
171#define MX35_INT_EXT_POWER 58 171#define MX35_INT_FEC (NR_IRQS_LEGACY + 57)
172#define MX35_INT_EXT_TEMPER 59 172#define MX35_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
173#define MX35_INT_EXT_SENSOR60 60 173#define MX35_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
174#define MX35_INT_EXT_SENSOR61 61 174#define MX35_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
175#define MX35_INT_EXT_WDOG 62 175#define MX35_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
176#define MX35_INT_EXT_TV 63 176#define MX35_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
177#define MX35_INT_EXT_TV (NR_IRQS_LEGACY + 63)
177 178
178#define MX35_DMA_REQ_SSI2_RX1 22 179#define MX35_DMA_REQ_SSI2_RX1 22
179#define MX35_DMA_REQ_SSI2_TX1 23 180#define MX35_DMA_REQ_SSI2_TX1 23
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 30dbf424583e..96fb4fbc8ad7 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -143,44 +143,45 @@
143/* 143/*
144 * Interrupt numbers 144 * Interrupt numbers
145 */ 145 */
146#define MX3x_INT_I2C3 3 146#include <asm/irq.h>
147#define MX3x_INT_I2C2 4 147#define MX3x_INT_I2C3 (NR_IRQS_LEGACY + 3)
148#define MX3x_INT_RTIC 6 148#define MX3x_INT_I2C2 (NR_IRQS_LEGACY + 4)
149#define MX3x_INT_I2C 10 149#define MX3x_INT_RTIC (NR_IRQS_LEGACY + 6)
150#define MX3x_INT_CSPI2 13 150#define MX3x_INT_I2C (NR_IRQS_LEGACY + 10)
151#define MX3x_INT_CSPI1 14 151#define MX3x_INT_CSPI2 (NR_IRQS_LEGACY + 13)
152#define MX3x_INT_ATA 15 152#define MX3x_INT_CSPI1 (NR_IRQS_LEGACY + 14)
153#define MX3x_INT_UART3 18 153#define MX3x_INT_ATA (NR_IRQS_LEGACY + 15)
154#define MX3x_INT_IIM 19 154#define MX3x_INT_UART3 (NR_IRQS_LEGACY + 18)
155#define MX3x_INT_RNGA 22 155#define MX3x_INT_IIM (NR_IRQS_LEGACY + 19)
156#define MX3x_INT_EVTMON 23 156#define MX3x_INT_RNGA (NR_IRQS_LEGACY + 22)
157#define MX3x_INT_KPP 24 157#define MX3x_INT_EVTMON (NR_IRQS_LEGACY + 23)
158#define MX3x_INT_RTC 25 158#define MX3x_INT_KPP (NR_IRQS_LEGACY + 24)
159#define MX3x_INT_PWM 26 159#define MX3x_INT_RTC (NR_IRQS_LEGACY + 25)
160#define MX3x_INT_EPIT2 27 160#define MX3x_INT_PWM (NR_IRQS_LEGACY + 26)
161#define MX3x_INT_EPIT1 28 161#define MX3x_INT_EPIT2 (NR_IRQS_LEGACY + 27)
162#define MX3x_INT_GPT 29 162#define MX3x_INT_EPIT1 (NR_IRQS_LEGACY + 28)
163#define MX3x_INT_POWER_FAIL 30 163#define MX3x_INT_GPT (NR_IRQS_LEGACY + 29)
164#define MX3x_INT_UART2 32 164#define MX3x_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
165#define MX3x_INT_NANDFC 33 165#define MX3x_INT_UART2 (NR_IRQS_LEGACY + 32)
166#define MX3x_INT_SDMA 34 166#define MX3x_INT_NANDFC (NR_IRQS_LEGACY + 33)
167#define MX3x_INT_MSHC1 39 167#define MX3x_INT_SDMA (NR_IRQS_LEGACY + 34)
168#define MX3x_INT_IPU_ERR 41 168#define MX3x_INT_MSHC1 (NR_IRQS_LEGACY + 39)
169#define MX3x_INT_IPU_SYN 42 169#define MX3x_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
170#define MX3x_INT_UART1 45 170#define MX3x_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
171#define MX3x_INT_ECT 48 171#define MX3x_INT_UART1 (NR_IRQS_LEGACY + 45)
172#define MX3x_INT_SCC_SCM 49 172#define MX3x_INT_ECT (NR_IRQS_LEGACY + 48)
173#define MX3x_INT_SCC_SMN 50 173#define MX3x_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
174#define MX3x_INT_GPIO2 51 174#define MX3x_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
175#define MX3x_INT_GPIO1 52 175#define MX3x_INT_GPIO2 (NR_IRQS_LEGACY + 51)
176#define MX3x_INT_WDOG 55 176#define MX3x_INT_GPIO1 (NR_IRQS_LEGACY + 52)
177#define MX3x_INT_GPIO3 56 177#define MX3x_INT_WDOG (NR_IRQS_LEGACY + 55)
178#define MX3x_INT_EXT_POWER 58 178#define MX3x_INT_GPIO3 (NR_IRQS_LEGACY + 56)
179#define MX3x_INT_EXT_TEMPER 59 179#define MX3x_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
180#define MX3x_INT_EXT_SENSOR60 60 180#define MX3x_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
181#define MX3x_INT_EXT_SENSOR61 61 181#define MX3x_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
182#define MX3x_INT_EXT_WDOG 62 182#define MX3x_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
183#define MX3x_INT_EXT_TV 63 183#define MX3x_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
184#define MX3x_INT_EXT_TV (NR_IRQS_LEGACY + 63)
184 185
185#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ 186#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
186 187
diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h
index 5f2da75a47f4..09ac19c1570c 100644
--- a/arch/arm/plat-mxc/include/mach/mx50.h
+++ b/arch/arm/plat-mxc/include/mach/mx50.h
@@ -188,99 +188,100 @@
188/* 188/*
189 * Interrupt numbers 189 * Interrupt numbers
190 */ 190 */
191#define MX50_INT_MMC_SDHC1 1 191#include <asm/irq.h>
192#define MX50_INT_MMC_SDHC2 2 192#define MX50_INT_MMC_SDHC1 (NR_IRQS_LEGACY + 1)
193#define MX50_INT_MMC_SDHC3 3 193#define MX50_INT_MMC_SDHC2 (NR_IRQS_LEGACY + 2)
194#define MX50_INT_MMC_SDHC4 4 194#define MX50_INT_MMC_SDHC3 (NR_IRQS_LEGACY + 3)
195#define MX50_INT_DAP 5 195#define MX50_INT_MMC_SDHC4 (NR_IRQS_LEGACY + 4)
196#define MX50_INT_SDMA 6 196#define MX50_INT_DAP (NR_IRQS_LEGACY + 5)
197#define MX50_INT_IOMUX 7 197#define MX50_INT_SDMA (NR_IRQS_LEGACY + 6)
198#define MX50_INT_UART4 13 198#define MX50_INT_IOMUX (NR_IRQS_LEGACY + 7)
199#define MX50_INT_USB_H1 14 199#define MX50_INT_UART4 (NR_IRQS_LEGACY + 13)
200#define MX50_INT_USB_OTG 18 200#define MX50_INT_USB_H1 (NR_IRQS_LEGACY + 14)
201#define MX50_INT_DATABAHN 19 201#define MX50_INT_USB_OTG (NR_IRQS_LEGACY + 18)
202#define MX50_INT_ELCDIF 20 202#define MX50_INT_DATABAHN (NR_IRQS_LEGACY + 19)
203#define MX50_INT_EPXP 21 203#define MX50_INT_ELCDIF (NR_IRQS_LEGACY + 20)
204#define MX50_INT_SRTC_NTZ 24 204#define MX50_INT_EPXP (NR_IRQS_LEGACY + 21)
205#define MX50_INT_SRTC_TZ 25 205#define MX50_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
206#define MX50_INT_EPDC 27 206#define MX50_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
207#define MX50_INT_NIC 28 207#define MX50_INT_EPDC (NR_IRQS_LEGACY + 27)
208#define MX50_INT_SSI1 29 208#define MX50_INT_NIC (NR_IRQS_LEGACY + 28)
209#define MX50_INT_SSI2 30 209#define MX50_INT_SSI1 (NR_IRQS_LEGACY + 29)
210#define MX50_INT_UART1 31 210#define MX50_INT_SSI2 (NR_IRQS_LEGACY + 30)
211#define MX50_INT_UART2 32 211#define MX50_INT_UART1 (NR_IRQS_LEGACY + 31)
212#define MX50_INT_UART3 33 212#define MX50_INT_UART2 (NR_IRQS_LEGACY + 32)
213#define MX50_INT_RESV34 34 213#define MX50_INT_UART3 (NR_IRQS_LEGACY + 33)
214#define MX50_INT_RESV35 35 214#define MX50_INT_RESV34 (NR_IRQS_LEGACY + 34)
215#define MX50_INT_CSPI1 36 215#define MX50_INT_RESV35 (NR_IRQS_LEGACY + 35)
216#define MX50_INT_CSPI2 37 216#define MX50_INT_CSPI1 (NR_IRQS_LEGACY + 36)
217#define MX50_INT_CSPI 38 217#define MX50_INT_CSPI2 (NR_IRQS_LEGACY + 37)
218#define MX50_INT_GPT 39 218#define MX50_INT_CSPI (NR_IRQS_LEGACY + 38)
219#define MX50_INT_EPIT1 40 219#define MX50_INT_GPT (NR_IRQS_LEGACY + 39)
220#define MX50_INT_GPIO1_INT7 42 220#define MX50_INT_EPIT1 (NR_IRQS_LEGACY + 40)
221#define MX50_INT_GPIO1_INT6 43 221#define MX50_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
222#define MX50_INT_GPIO1_INT5 44 222#define MX50_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
223#define MX50_INT_GPIO1_INT4 45 223#define MX50_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
224#define MX50_INT_GPIO1_INT3 46 224#define MX50_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
225#define MX50_INT_GPIO1_INT2 47 225#define MX50_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
226#define MX50_INT_GPIO1_INT1 48 226#define MX50_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
227#define MX50_INT_GPIO1_INT0 49 227#define MX50_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
228#define MX50_INT_GPIO1_LOW 50 228#define MX50_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
229#define MX50_INT_GPIO1_HIGH 51 229#define MX50_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
230#define MX50_INT_GPIO2_LOW 52 230#define MX50_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
231#define MX50_INT_GPIO2_HIGH 53 231#define MX50_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
232#define MX50_INT_GPIO3_LOW 54 232#define MX50_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
233#define MX50_INT_GPIO3_HIGH 55 233#define MX50_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
234#define MX50_INT_GPIO4_LOW 56 234#define MX50_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
235#define MX50_INT_GPIO4_HIGH 57 235#define MX50_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
236#define MX50_INT_WDOG1 58 236#define MX50_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
237#define MX50_INT_KPP 60 237#define MX50_INT_WDOG1 (NR_IRQS_LEGACY + 58)
238#define MX50_INT_PWM1 61 238#define MX50_INT_KPP (NR_IRQS_LEGACY + 60)
239#define MX50_INT_I2C1 62 239#define MX50_INT_PWM1 (NR_IRQS_LEGACY + 61)
240#define MX50_INT_I2C2 63 240#define MX50_INT_I2C1 (NR_IRQS_LEGACY + 62)
241#define MX50_INT_I2C3 64 241#define MX50_INT_I2C2 (NR_IRQS_LEGACY + 63)
242#define MX50_INT_RESV65 65 242#define MX50_INT_I2C3 (NR_IRQS_LEGACY + 64)
243#define MX50_INT_DCDC 66 243#define MX50_INT_RESV65 (NR_IRQS_LEGACY + 65)
244#define MX50_INT_THERMAL_ALARM 67 244#define MX50_INT_DCDC (NR_IRQS_LEGACY + 66)
245#define MX50_INT_ANA3 68 245#define MX50_INT_THERMAL_ALARM (NR_IRQS_LEGACY + 67)
246#define MX50_INT_ANA4 69 246#define MX50_INT_ANA3 (NR_IRQS_LEGACY + 68)
247#define MX50_INT_CCM1 71 247#define MX50_INT_ANA4 (NR_IRQS_LEGACY + 69)
248#define MX50_INT_CCM2 72 248#define MX50_INT_CCM1 (NR_IRQS_LEGACY + 71)
249#define MX50_INT_GPC1 73 249#define MX50_INT_CCM2 (NR_IRQS_LEGACY + 72)
250#define MX50_INT_GPC2 74 250#define MX50_INT_GPC1 (NR_IRQS_LEGACY + 73)
251#define MX50_INT_SRC 75 251#define MX50_INT_GPC2 (NR_IRQS_LEGACY + 74)
252#define MX50_INT_NM 76 252#define MX50_INT_SRC (NR_IRQS_LEGACY + 75)
253#define MX50_INT_PMU 77 253#define MX50_INT_NM (NR_IRQS_LEGACY + 76)
254#define MX50_INT_CTI_IRQ 78 254#define MX50_INT_PMU (NR_IRQS_LEGACY + 77)
255#define MX50_INT_CTI1_TG0 79 255#define MX50_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
256#define MX50_INT_CTI1_TG1 80 256#define MX50_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
257#define MX50_INT_GPU2_IRQ 84 257#define MX50_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
258#define MX50_INT_GPU2_BUSY 85 258#define MX50_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
259#define MX50_INT_UART5 86 259#define MX50_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
260#define MX50_INT_FEC 87 260#define MX50_INT_UART5 (NR_IRQS_LEGACY + 86)
261#define MX50_INT_OWIRE 88 261#define MX50_INT_FEC (NR_IRQS_LEGACY + 87)
262#define MX50_INT_CTI1_TG2 89 262#define MX50_INT_OWIRE (NR_IRQS_LEGACY + 88)
263#define MX50_INT_SJC 90 263#define MX50_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
264#define MX50_INT_DCP_CHAN1_3 91 264#define MX50_INT_SJC (NR_IRQS_LEGACY + 90)
265#define MX50_INT_DCP_CHAN0 92 265#define MX50_INT_DCP_CHAN1_3 (NR_IRQS_LEGACY + 91)
266#define MX50_INT_PWM2 94 266#define MX50_INT_DCP_CHAN0 (NR_IRQS_LEGACY + 92)
267#define MX50_INT_RNGB 97 267#define MX50_INT_PWM2 (NR_IRQS_LEGACY + 94)
268#define MX50_INT_CTI1_TG3 98 268#define MX50_INT_RNGB (NR_IRQS_LEGACY + 97)
269#define MX50_INT_RAWNAND_BCH 100 269#define MX50_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
270#define MX50_INT_RAWNAND_GPMI 102 270#define MX50_INT_RAWNAND_BCH (NR_IRQS_LEGACY + 100)
271#define MX50_INT_GPIO5_LOW 103 271#define MX50_INT_RAWNAND_GPMI (NR_IRQS_LEGACY + 102)
272#define MX50_INT_GPIO5_HIGH 104 272#define MX50_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
273#define MX50_INT_GPIO6_LOW 105 273#define MX50_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
274#define MX50_INT_GPIO6_HIGH 106 274#define MX50_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
275#define MX50_INT_MSHC 109 275#define MX50_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
276#define MX50_INT_APBHDMA_CHAN0 110 276#define MX50_INT_MSHC (NR_IRQS_LEGACY + 109)
277#define MX50_INT_APBHDMA_CHAN1 111 277#define MX50_INT_APBHDMA_CHAN0 (NR_IRQS_LEGACY + 110)
278#define MX50_INT_APBHDMA_CHAN2 112 278#define MX50_INT_APBHDMA_CHAN1 (NR_IRQS_LEGACY + 111)
279#define MX50_INT_APBHDMA_CHAN3 113 279#define MX50_INT_APBHDMA_CHAN2 (NR_IRQS_LEGACY + 112)
280#define MX50_INT_APBHDMA_CHAN4 114 280#define MX50_INT_APBHDMA_CHAN3 (NR_IRQS_LEGACY + 113)
281#define MX50_INT_APBHDMA_CHAN5 115 281#define MX50_INT_APBHDMA_CHAN4 (NR_IRQS_LEGACY + 114)
282#define MX50_INT_APBHDMA_CHAN6 116 282#define MX50_INT_APBHDMA_CHAN5 (NR_IRQS_LEGACY + 115)
283#define MX50_INT_APBHDMA_CHAN7 117 283#define MX50_INT_APBHDMA_CHAN6 (NR_IRQS_LEGACY + 116)
284#define MX50_INT_APBHDMA_CHAN7 (NR_IRQS_LEGACY + 117)
284 285
285#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 286#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
286extern int mx50_revision(void); 287extern int mx50_revision(void);
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index cdf07c65ec1e..af844f76261a 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -232,110 +232,111 @@
232/* 232/*
233 * Interrupt numbers 233 * Interrupt numbers
234 */ 234 */
235#define MX51_INT_BASE 0 235#include <asm/irq.h>
236#define MX51_INT_RESV0 0 236#define MX51_INT_BASE (NR_IRQS_LEGACY + 0)
237#define MX51_INT_ESDHC1 1 237#define MX51_INT_RESV0 (NR_IRQS_LEGACY + 0)
238#define MX51_INT_ESDHC2 2 238#define MX51_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
239#define MX51_INT_ESDHC3 3 239#define MX51_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
240#define MX51_INT_ESDHC4 4 240#define MX51_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
241#define MX51_INT_RESV5 5 241#define MX51_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
242#define MX51_INT_SDMA 6 242#define MX51_INT_RESV5 (NR_IRQS_LEGACY + 5)
243#define MX51_INT_IOMUX 7 243#define MX51_INT_SDMA (NR_IRQS_LEGACY + 6)
244#define MX51_INT_NFC 8 244#define MX51_INT_IOMUX (NR_IRQS_LEGACY + 7)
245#define MX51_INT_VPU 9 245#define MX51_INT_NFC (NR_IRQS_LEGACY + 8)
246#define MX51_INT_IPU_ERR 10 246#define MX51_INT_VPU (NR_IRQS_LEGACY + 9)
247#define MX51_INT_IPU_SYN 11 247#define MX51_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
248#define MX51_INT_GPU 12 248#define MX51_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
249#define MX51_INT_RESV13 13 249#define MX51_INT_GPU (NR_IRQS_LEGACY + 12)
250#define MX51_INT_USB_HS1 14 250#define MX51_INT_RESV13 (NR_IRQS_LEGACY + 13)
251#define MX51_INT_EMI 15 251#define MX51_INT_USB_HS1 (NR_IRQS_LEGACY + 14)
252#define MX51_INT_USB_HS2 16 252#define MX51_INT_EMI (NR_IRQS_LEGACY + 15)
253#define MX51_INT_USB_HS3 17 253#define MX51_INT_USB_HS2 (NR_IRQS_LEGACY + 16)
254#define MX51_INT_USB_OTG 18 254#define MX51_INT_USB_HS3 (NR_IRQS_LEGACY + 17)
255#define MX51_INT_SAHARA_H0 19 255#define MX51_INT_USB_OTG (NR_IRQS_LEGACY + 18)
256#define MX51_INT_SAHARA_H1 20 256#define MX51_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
257#define MX51_INT_SCC_SMN 21 257#define MX51_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
258#define MX51_INT_SCC_STZ 22 258#define MX51_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
259#define MX51_INT_SCC_SCM 23 259#define MX51_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
260#define MX51_INT_SRTC_NTZ 24 260#define MX51_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
261#define MX51_INT_SRTC_TZ 25 261#define MX51_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
262#define MX51_INT_RTIC 26 262#define MX51_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
263#define MX51_INT_CSU 27 263#define MX51_INT_RTIC (NR_IRQS_LEGACY + 26)
264#define MX51_INT_SLIM_B 28 264#define MX51_INT_CSU (NR_IRQS_LEGACY + 27)
265#define MX51_INT_SSI1 29 265#define MX51_INT_SLIM_B (NR_IRQS_LEGACY + 28)
266#define MX51_INT_SSI2 30 266#define MX51_INT_SSI1 (NR_IRQS_LEGACY + 29)
267#define MX51_INT_UART1 31 267#define MX51_INT_SSI2 (NR_IRQS_LEGACY + 30)
268#define MX51_INT_UART2 32 268#define MX51_INT_UART1 (NR_IRQS_LEGACY + 31)
269#define MX51_INT_UART3 33 269#define MX51_INT_UART2 (NR_IRQS_LEGACY + 32)
270#define MX51_INT_RESV34 34 270#define MX51_INT_UART3 (NR_IRQS_LEGACY + 33)
271#define MX51_INT_RESV35 35 271#define MX51_INT_RESV34 (NR_IRQS_LEGACY + 34)
272#define MX51_INT_ECSPI1 36 272#define MX51_INT_RESV35 (NR_IRQS_LEGACY + 35)
273#define MX51_INT_ECSPI2 37 273#define MX51_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
274#define MX51_INT_CSPI 38 274#define MX51_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
275#define MX51_INT_GPT 39 275#define MX51_INT_CSPI (NR_IRQS_LEGACY + 38)
276#define MX51_INT_EPIT1 40 276#define MX51_INT_GPT (NR_IRQS_LEGACY + 39)
277#define MX51_INT_EPIT2 41 277#define MX51_INT_EPIT1 (NR_IRQS_LEGACY + 40)
278#define MX51_INT_GPIO1_INT7 42 278#define MX51_INT_EPIT2 (NR_IRQS_LEGACY + 41)
279#define MX51_INT_GPIO1_INT6 43 279#define MX51_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
280#define MX51_INT_GPIO1_INT5 44 280#define MX51_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
281#define MX51_INT_GPIO1_INT4 45 281#define MX51_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
282#define MX51_INT_GPIO1_INT3 46 282#define MX51_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
283#define MX51_INT_GPIO1_INT2 47 283#define MX51_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
284#define MX51_INT_GPIO1_INT1 48 284#define MX51_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
285#define MX51_INT_GPIO1_INT0 49 285#define MX51_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
286#define MX51_INT_GPIO1_LOW 50 286#define MX51_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
287#define MX51_INT_GPIO1_HIGH 51 287#define MX51_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
288#define MX51_INT_GPIO2_LOW 52 288#define MX51_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
289#define MX51_INT_GPIO2_HIGH 53 289#define MX51_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
290#define MX51_INT_GPIO3_LOW 54 290#define MX51_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
291#define MX51_INT_GPIO3_HIGH 55 291#define MX51_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
292#define MX51_INT_GPIO4_LOW 56 292#define MX51_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
293#define MX51_INT_GPIO4_HIGH 57 293#define MX51_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
294#define MX51_INT_WDOG1 58 294#define MX51_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
295#define MX51_INT_WDOG2 59 295#define MX51_INT_WDOG1 (NR_IRQS_LEGACY + 58)
296#define MX51_INT_KPP 60 296#define MX51_INT_WDOG2 (NR_IRQS_LEGACY + 59)
297#define MX51_INT_PWM1 61 297#define MX51_INT_KPP (NR_IRQS_LEGACY + 60)
298#define MX51_INT_I2C1 62 298#define MX51_INT_PWM1 (NR_IRQS_LEGACY + 61)
299#define MX51_INT_I2C2 63 299#define MX51_INT_I2C1 (NR_IRQS_LEGACY + 62)
300#define MX51_INT_HS_I2C 64 300#define MX51_INT_I2C2 (NR_IRQS_LEGACY + 63)
301#define MX51_INT_RESV65 65 301#define MX51_INT_HS_I2C (NR_IRQS_LEGACY + 64)
302#define MX51_INT_RESV66 66 302#define MX51_INT_RESV65 (NR_IRQS_LEGACY + 65)
303#define MX51_INT_SIM_IPB 67 303#define MX51_INT_RESV66 (NR_IRQS_LEGACY + 66)
304#define MX51_INT_SIM_DAT 68 304#define MX51_INT_SIM_IPB (NR_IRQS_LEGACY + 67)
305#define MX51_INT_IIM 69 305#define MX51_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
306#define MX51_INT_ATA 70 306#define MX51_INT_IIM (NR_IRQS_LEGACY + 69)
307#define MX51_INT_CCM1 71 307#define MX51_INT_ATA (NR_IRQS_LEGACY + 70)
308#define MX51_INT_CCM2 72 308#define MX51_INT_CCM1 (NR_IRQS_LEGACY + 71)
309#define MX51_INT_GPC1 73 309#define MX51_INT_CCM2 (NR_IRQS_LEGACY + 72)
310#define MX51_INT_GPC2 74 310#define MX51_INT_GPC1 (NR_IRQS_LEGACY + 73)
311#define MX51_INT_SRC 75 311#define MX51_INT_GPC2 (NR_IRQS_LEGACY + 74)
312#define MX51_INT_NM 76 312#define MX51_INT_SRC (NR_IRQS_LEGACY + 75)
313#define MX51_INT_PMU 77 313#define MX51_INT_NM (NR_IRQS_LEGACY + 76)
314#define MX51_INT_CTI_IRQ 78 314#define MX51_INT_PMU (NR_IRQS_LEGACY + 77)
315#define MX51_INT_CTI1_TG0 79 315#define MX51_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
316#define MX51_INT_CTI1_TG1 80 316#define MX51_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
317#define MX51_INT_MCG_ERR 81 317#define MX51_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
318#define MX51_INT_MCG_TMR 82 318#define MX51_INT_MCG_ERR (NR_IRQS_LEGACY + 81)
319#define MX51_INT_MCG_FUNC 83 319#define MX51_INT_MCG_TMR (NR_IRQS_LEGACY + 82)
320#define MX51_INT_GPU2_IRQ 84 320#define MX51_INT_MCG_FUNC (NR_IRQS_LEGACY + 83)
321#define MX51_INT_GPU2_BUSY 85 321#define MX51_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
322#define MX51_INT_RESV86 86 322#define MX51_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
323#define MX51_INT_FEC 87 323#define MX51_INT_RESV86 (NR_IRQS_LEGACY + 86)
324#define MX51_INT_OWIRE 88 324#define MX51_INT_FEC (NR_IRQS_LEGACY + 87)
325#define MX51_INT_CTI1_TG2 89 325#define MX51_INT_OWIRE (NR_IRQS_LEGACY + 88)
326#define MX51_INT_SJC 90 326#define MX51_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
327#define MX51_INT_SPDIF 91 327#define MX51_INT_SJC (NR_IRQS_LEGACY + 90)
328#define MX51_INT_TVE 92 328#define MX51_INT_SPDIF (NR_IRQS_LEGACY + 91)
329#define MX51_INT_FIRI 93 329#define MX51_INT_TVE (NR_IRQS_LEGACY + 92)
330#define MX51_INT_PWM2 94 330#define MX51_INT_FIRI (NR_IRQS_LEGACY + 93)
331#define MX51_INT_SLIM_EXP 95 331#define MX51_INT_PWM2 (NR_IRQS_LEGACY + 94)
332#define MX51_INT_SSI3 96 332#define MX51_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
333#define MX51_INT_EMI_BOOT 97 333#define MX51_INT_SSI3 (NR_IRQS_LEGACY + 96)
334#define MX51_INT_CTI1_TG3 98 334#define MX51_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
335#define MX51_INT_SMC_RX 99 335#define MX51_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
336#define MX51_INT_VPU_IDLE 100 336#define MX51_INT_SMC_RX (NR_IRQS_LEGACY + 99)
337#define MX51_INT_EMI_NFC 101 337#define MX51_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
338#define MX51_INT_GPU_IDLE 102 338#define MX51_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
339#define MX51_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
339 340
340#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 341#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
341extern int mx51_revision(void); 342extern int mx51_revision(void);
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index a37e8c353994..f829d1c22501 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -229,113 +229,114 @@
229/* 229/*
230 * Interrupt numbers 230 * Interrupt numbers
231 */ 231 */
232#define MX53_INT_RESV0 0 232#include <asm/irq.h>
233#define MX53_INT_ESDHC1 1 233#define MX53_INT_RESV0 (NR_IRQS_LEGACY + 0)
234#define MX53_INT_ESDHC2 2 234#define MX53_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
235#define MX53_INT_ESDHC3 3 235#define MX53_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
236#define MX53_INT_ESDHC4 4 236#define MX53_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
237#define MX53_INT_DAP 5 237#define MX53_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
238#define MX53_INT_SDMA 6 238#define MX53_INT_DAP (NR_IRQS_LEGACY + 5)
239#define MX53_INT_IOMUX 7 239#define MX53_INT_SDMA (NR_IRQS_LEGACY + 6)
240#define MX53_INT_NFC 8 240#define MX53_INT_IOMUX (NR_IRQS_LEGACY + 7)
241#define MX53_INT_VPU 9 241#define MX53_INT_NFC (NR_IRQS_LEGACY + 8)
242#define MX53_INT_IPU_ERR 10 242#define MX53_INT_VPU (NR_IRQS_LEGACY + 9)
243#define MX53_INT_IPU_SYN 11 243#define MX53_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
244#define MX53_INT_GPU 12 244#define MX53_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
245#define MX53_INT_UART4 13 245#define MX53_INT_GPU (NR_IRQS_LEGACY + 12)
246#define MX53_INT_USB_H1 14 246#define MX53_INT_UART4 (NR_IRQS_LEGACY + 13)
247#define MX53_INT_EMI 15 247#define MX53_INT_USB_H1 (NR_IRQS_LEGACY + 14)
248#define MX53_INT_USB_H2 16 248#define MX53_INT_EMI (NR_IRQS_LEGACY + 15)
249#define MX53_INT_USB_H3 17 249#define MX53_INT_USB_H2 (NR_IRQS_LEGACY + 16)
250#define MX53_INT_USB_OTG 18 250#define MX53_INT_USB_H3 (NR_IRQS_LEGACY + 17)
251#define MX53_INT_SAHARA_H0 19 251#define MX53_INT_USB_OTG (NR_IRQS_LEGACY + 18)
252#define MX53_INT_SAHARA_H1 20 252#define MX53_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
253#define MX53_INT_SCC_SMN 21 253#define MX53_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
254#define MX53_INT_SCC_STZ 22 254#define MX53_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
255#define MX53_INT_SCC_SCM 23 255#define MX53_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
256#define MX53_INT_SRTC_NTZ 24 256#define MX53_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
257#define MX53_INT_SRTC_TZ 25 257#define MX53_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
258#define MX53_INT_RTIC 26 258#define MX53_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
259#define MX53_INT_CSU 27 259#define MX53_INT_RTIC (NR_IRQS_LEGACY + 26)
260#define MX53_INT_SATA 28 260#define MX53_INT_CSU (NR_IRQS_LEGACY + 27)
261#define MX53_INT_SSI1 29 261#define MX53_INT_SATA (NR_IRQS_LEGACY + 28)
262#define MX53_INT_SSI2 30 262#define MX53_INT_SSI1 (NR_IRQS_LEGACY + 29)
263#define MX53_INT_UART1 31 263#define MX53_INT_SSI2 (NR_IRQS_LEGACY + 30)
264#define MX53_INT_UART2 32 264#define MX53_INT_UART1 (NR_IRQS_LEGACY + 31)
265#define MX53_INT_UART3 33 265#define MX53_INT_UART2 (NR_IRQS_LEGACY + 32)
266#define MX53_INT_RTC 34 266#define MX53_INT_UART3 (NR_IRQS_LEGACY + 33)
267#define MX53_INT_PTP 35 267#define MX53_INT_RTC (NR_IRQS_LEGACY + 34)
268#define MX53_INT_ECSPI1 36 268#define MX53_INT_PTP (NR_IRQS_LEGACY + 35)
269#define MX53_INT_ECSPI2 37 269#define MX53_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
270#define MX53_INT_CSPI 38 270#define MX53_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
271#define MX53_INT_GPT 39 271#define MX53_INT_CSPI (NR_IRQS_LEGACY + 38)
272#define MX53_INT_EPIT1 40 272#define MX53_INT_GPT (NR_IRQS_LEGACY + 39)
273#define MX53_INT_EPIT2 41 273#define MX53_INT_EPIT1 (NR_IRQS_LEGACY + 40)
274#define MX53_INT_GPIO1_INT7 42 274#define MX53_INT_EPIT2 (NR_IRQS_LEGACY + 41)
275#define MX53_INT_GPIO1_INT6 43 275#define MX53_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
276#define MX53_INT_GPIO1_INT5 44 276#define MX53_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
277#define MX53_INT_GPIO1_INT4 45 277#define MX53_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
278#define MX53_INT_GPIO1_INT3 46 278#define MX53_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
279#define MX53_INT_GPIO1_INT2 47 279#define MX53_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
280#define MX53_INT_GPIO1_INT1 48 280#define MX53_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
281#define MX53_INT_GPIO1_INT0 49 281#define MX53_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
282#define MX53_INT_GPIO1_LOW 50 282#define MX53_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
283#define MX53_INT_GPIO1_HIGH 51 283#define MX53_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
284#define MX53_INT_GPIO2_LOW 52 284#define MX53_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
285#define MX53_INT_GPIO2_HIGH 53 285#define MX53_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
286#define MX53_INT_GPIO3_LOW 54 286#define MX53_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
287#define MX53_INT_GPIO3_HIGH 55 287#define MX53_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
288#define MX53_INT_GPIO4_LOW 56 288#define MX53_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
289#define MX53_INT_GPIO4_HIGH 57 289#define MX53_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
290#define MX53_INT_WDOG1 58 290#define MX53_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
291#define MX53_INT_WDOG2 59 291#define MX53_INT_WDOG1 (NR_IRQS_LEGACY + 58)
292#define MX53_INT_KPP 60 292#define MX53_INT_WDOG2 (NR_IRQS_LEGACY + 59)
293#define MX53_INT_PWM1 61 293#define MX53_INT_KPP (NR_IRQS_LEGACY + 60)
294#define MX53_INT_I2C1 62 294#define MX53_INT_PWM1 (NR_IRQS_LEGACY + 61)
295#define MX53_INT_I2C2 63 295#define MX53_INT_I2C1 (NR_IRQS_LEGACY + 62)
296#define MX53_INT_I2C3 64 296#define MX53_INT_I2C2 (NR_IRQS_LEGACY + 63)
297#define MX53_INT_MLB 65 297#define MX53_INT_I2C3 (NR_IRQS_LEGACY + 64)
298#define MX53_INT_ASRC 66 298#define MX53_INT_MLB (NR_IRQS_LEGACY + 65)
299#define MX53_INT_SPDIF 67 299#define MX53_INT_ASRC (NR_IRQS_LEGACY + 66)
300#define MX53_INT_SIM_DAT 68 300#define MX53_INT_SPDIF (NR_IRQS_LEGACY + 67)
301#define MX53_INT_IIM 69 301#define MX53_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
302#define MX53_INT_ATA 70 302#define MX53_INT_IIM (NR_IRQS_LEGACY + 69)
303#define MX53_INT_CCM1 71 303#define MX53_INT_ATA (NR_IRQS_LEGACY + 70)
304#define MX53_INT_CCM2 72 304#define MX53_INT_CCM1 (NR_IRQS_LEGACY + 71)
305#define MX53_INT_GPC1 73 305#define MX53_INT_CCM2 (NR_IRQS_LEGACY + 72)
306#define MX53_INT_GPC2 74 306#define MX53_INT_GPC1 (NR_IRQS_LEGACY + 73)
307#define MX53_INT_SRC 75 307#define MX53_INT_GPC2 (NR_IRQS_LEGACY + 74)
308#define MX53_INT_NM 76 308#define MX53_INT_SRC (NR_IRQS_LEGACY + 75)
309#define MX53_INT_PMU 77 309#define MX53_INT_NM (NR_IRQS_LEGACY + 76)
310#define MX53_INT_CTI_IRQ 78 310#define MX53_INT_PMU (NR_IRQS_LEGACY + 77)
311#define MX53_INT_CTI1_TG0 79 311#define MX53_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
312#define MX53_INT_CTI1_TG1 80 312#define MX53_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
313#define MX53_INT_ESAI 81 313#define MX53_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
314#define MX53_INT_CAN1 82 314#define MX53_INT_ESAI (NR_IRQS_LEGACY + 81)
315#define MX53_INT_CAN2 83 315#define MX53_INT_CAN1 (NR_IRQS_LEGACY + 82)
316#define MX53_INT_GPU2_IRQ 84 316#define MX53_INT_CAN2 (NR_IRQS_LEGACY + 83)
317#define MX53_INT_GPU2_BUSY 85 317#define MX53_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
318#define MX53_INT_UART5 86 318#define MX53_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
319#define MX53_INT_FEC 87 319#define MX53_INT_UART5 (NR_IRQS_LEGACY + 86)
320#define MX53_INT_OWIRE 88 320#define MX53_INT_FEC (NR_IRQS_LEGACY + 87)
321#define MX53_INT_CTI1_TG2 89 321#define MX53_INT_OWIRE (NR_IRQS_LEGACY + 88)
322#define MX53_INT_SJC 90 322#define MX53_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
323#define MX53_INT_TVE 92 323#define MX53_INT_SJC (NR_IRQS_LEGACY + 90)
324#define MX53_INT_FIRI 93 324#define MX53_INT_TVE (NR_IRQS_LEGACY + 92)
325#define MX53_INT_PWM2 94 325#define MX53_INT_FIRI (NR_IRQS_LEGACY + 93)
326#define MX53_INT_SLIM_EXP 95 326#define MX53_INT_PWM2 (NR_IRQS_LEGACY + 94)
327#define MX53_INT_SSI3 96 327#define MX53_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
328#define MX53_INT_EMI_BOOT 97 328#define MX53_INT_SSI3 (NR_IRQS_LEGACY + 96)
329#define MX53_INT_CTI1_TG3 98 329#define MX53_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
330#define MX53_INT_SMC_RX 99 330#define MX53_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
331#define MX53_INT_VPU_IDLE 100 331#define MX53_INT_SMC_RX (NR_IRQS_LEGACY + 99)
332#define MX53_INT_EMI_NFC 101 332#define MX53_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
333#define MX53_INT_GPU_IDLE 102 333#define MX53_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
334#define MX53_INT_GPIO5_LOW 103 334#define MX53_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
335#define MX53_INT_GPIO5_HIGH 104 335#define MX53_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
336#define MX53_INT_GPIO6_LOW 105 336#define MX53_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
337#define MX53_INT_GPIO6_HIGH 106 337#define MX53_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
338#define MX53_INT_GPIO7_LOW 107 338#define MX53_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
339#define MX53_INT_GPIO7_HIGH 108 339#define MX53_INT_GPIO7_LOW (NR_IRQS_LEGACY + 107)
340#define MX53_INT_GPIO7_HIGH (NR_IRQS_LEGACY + 108)
340 341
341#endif /* ifndef __MACH_MX53_H__ */ 342#endif /* ifndef __MACH_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
index 9ffd1bbe615f..7eb9d1329671 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
@@ -20,13 +20,15 @@
20#define MXC_EHCI_INTERFACE_MASK (0xf) 20#define MXC_EHCI_INTERFACE_MASK (0xf)
21 21
22#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) 22#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
23#define MXC_EHCI_TTL_ENABLED (1 << 6) 23#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6)
24 24#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7)
25#define MXC_EHCI_INTERNAL_PHY (1 << 7) 25#define MXC_EHCI_TTL_ENABLED (1 << 8)
26#define MXC_EHCI_IPPUE_DOWN (1 << 8) 26
27#define MXC_EHCI_IPPUE_UP (1 << 9) 27#define MXC_EHCI_INTERNAL_PHY (1 << 9)
28#define MXC_EHCI_WAKEUP_ENABLED (1 << 10) 28#define MXC_EHCI_IPPUE_DOWN (1 << 10)
29#define MXC_EHCI_ITC_NO_THRESHOLD (1 << 11) 29#define MXC_EHCI_IPPUE_UP (1 << 11)
30#define MXC_EHCI_WAKEUP_ENABLED (1 << 12)
31#define MXC_EHCI_ITC_NO_THRESHOLD (1 << 13)
30 32
31#define MXC_USBCTRL_OFFSET 0 33#define MXC_USBCTRL_OFFSET 0
32#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 34#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 11:54:07 -0500