1 files changed, 86 insertions, 97 deletions

diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index dede19a766ff..cdf07c65ec1e 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -18,18 +18,6 @@
 #define MX51_GPU_CTRL_BASE_ADDR         0x30000000
 #define MX51_IPU_CTRL_BASE_ADDR         0x40000000
 
-#define MX51_DEBUG_BASE_ADDR            0x60000000
-#define MX51_DEBUG_SIZE                 SZ_1M
-
-#define MX51_ETB_BASE_ADDR              (MX51_DEBUG_BASE_ADDR + 0x01000)
-#define MX51_ETM_BASE_ADDR              (MX51_DEBUG_BASE_ADDR + 0x02000)
-#define MX51_TPIU_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x03000)
-#define MX51_CTI0_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x04000)
-#define MX51_CTI1_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x05000)
-#define MX51_CTI2_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x06000)
-#define MX51_CTI3_BASE_ADDR             (MX51_DEBUG_BASE_ADDR + 0x07000)
-#define MX51_CORTEX_DBG_BASE_ADDR       (MX51_DEBUG_BASE_ADDR + 0x08000)
-
 /*
  * SPBA global module enabled #0
  */
@@ -55,7 +43,10 @@
 #define MX51_AIPS1_BASE_ADDR            0x73f00000
 #define MX51_AIPS1_SIZE                 SZ_1M
 
-#define MX51_OTG_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0x80000)
+#define MX51_USB_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0x80000)
+#define MX51_USB_OTG_BASE_ADDR          (MX51_USB_BASE_ADDR + 0x0000)
+#define MX51_USB_HS1_BASE_ADDR          (MX51_USB_BASE_ADDR + 0x0200)
+#define MX51_USB_HS2_BASE_ADDR          (MX51_USB_BASE_ADDR + 0x0400)
 #define MX51_GPIO1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x84000)
 #define MX51_GPIO2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x88000)
 #define MX51_GPIO3_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x8c000)
@@ -132,6 +123,7 @@
 
 #define MX51_GPU2D_BASE_ADDR            0xd0000000
 #define MX51_TZIC_BASE_ADDR             0xe0000000
+#define MX51_TZIC_SIZE                  SZ_16K
 
 #define MX51_IO_P2V(x)                  IMX_IO_P2V(x)
 #define MX51_IO_ADDRESS(x)              IOMEM(MX51_IO_P2V(x))
@@ -240,117 +232,114 @@
 /*
  * Interrupt numbers
  */
-#define MX51_MXC_INT_BASE               0
-#define MX51_MXC_INT_RESV0              0
+#define MX51_INT_BASE                   0
+#define MX51_INT_RESV0                  0
 #define MX51_INT_ESDHC1                 1
 #define MX51_INT_ESDHC2                 2
 #define MX51_INT_ESDHC3                 3
 #define MX51_INT_ESDHC4                 4
-#define MX51_MXC_INT_RESV5              5
+#define MX51_INT_RESV5                  5
 #define MX51_INT_SDMA                   6
-#define MX51_MXC_INT_IOMUX              7
+#define MX51_INT_IOMUX                  7
 #define MX51_INT_NFC                    8
-#define MX51_MXC_INT_VPU                9
+#define MX51_INT_VPU                    9
 #define MX51_INT_IPU_ERR                10
 #define MX51_INT_IPU_SYN                11
-#define MX51_MXC_INT_GPU                12
-#define MX51_MXC_INT_RESV13             13
-#define MX51_MXC_INT_USB_H1             14
-#define MX51_MXC_INT_EMI                15
-#define MX51_MXC_INT_USB_H2             16
-#define MX51_MXC_INT_USB_H3             17
-#define MX51_MXC_INT_USB_OTG            18
-#define MX51_MXC_INT_SAHARA_H0          19
-#define MX51_MXC_INT_SAHARA_H1          20
-#define MX51_MXC_INT_SCC_SMN            21
-#define MX51_MXC_INT_SCC_STZ            22
-#define MX51_MXC_INT_SCC_SCM            23
-#define MX51_MXC_INT_SRTC_NTZ           24
-#define MX51_MXC_INT_SRTC_TZ            25
-#define MX51_MXC_INT_RTIC               26
-#define MX51_MXC_INT_CSU                27
-#define MX51_MXC_INT_SLIM_B             28
+#define MX51_INT_GPU                    12
+#define MX51_INT_RESV13                 13
+#define MX51_INT_USB_HS1                14
+#define MX51_INT_EMI                    15
+#define MX51_INT_USB_HS2                16
+#define MX51_INT_USB_HS3                17
+#define MX51_INT_USB_OTG                18
+#define MX51_INT_SAHARA_H0              19
+#define MX51_INT_SAHARA_H1              20
+#define MX51_INT_SCC_SMN                21
+#define MX51_INT_SCC_STZ                22
+#define MX51_INT_SCC_SCM                23
+#define MX51_INT_SRTC_NTZ               24
+#define MX51_INT_SRTC_TZ                25
+#define MX51_INT_RTIC                   26
+#define MX51_INT_CSU                    27
+#define MX51_INT_SLIM_B                 28
 #define MX51_INT_SSI1                   29
 #define MX51_INT_SSI2                   30
 #define MX51_INT_UART1                  31
 #define MX51_INT_UART2                  32
 #define MX51_INT_UART3                  33
-#define MX51_MXC_INT_RESV34             34
-#define MX51_MXC_INT_RESV35             35
+#define MX51_INT_RESV34                 34
+#define MX51_INT_RESV35                 35
 #define MX51_INT_ECSPI1                 36
 #define MX51_INT_ECSPI2                 37
 #define MX51_INT_CSPI                   38
-#define MX51_MXC_INT_GPT                39
-#define MX51_MXC_INT_EPIT1              40
-#define MX51_MXC_INT_EPIT2              41
-#define MX51_MXC_INT_GPIO1_INT7         42
-#define MX51_MXC_INT_GPIO1_INT6         43
-#define MX51_MXC_INT_GPIO1_INT5         44
-#define MX51_MXC_INT_GPIO1_INT4         45
-#define MX51_MXC_INT_GPIO1_INT3         46
-#define MX51_MXC_INT_GPIO1_INT2         47
-#define MX51_MXC_INT_GPIO1_INT1         48
-#define MX51_MXC_INT_GPIO1_INT0         49
-#define MX51_MXC_INT_GPIO1_LOW          50
-#define MX51_MXC_INT_GPIO1_HIGH         51
-#define MX51_MXC_INT_GPIO2_LOW          52
-#define MX51_MXC_INT_GPIO2_HIGH         53
-#define MX51_MXC_INT_GPIO3_LOW          54
-#define MX51_MXC_INT_GPIO3_HIGH         55
-#define MX51_MXC_INT_GPIO4_LOW          56
-#define MX51_MXC_INT_GPIO4_HIGH         57
-#define MX51_MXC_INT_WDOG1              58
-#define MX51_MXC_INT_WDOG2              59
+#define MX51_INT_GPT                    39
+#define MX51_INT_EPIT1                  40
+#define MX51_INT_EPIT2                  41
+#define MX51_INT_GPIO1_INT7             42
+#define MX51_INT_GPIO1_INT6             43
+#define MX51_INT_GPIO1_INT5             44
+#define MX51_INT_GPIO1_INT4             45
+#define MX51_INT_GPIO1_INT3             46
+#define MX51_INT_GPIO1_INT2             47
+#define MX51_INT_GPIO1_INT1             48
+#define MX51_INT_GPIO1_INT0             49
+#define MX51_INT_GPIO1_LOW              50
+#define MX51_INT_GPIO1_HIGH             51
+#define MX51_INT_GPIO2_LOW              52
+#define MX51_INT_GPIO2_HIGH             53
+#define MX51_INT_GPIO3_LOW              54
+#define MX51_INT_GPIO3_HIGH             55
+#define MX51_INT_GPIO4_LOW              56
+#define MX51_INT_GPIO4_HIGH             57
+#define MX51_INT_WDOG1                  58
+#define MX51_INT_WDOG2                  59
 #define MX51_INT_KPP                    60
 #define MX51_INT_PWM1                   61
 #define MX51_INT_I2C1                   62
 #define MX51_INT_I2C2                   63
-#define MX51_MXC_INT_HS_I2C             64
-#define MX51_MXC_INT_RESV65             65
-#define MX51_MXC_INT_RESV66             66
-#define MX51_MXC_INT_SIM_IPB            67
-#define MX51_MXC_INT_SIM_DAT            68
-#define MX51_MXC_INT_IIM                69
-#define MX51_MXC_INT_ATA                70
-#define MX51_MXC_INT_CCM1               71
-#define MX51_MXC_INT_CCM2               72
-#define MX51_MXC_INT_GPC1               73
-#define MX51_MXC_INT_GPC2               74
-#define MX51_MXC_INT_SRC                75
-#define MX51_MXC_INT_NM                 76
-#define MX51_MXC_INT_PMU                77
-#define MX51_MXC_INT_CTI_IRQ            78
-#define MX51_MXC_INT_CTI1_TG0           79
-#define MX51_MXC_INT_CTI1_TG1           80
-#define MX51_MXC_INT_MCG_ERR            81
-#define MX51_MXC_INT_MCG_TMR            82
-#define MX51_MXC_INT_MCG_FUNC           83
-#define MX51_MXC_INT_GPU2_IRQ           84
-#define MX51_MXC_INT_GPU2_BUSY          85
-#define MX51_MXC_INT_RESV86             86
+#define MX51_INT_HS_I2C                 64
+#define MX51_INT_RESV65                 65
+#define MX51_INT_RESV66                 66
+#define MX51_INT_SIM_IPB                67
+#define MX51_INT_SIM_DAT                68
+#define MX51_INT_IIM                    69
+#define MX51_INT_ATA                    70
+#define MX51_INT_CCM1                   71
+#define MX51_INT_CCM2                   72
+#define MX51_INT_GPC1                           73
+#define MX51_INT_GPC2                   74
+#define MX51_INT_SRC                    75
+#define MX51_INT_NM                     76
+#define MX51_INT_PMU                    77
+#define MX51_INT_CTI_IRQ                78
+#define MX51_INT_CTI1_TG0               79
+#define MX51_INT_CTI1_TG1               80
+#define MX51_INT_MCG_ERR                81
+#define MX51_INT_MCG_TMR                82
+#define MX51_INT_MCG_FUNC               83
+#define MX51_INT_GPU2_IRQ               84
+#define MX51_INT_GPU2_BUSY              85
+#define MX51_INT_RESV86                 86
 #define MX51_INT_FEC                    87
-#define MX51_MXC_INT_OWIRE              88
-#define MX51_MXC_INT_CTI1_TG2           89
-#define MX51_MXC_INT_SJC                90
-#define MX51_MXC_INT_SPDIF              91
-#define MX51_MXC_INT_TVE                92
-#define MX51_MXC_INT_FIRI               93
+#define MX51_INT_OWIRE                  88
+#define MX51_INT_CTI1_TG2               89
+#define MX51_INT_SJC                    90
+#define MX51_INT_SPDIF                  91
+#define MX51_INT_TVE                    92
+#define MX51_INT_FIRI                   93
 #define MX51_INT_PWM2                   94
-#define MX51_MXC_INT_SLIM_EXP           95
+#define MX51_INT_SLIM_EXP               95
 #define MX51_INT_SSI3                   96
-#define MX51_MXC_INT_EMI_BOOT           97
-#define MX51_MXC_INT_CTI1_TG3           98
-#define MX51_MXC_INT_SMC_RX             99
-#define MX51_MXC_INT_VPU_IDLE           100
-#define MX51_MXC_INT_EMI_NFC            101
-#define MX51_MXC_INT_GPU_IDLE           102
+#define MX51_INT_EMI_BOOT               97
+#define MX51_INT_CTI1_TG3               98
+#define MX51_INT_SMC_RX                 99
+#define MX51_INT_VPU_IDLE               100
+#define MX51_INT_EMI_NFC                101
+#define MX51_INT_GPU_IDLE               102
 
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 extern int mx51_revision(void);
 extern void mx51_display_revision(void);
 #endif
 
-/* tape-out 1 defines */
-#define MX51_TZIC_BASE_ADDR_TO1         0x8fffc000
-
 #endif  /* ifndef __MACH_MX51_H__ */