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-rw-r--r--arch/arm/plat-iop/Makefile8
-rw-r--r--arch/arm/plat-iop/gpio.c48
-rw-r--r--arch/arm/plat-iop/i2c.c81
-rw-r--r--arch/arm/plat-iop/pci.c247
-rw-r--r--arch/arm/plat-iop/setup.c38
-rw-r--r--arch/arm/plat-iop/time.c98
6 files changed, 520 insertions, 0 deletions
diff --git a/arch/arm/plat-iop/Makefile b/arch/arm/plat-iop/Makefile
new file mode 100644
index 000000000000..23da00b11517
--- /dev/null
+++ b/arch/arm/plat-iop/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for the linux kernel.
3#
4
5obj-y := gpio.o i2c.o pci.o setup.o time.o
6obj-m :=
7obj-n :=
8obj- :=
diff --git a/arch/arm/plat-iop/gpio.c b/arch/arm/plat-iop/gpio.c
new file mode 100644
index 000000000000..eda436083417
--- /dev/null
+++ b/arch/arm/plat-iop/gpio.c
@@ -0,0 +1,48 @@
1/*
2 * arch/arm/plat-iop/gpio.c
3 * GPIO handling for Intel IOP3xx processors.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or (at
10 * your option) any later version.
11 */
12
13#include <linux/device.h>
14#include <asm/hardware/iop3xx.h>
15
16void gpio_line_config(int line, int direction)
17{
18 unsigned long flags;
19
20 local_irq_save(flags);
21 if (direction == GPIO_IN) {
22 *IOP3XX_GPOE |= 1 << line;
23 } else if (direction == GPIO_OUT) {
24 *IOP3XX_GPOE &= ~(1 << line);
25 }
26 local_irq_restore(flags);
27}
28EXPORT_SYMBOL(gpio_line_config);
29
30int gpio_line_get(int line)
31{
32 return !!(*IOP3XX_GPID & (1 << line));
33}
34EXPORT_SYMBOL(gpio_line_get);
35
36void gpio_line_set(int line, int value)
37{
38 unsigned long flags;
39
40 local_irq_save(flags);
41 if (value == GPIO_LOW) {
42 *IOP3XX_GPOD &= ~(1 << line);
43 } else if (value == GPIO_HIGH) {
44 *IOP3XX_GPOD |= 1 << line;
45 }
46 local_irq_restore(flags);
47}
48EXPORT_SYMBOL(gpio_line_set);
diff --git a/arch/arm/plat-iop/i2c.c b/arch/arm/plat-iop/i2c.c
new file mode 100644
index 000000000000..e99909bdba71
--- /dev/null
+++ b/arch/arm/plat-iop/i2c.c
@@ -0,0 +1,81 @@
1/*
2 * arch/arm/plat-iop/i2c.c
3 *
4 * Author: Nicolas Pitre <nico@cam.org>
5 * Copyright (C) 2001 MontaVista Software, Inc.
6 * Copyright (C) 2004 Intel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/mm.h>
14#include <linux/init.h>
15#include <linux/major.h>
16#include <linux/fs.h>
17#include <linux/platform_device.h>
18#include <linux/serial.h>
19#include <linux/tty.h>
20#include <linux/serial_core.h>
21#include <asm/io.h>
22#include <asm/pgtable.h>
23#include <asm/page.h>
24#include <asm/mach/map.h>
25#include <asm/setup.h>
26#include <asm/system.h>
27#include <asm/memory.h>
28#include <asm/hardware.h>
29#include <asm/hardware/iop3xx.h>
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32
33#ifdef CONFIG_ARCH_IOP32X
34#define IRQ_IOP3XX_I2C_0 IRQ_IOP32X_I2C_0
35#define IRQ_IOP3XX_I2C_1 IRQ_IOP32X_I2C_1
36#endif
37#ifdef CONFIG_ARCH_IOP33X
38#define IRQ_IOP3XX_I2C_0 IRQ_IOP33X_I2C_0
39#define IRQ_IOP3XX_I2C_1 IRQ_IOP33X_I2C_1
40#endif
41
42static struct resource iop3xx_i2c0_resources[] = {
43 [0] = {
44 .start = 0xfffff680,
45 .end = 0xfffff697,
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = IRQ_IOP3XX_I2C_0,
50 .end = IRQ_IOP3XX_I2C_0,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
55struct platform_device iop3xx_i2c0_device = {
56 .name = "IOP3xx-I2C",
57 .id = 0,
58 .num_resources = 2,
59 .resource = iop3xx_i2c0_resources,
60};
61
62
63static struct resource iop3xx_i2c1_resources[] = {
64 [0] = {
65 .start = 0xfffff6a0,
66 .end = 0xfffff6b7,
67 .flags = IORESOURCE_MEM,
68 },
69 [1] = {
70 .start = IRQ_IOP3XX_I2C_1,
71 .end = IRQ_IOP3XX_I2C_1,
72 .flags = IORESOURCE_IRQ,
73 }
74};
75
76struct platform_device iop3xx_i2c1_device = {
77 .name = "IOP3xx-I2C",
78 .id = 1,
79 .num_resources = 2,
80 .resource = iop3xx_i2c1_resources,
81};
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
new file mode 100644
index 000000000000..e647812654f2
--- /dev/null
+++ b/arch/arm/plat-iop/pci.c
@@ -0,0 +1,247 @@
1/*
2 * arch/arm/plat-iop/pci.c
3 *
4 * PCI support for the Intel IOP32X and IOP33X processors
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/slab.h>
17#include <linux/mm.h>
18#include <linux/init.h>
19#include <linux/ioport.h>
20#include <asm/io.h>
21#include <asm/irq.h>
22#include <asm/system.h>
23#include <asm/hardware.h>
24#include <asm/mach/pci.h>
25#include <asm/hardware/iop3xx.h>
26
27// #define DEBUG
28
29#ifdef DEBUG
30#define DBG(x...) printk(x)
31#else
32#define DBG(x...) do { } while (0)
33#endif
34
35/*
36 * This routine builds either a type0 or type1 configuration command. If the
37 * bus is on the 803xx then a type0 made, else a type1 is created.
38 */
39static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where)
40{
41 struct pci_sys_data *sys = bus->sysdata;
42 u32 addr;
43
44 if (sys->busnr == bus->number)
45 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
46 else
47 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
48
49 addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
50
51 return addr;
52}
53
54/*
55 * This routine checks the status of the last configuration cycle. If an error
56 * was detected it returns a 1, else it returns a 0. The errors being checked
57 * are parity, master abort, target abort (master and target). These types of
58 * errors occure during a config cycle where there is no device, like during
59 * the discovery stage.
60 */
61static int iop3xx_pci_status(void)
62{
63 unsigned int status;
64 int ret = 0;
65
66 /*
67 * Check the status registers.
68 */
69 status = *IOP3XX_ATUSR;
70 if (status & 0xf900) {
71 DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
72 *IOP3XX_ATUSR = status & 0xf900;
73 ret = 1;
74 }
75
76 status = *IOP3XX_ATUISR;
77 if (status & 0x679f) {
78 DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
79 *IOP3XX_ATUISR = status & 0x679f;
80 ret = 1;
81 }
82
83 return ret;
84}
85
86/*
87 * Simply write the address register and read the configuration
88 * data. Note that the 4 nop's ensure that we are able to handle
89 * a delayed abort (in theory.)
90 */
91static inline u32 iop3xx_read(unsigned long addr)
92{
93 u32 val;
94
95 __asm__ __volatile__(
96 "str %1, [%2]\n\t"
97 "ldr %0, [%3]\n\t"
98 "nop\n\t"
99 "nop\n\t"
100 "nop\n\t"
101 "nop\n\t"
102 : "=r" (val)
103 : "r" (addr), "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
104
105 return val;
106}
107
108/*
109 * The read routines must check the error status of the last configuration
110 * cycle. If there was an error, the routine returns all hex f's.
111 */
112static int
113iop3xx_read_config(struct pci_bus *bus, unsigned int devfn, int where,
114 int size, u32 *value)
115{
116 unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
117 u32 val = iop3xx_read(addr) >> ((where & 3) * 8);
118
119 if (iop3xx_pci_status())
120 val = 0xffffffff;
121
122 *value = val;
123
124 return PCIBIOS_SUCCESSFUL;
125}
126
127static int
128iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where,
129 int size, u32 value)
130{
131 unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
132 u32 val;
133
134 if (size != 4) {
135 val = iop3xx_read(addr);
136 if (iop3xx_pci_status())
137 return PCIBIOS_SUCCESSFUL;
138
139 where = (where & 3) * 8;
140
141 if (size == 1)
142 val &= ~(0xff << where);
143 else
144 val &= ~(0xffff << where);
145
146 *IOP3XX_OCCDR = val | value << where;
147 } else {
148 asm volatile(
149 "str %1, [%2]\n\t"
150 "str %0, [%3]\n\t"
151 "nop\n\t"
152 "nop\n\t"
153 "nop\n\t"
154 "nop\n\t"
155 :
156 : "r" (value), "r" (addr),
157 "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
158 }
159
160 return PCIBIOS_SUCCESSFUL;
161}
162
163static struct pci_ops iop3xx_ops = {
164 .read = iop3xx_read_config,
165 .write = iop3xx_write_config,
166};
167
168/*
169 * When a PCI device does not exist during config cycles, the 80200 gets a
170 * bus error instead of returning 0xffffffff. This handler simply returns.
171 */
172static int
173iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
174{
175 DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
176 addr, fsr, regs->ARM_pc, regs->ARM_lr);
177
178 /*
179 * If it was an imprecise abort, then we need to correct the
180 * return address to be _after_ the instruction.
181 */
182 if (fsr & (1 << 10))
183 regs->ARM_pc += 4;
184
185 return 0;
186}
187
188int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
189{
190 struct resource *res;
191
192 if (nr != 0)
193 return 0;
194
195 res = kzalloc(2 * sizeof(struct resource), GFP_KERNEL);
196 if (!res)
197 panic("PCI: unable to alloc resources");
198
199 res[0].start = IOP3XX_PCI_LOWER_IO_VA;
200 res[0].end = IOP3XX_PCI_LOWER_IO_VA + IOP3XX_PCI_IO_WINDOW_SIZE - 1;
201 res[0].name = "IOP3XX PCI I/O Space";
202 res[0].flags = IORESOURCE_IO;
203 request_resource(&ioport_resource, &res[0]);
204
205 res[1].start = IOP3XX_PCI_LOWER_MEM_PA;
206 res[1].end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
207 res[1].name = "IOP3XX PCI Memory Space";
208 res[1].flags = IORESOURCE_MEM;
209 request_resource(&iomem_resource, &res[1]);
210
211 sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - IOP3XX_PCI_LOWER_MEM_BA;
212 sys->io_offset = IOP3XX_PCI_LOWER_IO_VA - IOP3XX_PCI_LOWER_IO_BA;
213
214 sys->resource[0] = &res[0];
215 sys->resource[1] = &res[1];
216 sys->resource[2] = NULL;
217
218 return 1;
219}
220
221struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys)
222{
223 return pci_scan_bus(sys->busnr, &iop3xx_ops, sys);
224}
225
226void iop3xx_pci_preinit(void)
227{
228 DBG("PCI: Intel 803xx PCI init code.\n");
229 DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
230 DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n",
231 *IOP3XX_OMWTVR0,
232 *IOP3XX_OIOWTVR);
233 DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
234 DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n",
235 *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);
236 DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0);
237 DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n",
238 *IOP3XX_IABAR1, *IOP3XX_IALR1);
239 DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n",
240 *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);
241 DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n",
242 *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);
243 DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n",
244 *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);
245
246 hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort");
247}
diff --git a/arch/arm/plat-iop/setup.c b/arch/arm/plat-iop/setup.c
new file mode 100644
index 000000000000..4689db638e95
--- /dev/null
+++ b/arch/arm/plat-iop/setup.c
@@ -0,0 +1,38 @@
1/*
2 * arch/arm/plat-iop/setup.c
3 *
4 * Author: Nicolas Pitre <nico@cam.org>
5 * Copyright (C) 2001 MontaVista Software, Inc.
6 * Copyright (C) 2004 Intel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/mm.h>
14#include <linux/init.h>
15#include <asm/mach/map.h>
16#include <asm/hardware/iop3xx.h>
17
18/*
19 * Standard IO mapping for all IOP3xx based systems
20 */
21static struct map_desc iop3xx_std_desc[] __initdata = {
22 { /* mem mapped registers */
23 .virtual = IOP3XX_PERIPHERAL_VIRT_BASE,
24 .pfn = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE),
25 .length = IOP3XX_PERIPHERAL_SIZE,
26 .type = MT_DEVICE,
27 }, { /* PCI IO space */
28 .virtual = IOP3XX_PCI_LOWER_IO_VA,
29 .pfn = __phys_to_pfn(IOP3XX_PCI_LOWER_IO_PA),
30 .length = IOP3XX_PCI_IO_WINDOW_SIZE,
31 .type = MT_DEVICE,
32 },
33};
34
35void __init iop3xx_map_io(void)
36{
37 iotable_init(iop3xx_std_desc, ARRAY_SIZE(iop3xx_std_desc));
38}
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
new file mode 100644
index 000000000000..06282dffbdc6
--- /dev/null
+++ b/arch/arm/plat-iop/time.c
@@ -0,0 +1,98 @@
1/*
2 * arch/arm/plat-iop/time.c
3 *
4 * Timer code for IOP32x and IOP33x based systems
5 *
6 * Author: Deepak Saxena <dsaxena@mvista.com>
7 *
8 * Copyright 2002-2003 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/kernel.h>
17#include <linux/interrupt.h>
18#include <linux/time.h>
19#include <linux/init.h>
20#include <linux/timex.h>
21#include <asm/hardware.h>
22#include <asm/io.h>
23#include <asm/irq.h>
24#include <asm/uaccess.h>
25#include <asm/mach/irq.h>
26#include <asm/mach/time.h>
27
28#ifdef CONFIG_ARCH_IOP32X
29#define IRQ_IOP3XX_TIMER0 IRQ_IOP32X_TIMER0
30#else
31#ifdef CONFIG_ARCH_IOP33X
32#define IRQ_IOP3XX_TIMER0 IRQ_IOP33X_TIMER0
33#endif
34#endif
35
36static unsigned long ticks_per_jiffy;
37static unsigned long ticks_per_usec;
38static unsigned long next_jiffy_time;
39
40unsigned long iop3xx_gettimeoffset(void)
41{
42 unsigned long offset;
43
44 offset = next_jiffy_time - *IOP3XX_TU_TCR1;
45
46 return offset / ticks_per_usec;
47}
48
49static irqreturn_t
50iop3xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
51{
52 write_seqlock(&xtime_lock);
53
54 iop3xx_cp6_enable();
55 asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1));
56 iop3xx_cp6_disable();
57
58 while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1)
59 >= ticks_per_jiffy) {
60 timer_tick(regs);
61 next_jiffy_time -= ticks_per_jiffy;
62 }
63
64 write_sequnlock(&xtime_lock);
65
66 return IRQ_HANDLED;
67}
68
69static struct irqaction iop3xx_timer_irq = {
70 .name = "IOP3XX Timer Tick",
71 .handler = iop3xx_timer_interrupt,
72 .flags = IRQF_DISABLED | IRQF_TIMER,
73};
74
75void __init iop3xx_init_time(unsigned long tick_rate)
76{
77 u32 timer_ctl;
78
79 ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
80 ticks_per_usec = tick_rate / 1000000;
81 next_jiffy_time = 0xffffffff;
82
83 timer_ctl = IOP3XX_TMR_EN | IOP3XX_TMR_PRIVILEGED |
84 IOP3XX_TMR_RELOAD | IOP3XX_TMR_RATIO_1_1;
85
86 /*
87 * We use timer 0 for our timer interrupt, and timer 1 as
88 * monotonic counter for tracking missed jiffies.
89 */
90 iop3xx_cp6_enable();
91 asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1));
92 asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl));
93 asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff));
94 asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl));
95 iop3xx_cp6_disable();
96
97 setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq);
98}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 16:43:16 -0500