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-rw-r--r--arch/arm/plat-iop/time.c66
1 files changed, 35 insertions, 31 deletions
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index f530abdaa7a1..16300adfb4de 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -24,39 +24,45 @@
24#include <asm/uaccess.h> 24#include <asm/uaccess.h>
25#include <asm/mach/irq.h> 25#include <asm/mach/irq.h>
26#include <asm/mach/time.h> 26#include <asm/mach/time.h>
27 27#include <asm/arch/time.h>
28#ifdef CONFIG_ARCH_IOP32X
29#define IRQ_IOP3XX_TIMER0 IRQ_IOP32X_TIMER0
30#else
31#ifdef CONFIG_ARCH_IOP33X
32#define IRQ_IOP3XX_TIMER0 IRQ_IOP33X_TIMER0
33#endif
34#endif
35 28
36static unsigned long ticks_per_jiffy; 29static unsigned long ticks_per_jiffy;
37static unsigned long ticks_per_usec; 30static unsigned long ticks_per_usec;
38static unsigned long next_jiffy_time; 31static unsigned long next_jiffy_time;
39 32
40unsigned long iop3xx_gettimeoffset(void) 33unsigned long iop_gettimeoffset(void)
41{ 34{
42 unsigned long offset; 35 unsigned long offset, temp1, temp2;
43 36
44 offset = next_jiffy_time - *IOP3XX_TU_TCR1; 37 /* enable cp6, if necessary, to avoid taking the overhead of an
38 * undefined instruction trap
39 */
40 asm volatile (
41 "mrc p15, 0, %0, c15, c1, 0\n\t"
42 "ands %1, %0, #(1 << 6)\n\t"
43 "orreq %0, %0, #(1 << 6)\n\t"
44 "mcreq p15, 0, %0, c15, c1, 0\n\t"
45#ifdef CONFIG_XSCALE
46 "mrceq p15, 0, %0, c15, c1, 0\n\t"
47 "moveq %0, %0\n\t"
48 "subeq pc, pc, #4\n\t"
49#endif
50 : "=r"(temp1), "=r"(temp2) : : "cc");
51
52 offset = next_jiffy_time - read_tcr1();
45 53
46 return offset / ticks_per_usec; 54 return offset / ticks_per_usec;
47} 55}
48 56
49static irqreturn_t 57static irqreturn_t
50iop3xx_timer_interrupt(int irq, void *dev_id) 58iop_timer_interrupt(int irq, void *dev_id)
51{ 59{
52 write_seqlock(&xtime_lock); 60 write_seqlock(&xtime_lock);
53 61
54 iop3xx_cp6_enable(); 62 write_tisr(1);
55 asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1));
56 iop3xx_cp6_disable();
57 63
58 while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1) 64 while ((signed long)(next_jiffy_time - read_tcr1())
59 >= ticks_per_jiffy) { 65 >= ticks_per_jiffy) {
60 timer_tick(); 66 timer_tick();
61 next_jiffy_time -= ticks_per_jiffy; 67 next_jiffy_time -= ticks_per_jiffy;
62 } 68 }
@@ -66,13 +72,13 @@ iop3xx_timer_interrupt(int irq, void *dev_id)
66 return IRQ_HANDLED; 72 return IRQ_HANDLED;
67} 73}
68 74
69static struct irqaction iop3xx_timer_irq = { 75static struct irqaction iop_timer_irq = {
70 .name = "IOP3XX Timer Tick", 76 .name = "IOP Timer Tick",
71 .handler = iop3xx_timer_interrupt, 77 .handler = iop_timer_interrupt,
72 .flags = IRQF_DISABLED | IRQF_TIMER, 78 .flags = IRQF_DISABLED | IRQF_TIMER,
73}; 79};
74 80
75void __init iop3xx_init_time(unsigned long tick_rate) 81void __init iop_init_time(unsigned long tick_rate)
76{ 82{
77 u32 timer_ctl; 83 u32 timer_ctl;
78 84
@@ -80,19 +86,17 @@ void __init iop3xx_init_time(unsigned long tick_rate)
80 ticks_per_usec = tick_rate / 1000000; 86 ticks_per_usec = tick_rate / 1000000;
81 next_jiffy_time = 0xffffffff; 87 next_jiffy_time = 0xffffffff;
82 88
83 timer_ctl = IOP3XX_TMR_EN | IOP3XX_TMR_PRIVILEGED | 89 timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
84 IOP3XX_TMR_RELOAD | IOP3XX_TMR_RATIO_1_1; 90 IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;
85 91
86 /* 92 /*
87 * We use timer 0 for our timer interrupt, and timer 1 as 93 * We use timer 0 for our timer interrupt, and timer 1 as
88 * monotonic counter for tracking missed jiffies. 94 * monotonic counter for tracking missed jiffies.
89 */ 95 */
90 iop3xx_cp6_enable(); 96 write_trr0(ticks_per_jiffy - 1);
91 asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1)); 97 write_tmr0(timer_ctl);
92 asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl)); 98 write_trr1(0xffffffff);
93 asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff)); 99 write_tmr1(timer_ctl);
94 asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl)); 100
95 iop3xx_cp6_disable(); 101 setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
96
97 setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq);
98} 102}