3 files changed, 19 insertions, 16 deletions

diff --git a/arch/arm/nwfpe/ARM-gcc.h b/arch/arm/nwfpe/ARM-gcc.h
index e6598470b076..436e54aa02ec 100644
--- a/arch/arm/nwfpe/ARM-gcc.h
+++ b/arch/arm/nwfpe/ARM-gcc.h
@@ -68,7 +68,7 @@ a compiler does not support explicit inlining, this macro should be defined
 to be `static'.
 -------------------------------------------------------------------------------
 */
-#define INLINE extern __inline__
+#define INLINE static inline
 
 
 /* For use as a GCC soft-float library we need some special function names. */
diff --git a/arch/arm/nwfpe/entry.S b/arch/arm/nwfpe/entry.S
index 1dc13bc6d810..48bca0db4607 100644
--- a/arch/arm/nwfpe/entry.S
+++ b/arch/arm/nwfpe/entry.S
@@ -70,13 +70,24 @@ floating point instructions.  GCC attempts to group floating point
 instructions to allow the emulator to spread the cost of the trap over
 several floating point instructions.  */
 
+#include <asm/asm-offsets.h>
+
         .globl  nwfpe_enter
 nwfpe_enter:
         mov     r4, lr                  @ save the failure-return addresses
         mov     sl, sp                  @ we access the registers via 'sl'
 
-        ldr     r5, [sp, #60]           @ get contents of PC;
+        ldr     r5, [sp, #S_PC]         @ get contents of PC;
+        mov     r6, r0                  @ save the opcode
 emulate:
+        ldr     r1, [sp, #S_PSR]        @ fetch the PSR
+        bl      checkCondition          @ check the condition
+        cmp     r0, #0                  @ r0 = 0 ==> condition failed
+
+        @ if condition code failed to match, next insn
+        beq     next                    @ get the next instruction;
+
+        mov     r0, r6                  @ prepare for EmulateAll()
         bl      EmulateAll              @ emulate the instruction
         cmp     r0, #0                  @ was emulation successful
         moveq   pc, r4                  @ no, return failure
@@ -91,18 +102,10 @@ next:
         teqne   r2, #0x0E000000
         movne   pc, r9                  @ return ok if not a fp insn
 
-        str     r5, [sp, #60]           @ update PC copy in regs
+        str     r5, [sp, #S_PC]         @ update PC copy in regs
 
         mov     r0, r6                  @ save a copy
-        ldr     r1, [sp, #64]           @ fetch the condition codes
-        bl      checkCondition          @ check the condition
-        cmp     r0, #0                  @ r0 = 0 ==> condition failed
-
-        @ if condition code failed to match, next insn
-        beq     next                    @ get the next instruction;
-
-        mov     r0, r6                  @ prepare for EmulateAll()
-        b       emulate                 @ if r0 != 0, goto EmulateAll
+        b       emulate                 @ check condition and emulate
 
         @ We need to be prepared for the instructions at .Lx1 and .Lx2 
         @ to fault.  Emit the appropriate exception gunk to fix things up.
diff --git a/arch/arm/nwfpe/fpa11.inl b/arch/arm/nwfpe/fpa11.inl
index 10c3caf2868f..ab8d6826245f 100644
--- a/arch/arm/nwfpe/fpa11.inl
+++ b/arch/arm/nwfpe/fpa11.inl
@@ -22,13 +22,13 @@
 #include "fpa11.h"
 
 /* Read and write floating point status register */
-extern __inline__ unsigned int readFPSR(void)
+static inline unsigned int readFPSR(void)
 {
         FPA11 *fpa11 = GET_FPA11();
         return (fpa11->fpsr);
 }
 
-extern __inline__ void writeFPSR(FPSR reg)
+static inline void writeFPSR(FPSR reg)
 {
         FPA11 *fpa11 = GET_FPA11();
         /* the sysid byte in the status register is readonly */
@@ -36,14 +36,14 @@ extern __inline__ void writeFPSR(FPSR reg)
 }
 
 /* Read and write floating point control register */
-extern __inline__ FPCR readFPCR(void)
+static inline FPCR readFPCR(void)
 {
         FPA11 *fpa11 = GET_FPA11();
         /* clear SB, AB and DA bits before returning FPCR */
         return (fpa11->fpcr & ~MASK_RFC);
 }
 
-extern __inline__ void writeFPCR(FPCR reg)
+static inline void writeFPCR(FPCR reg)
 {
         FPA11 *fpa11 = GET_FPA11();
         fpa11->fpcr &= ~MASK_WFC;               /* clear SB, AB and DA bits */