5 files changed, 236 insertions, 1 deletions

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 35955b54944c..9e8101ecd63e 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -397,6 +397,15 @@ config CPU_V7
         select CPU_PABRT_V7
         select CPU_TLB_V7 if MMU
 
+# ARMv7M
+config CPU_V7M
+        bool
+        select CPU_32v7M
+        select CPU_ABRT_NOMMU
+        select CPU_CACHE_NOP
+        select CPU_PABRT_LEGACY
+        select CPU_THUMBONLY
+
 config CPU_THUMBONLY
         bool
         # There are no CPUs available with MMU that don't implement an ARM ISA:
@@ -441,6 +450,9 @@ config CPU_32v6K
 config CPU_32v7
         bool
 
+config CPU_32v7M
+        bool
+
 # The abort model
 config CPU_ABRT_NOMMU
         bool
@@ -491,6 +503,9 @@ config CPU_CACHE_V6
 config CPU_CACHE_V7
         bool
 
+config CPU_CACHE_NOP
+        bool
+
 config CPU_CACHE_VIVT
         bool
 
@@ -613,7 +628,11 @@ config ARCH_DMA_ADDR_T_64BIT
 
 config ARM_THUMB
         bool "Support Thumb user binaries" if !CPU_THUMBONLY
-        depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
+        depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \
+                CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \
+                CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
+                CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \
+                CPU_V7 || CPU_FEROCEON || CPU_V7M
         default y
         help
           Say Y if you want to include kernel support for running user space
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 9e51be96f635..ee558a01f390 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_CPU_CACHE_V4WB)	+= cache-v4wb.o
 obj-$(CONFIG_CPU_CACHE_V6)      += cache-v6.o
 obj-$(CONFIG_CPU_CACHE_V7)      += cache-v7.o
 obj-$(CONFIG_CPU_CACHE_FA)      += cache-fa.o
+obj-$(CONFIG_CPU_CACHE_NOP)     += cache-nop.o
 
 AFLAGS_cache-v6.o       :=-Wa,-march=armv6
 AFLAGS_cache-v7.o       :=-Wa,-march=armv7-a
@@ -87,6 +88,7 @@ obj-$(CONFIG_CPU_FEROCEON)	+= proc-feroceon.o
 obj-$(CONFIG_CPU_V6)            += proc-v6.o
 obj-$(CONFIG_CPU_V6K)           += proc-v6.o
 obj-$(CONFIG_CPU_V7)            += proc-v7.o
+obj-$(CONFIG_CPU_V7M)           += proc-v7m.o
 
 AFLAGS_proc-v6.o        :=-Wa,-march=armv6
 AFLAGS_proc-v7.o        :=-Wa,-march=armv7-a
diff --git a/arch/arm/mm/cache-nop.S b/arch/arm/mm/cache-nop.S
new file mode 100644
index 000000000000..8e12ddca0031
--- /dev/null
+++ b/arch/arm/mm/cache-nop.S
@@ -0,0 +1,50 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+#include "proc-macros.S"
+
+ENTRY(nop_flush_icache_all)
+        mov     pc, lr
+ENDPROC(nop_flush_icache_all)
+
+        .globl nop_flush_kern_cache_all
+        .equ nop_flush_kern_cache_all, nop_flush_icache_all
+
+        .globl nop_flush_kern_cache_louis
+        .equ nop_flush_kern_cache_louis, nop_flush_icache_all
+
+        .globl nop_flush_user_cache_all
+        .equ nop_flush_user_cache_all, nop_flush_icache_all
+
+        .globl nop_flush_user_cache_range
+        .equ nop_flush_user_cache_range, nop_flush_icache_all
+
+        .globl nop_coherent_kern_range
+        .equ nop_coherent_kern_range, nop_flush_icache_all
+
+ENTRY(nop_coherent_user_range)
+        mov     r0, 0
+        mov     pc, lr
+ENDPROC(nop_coherent_user_range)
+
+        .globl nop_flush_kern_dcache_area
+        .equ nop_flush_kern_dcache_area, nop_flush_icache_all
+
+        .globl nop_dma_flush_range
+        .equ nop_dma_flush_range, nop_flush_icache_all
+
+        .globl nop_dma_map_area
+        .equ nop_dma_map_area, nop_flush_icache_all
+
+        .globl nop_dma_unmap_area
+        .equ nop_dma_unmap_area, nop_flush_icache_all
+
+        __INITDATA
+
+        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+        define_cache_functions nop
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index d51225f90ae2..dd3a6c670f08 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -20,12 +20,19 @@
 
 void __init arm_mm_memblock_reserve(void)
 {
+#ifndef CONFIG_CPU_V7M
         /*
          * Register the exception vector page.
          * some architectures which the DRAM is the exception vector to trap,
          * alloc_page breaks with error, although it is not NULL, but "0."
          */
         memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
+#else /* ifndef CONFIG_CPU_V7M */
+        /*
+         * There is no dedicated vector page on V7-M. So nothing needs to be
+         * reserved here.
+         */
+#endif
 }
 
 void __init sanity_check_meminfo(void)
diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
new file mode 100644
index 000000000000..0c93588fcb91
--- /dev/null
+++ b/arch/arm/mm/proc-v7m.S
@@ -0,0 +1,157 @@
+/*
+ *  linux/arch/arm/mm/proc-v7m.S
+ *
+ *  Copyright (C) 2008 ARM Ltd.
+ *  Copyright (C) 2001 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This is the "shell" of the ARMv7-M processor support.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/v7m.h>
+#include "proc-macros.S"
+
+ENTRY(cpu_v7m_proc_init)
+        mov     pc, lr
+ENDPROC(cpu_v7m_proc_init)
+
+ENTRY(cpu_v7m_proc_fin)
+        mov     pc, lr
+ENDPROC(cpu_v7m_proc_fin)
+
+/*
+ *      cpu_v7m_reset(loc)
+ *
+ *      Perform a soft reset of the system.  Put the CPU into the
+ *      same state as it would be if it had been reset, and branch
+ *      to what would be the reset vector.
+ *
+ *      - loc   - location to jump to for soft reset
+ */
+        .align  5
+ENTRY(cpu_v7m_reset)
+        mov     pc, r0
+ENDPROC(cpu_v7m_reset)
+
+/*
+ *      cpu_v7m_do_idle()
+ *
+ *      Idle the processor (eg, wait for interrupt).
+ *
+ *      IRQs are already disabled.
+ */
+ENTRY(cpu_v7m_do_idle)
+        wfi
+        mov     pc, lr
+ENDPROC(cpu_v7m_do_idle)
+
+ENTRY(cpu_v7m_dcache_clean_area)
+        mov     pc, lr
+ENDPROC(cpu_v7m_dcache_clean_area)
+
+/*
+ * There is no MMU, so here is nothing to do.
+ */
+ENTRY(cpu_v7m_switch_mm)
+        mov     pc, lr
+ENDPROC(cpu_v7m_switch_mm)
+
+.globl  cpu_v7m_suspend_size
+.equ    cpu_v7m_suspend_size, 0
+
+#ifdef CONFIG_ARM_CPU_SUSPEND
+ENTRY(cpu_v7m_do_suspend)
+        mov     pc, lr
+ENDPROC(cpu_v7m_do_suspend)
+
+ENTRY(cpu_v7m_do_resume)
+        mov     pc, lr
+ENDPROC(cpu_v7m_do_resume)
+#endif
+
+        .section ".text.init", #alloc, #execinstr
+
+/*
+ *      __v7m_setup
+ *
+ *      This should be able to cover all ARMv7-M cores.
+ */
+__v7m_setup:
+        @ Configure the vector table base address
+        ldr     r0, =BASEADDR_V7M_SCB
+        ldr     r12, =vector_table
+        str     r12, [r0, V7M_SCB_VTOR]
+
+        @ enable UsageFault, BusFault and MemManage fault.
+        ldr     r5, [r0, #V7M_SCB_SHCSR]
+        orr     r5, #(V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA)
+        str     r5, [r0, #V7M_SCB_SHCSR]
+
+        @ Lower the priority of the SVC and PendSV exceptions
+        mov     r5, #0x80000000
+        str     r5, [r0, V7M_SCB_SHPR2] @ set SVC priority
+        mov     r5, #0x00800000
+        str     r5, [r0, V7M_SCB_SHPR3] @ set PendSV priority
+
+        @ SVC to run the kernel in this mode
+        adr     r1, BSYM(1f)
+        ldr     r5, [r12, #11 * 4]      @ read the SVC vector entry
+        str     r1, [r12, #11 * 4]      @ write the temporary SVC vector entry
+        mov     r6, lr                  @ save LR
+        mov     r7, sp                  @ save SP
+        ldr     sp, =__v7m_setup_stack_top
+        cpsie   i
+        svc     #0
+1:      cpsid   i
+        str     r5, [r12, #11 * 4]      @ restore the original SVC vector entry
+        mov     lr, r6                  @ restore LR
+        mov     sp, r7                  @ restore SP
+
+        @ Special-purpose control register
+        mov     r1, #1
+        msr     control, r1             @ Thread mode has unpriviledged access
+
+        @ Configure the System Control Register to ensure 8-byte stack alignment
+        @ Note the STKALIGN bit is either RW or RAO.
+        ldr     r12, [r0, V7M_SCB_CCR]  @ system control register
+        orr     r12, #V7M_SCB_CCR_STKALIGN
+        str     r12, [r0, V7M_SCB_CCR]
+        mov     pc, lr
+ENDPROC(__v7m_setup)
+
+        define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
+
+        .section ".rodata"
+        string cpu_arch_name, "armv7m"
+        string cpu_elf_name "v7m"
+        string cpu_v7m_name "ARMv7-M"
+
+        .section ".proc.info.init", #alloc, #execinstr
+
+        /*
+         * Match any ARMv7-M processor core.
+         */
+        .type   __v7m_proc_info, #object
+__v7m_proc_info:
+        .long   0x000f0000              @ Required ID value
+        .long   0x000f0000              @ Mask for ID
+        .long   0                       @ proc_info_list.__cpu_mm_mmu_flags
+        .long   0                       @ proc_info_list.__cpu_io_mmu_flags
+        b       __v7m_setup             @ proc_info_list.__cpu_flush
+        .long   cpu_arch_name
+        .long   cpu_elf_name
+        .long   HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT
+        .long   cpu_v7m_name
+        .long   v7m_processor_functions @ proc_info_list.proc
+        .long   0                       @ proc_info_list.tlb
+        .long   0                       @ proc_info_list.user
+        .long   nop_cache_fns           @ proc_info_list.cache
+        .size   __v7m_proc_info, . - __v7m_proc_info
+
+__v7m_setup_stack:
+        .space  4 * 8                           @ 8 registers
+__v7m_setup_stack_top: