4 files changed, 70 insertions, 36 deletions

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index c2f37390308a..c465faca51b0 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -299,7 +299,7 @@ static void l2x0_unlock(u32 cache_id)
         int lockregs;
         int i;
 
-        switch (cache_id) {
+        switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
         case L2X0_CACHE_ID_PART_L310:
                 lockregs = 8;
                 break;
@@ -333,15 +333,14 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
         if (cache_id_part_number_from_dt)
                 cache_id = cache_id_part_number_from_dt;
         else
-                cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID)
-                        & L2X0_CACHE_ID_PART_MASK;
+                cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
         aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 
         aux &= aux_mask;
         aux |= aux_val;
 
         /* Determine the number of ways */
-        switch (cache_id) {
+        switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
         case L2X0_CACHE_ID_PART_L310:
                 if (aux & (1 << 16))
                         ways = 16;
@@ -725,7 +724,6 @@ static const struct l2x0_of_data pl310_data = {
                 .flush_all   = l2x0_flush_all,
                 .inv_all     = l2x0_inv_all,
                 .disable     = l2x0_disable,
-                .set_debug   = pl310_set_debug,
         },
 };
 
@@ -814,9 +812,8 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
                 data->save();
 
         of_init = true;
-        l2x0_init(l2x0_base, aux_val, aux_mask);
-
         memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
+        l2x0_init(l2x0_base, aux_val, aux_mask);
 
         return 0;
 }
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index a5a4b2bc42ba..2ac37372ef52 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -48,7 +48,7 @@ static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
 static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION);
 static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS);
 
-static DEFINE_PER_CPU(atomic64_t, active_asids);
+DEFINE_PER_CPU(atomic64_t, active_asids);
 static DEFINE_PER_CPU(u64, reserved_asids);
 static cpumask_t tlb_flush_pending;
 
@@ -215,6 +215,7 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
         if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) {
                 local_flush_bp_all();
                 local_flush_tlb_all();
+                dummy_flush_tlb_a15_erratum();
         }
 
         atomic64_set(&per_cpu(active_asids, cpu), asid);
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e95a996ab78f..78978945492a 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -598,39 +598,60 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
         } while (pte++, addr += PAGE_SIZE, addr != end);
 }
 
-static void __init alloc_init_section(pud_t *pud, unsigned long addr,
-                                      unsigned long end, phys_addr_t phys,
-                                      const struct mem_type *type)
+static void __init map_init_section(pmd_t *pmd, unsigned long addr,
+                        unsigned long end, phys_addr_t phys,
+                        const struct mem_type *type)
 {
-        pmd_t *pmd = pmd_offset(pud, addr);
-
+#ifndef CONFIG_ARM_LPAE
         /*
-         * Try a section mapping - end, addr and phys must all be aligned
-         * to a section boundary.  Note that PMDs refer to the individual
-         * L1 entries, whereas PGDs refer to a group of L1 entries making
-         * up one logical pointer to an L2 table.
+         * In classic MMU format, puds and pmds are folded in to
+         * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
+         * group of L1 entries making up one logical pointer to
+         * an L2 table (2MB), where as PMDs refer to the individual
+         * L1 entries (1MB). Hence increment to get the correct
+         * offset for odd 1MB sections.
+         * (See arch/arm/include/asm/pgtable-2level.h)
          */
-        if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) {
-                pmd_t *p = pmd;
-
-#ifndef CONFIG_ARM_LPAE
-                if (addr & SECTION_SIZE)
-                        pmd++;
+        if (addr & SECTION_SIZE)
+                pmd++;
 #endif
+        do {
+                *pmd = __pmd(phys | type->prot_sect);
+                phys += SECTION_SIZE;
+        } while (pmd++, addr += SECTION_SIZE, addr != end);
 
-                do {
-                        *pmd = __pmd(phys | type->prot_sect);
-                        phys += SECTION_SIZE;
-                } while (pmd++, addr += SECTION_SIZE, addr != end);
+        flush_pmd_entry(pmd);
+}
 
-                flush_pmd_entry(p);
-        } else {
+static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
+                                      unsigned long end, phys_addr_t phys,
+                                      const struct mem_type *type)
+{
+        pmd_t *pmd = pmd_offset(pud, addr);
+        unsigned long next;
+
+        do {
                 /*
-                 * No need to loop; pte's aren't interested in the
-                 * individual L1 entries.
+                 * With LPAE, we must loop over to map
+                 * all the pmds for the given range.
                  */
-                alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
-        }
+                next = pmd_addr_end(addr, end);
+
+                /*
+                 * Try a section mapping - addr, next and phys must all be
+                 * aligned to a section boundary.
+                 */
+                if (type->prot_sect &&
+                                ((addr | next | phys) & ~SECTION_MASK) == 0) {
+                        map_init_section(pmd, addr, next, phys, type);
+                } else {
+                        alloc_init_pte(pmd, addr, next,
+                                                __phys_to_pfn(phys), type);
+                }
+
+                phys += next - addr;
+
+        } while (pmd++, addr = next, addr != end);
 }
 
 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
@@ -641,7 +662,7 @@ static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
 
         do {
                 next = pud_addr_end(addr, end);
-                alloc_init_section(pud, addr, next, phys, type);
+                alloc_init_pmd(pud, addr, next, phys, type);
                 phys += next - addr;
         } while (pud++, addr = next, addr != end);
 }
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 3a3c015f8d5c..f584d3f5b37c 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -420,7 +420,7 @@ __v7_pj4b_proc_info:
 __v7_ca7mp_proc_info:
         .long   0x410fc070
         .long   0xff0ffff0
-        __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
+        __v7_proc __v7_ca7mp_setup
         .size   __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
 
         /*
@@ -430,10 +430,25 @@ __v7_ca7mp_proc_info:
 __v7_ca15mp_proc_info:
         .long   0x410fc0f0
         .long   0xff0ffff0
-        __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
+        __v7_proc __v7_ca15mp_setup
         .size   __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
 
         /*
+         * Qualcomm Inc. Krait processors.
+         */
+        .type   __krait_proc_info, #object
+__krait_proc_info:
+        .long   0x510f0400              @ Required ID value
+        .long   0xff0ffc00              @ Mask for ID
+        /*
+         * Some Krait processors don't indicate support for SDIV and UDIV
+         * instructions in the ARM instruction set, even though they actually
+         * do support them.
+         */
+        __v7_proc __v7_setup, hwcaps = HWCAP_IDIV
+        .size   __krait_proc_info, . - __krait_proc_info
+
+        /*
          * Match any ARMv7 processor core.
          */
         .type   __v7_proc_info, #object