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-rw-r--r--arch/arm/mm/Kconfig14
-rw-r--r--arch/arm/mm/Makefile1
-rw-r--r--arch/arm/mm/alignment.c2
-rw-r--r--arch/arm/mm/cache-feroceon-l2.c1
-rw-r--r--arch/arm/mm/cache-v3.S137
-rw-r--r--arch/arm/mm/cache-v4.S2
-rw-r--r--arch/arm/mm/dma-mapping.c15
-rw-r--r--arch/arm/mm/flush.c15
-rw-r--r--arch/arm/mm/mmu.c19
-rw-r--r--arch/arm/mm/proc-arm740.S30
-rw-r--r--arch/arm/mm/proc-arm920.S2
-rw-r--r--arch/arm/mm/proc-arm926.S2
-rw-r--r--arch/arm/mm/proc-mohawk.S2
-rw-r--r--arch/arm/mm/proc-sa1100.S2
-rw-r--r--arch/arm/mm/proc-syms.c2
-rw-r--r--arch/arm/mm/proc-v6.S4
-rw-r--r--arch/arm/mm/proc-v7-2level.S3
-rw-r--r--arch/arm/mm/proc-v7-3level.S3
-rw-r--r--arch/arm/mm/proc-v7.S7
-rw-r--r--arch/arm/mm/proc-xsc3.S2
-rw-r--r--arch/arm/mm/proc-xscale.S2
-rw-r--r--arch/arm/mm/tcm.h17
22 files changed, 100 insertions, 184 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 025d17328730..35955b54944c 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -43,7 +43,7 @@ config CPU_ARM740T
43 depends on !MMU 43 depends on !MMU
44 select CPU_32v4T 44 select CPU_32v4T
45 select CPU_ABRT_LV4T 45 select CPU_ABRT_LV4T
46 select CPU_CACHE_V3 # although the core is v4t 46 select CPU_CACHE_V4
47 select CPU_CP15_MPU 47 select CPU_CP15_MPU
48 select CPU_PABRT_LEGACY 48 select CPU_PABRT_LEGACY
49 help 49 help
@@ -397,6 +397,13 @@ config CPU_V7
397 select CPU_PABRT_V7 397 select CPU_PABRT_V7
398 select CPU_TLB_V7 if MMU 398 select CPU_TLB_V7 if MMU
399 399
400config CPU_THUMBONLY
401 bool
402 # There are no CPUs available with MMU that don't implement an ARM ISA:
403 depends on !MMU
404 help
405 Select this if your CPU doesn't support the 32 bit ARM instructions.
406
400# Figure out what processor architecture version we should be using. 407# Figure out what processor architecture version we should be using.
401# This defines the compiler instruction set which depends on the machine type. 408# This defines the compiler instruction set which depends on the machine type.
402config CPU_32v3 409config CPU_32v3
@@ -469,9 +476,6 @@ config CPU_PABRT_V7
469 bool 476 bool
470 477
471# The cache model 478# The cache model
472config CPU_CACHE_V3
473 bool
474
475config CPU_CACHE_V4 479config CPU_CACHE_V4
476 bool 480 bool
477 481
@@ -608,7 +612,7 @@ config ARCH_DMA_ADDR_T_64BIT
608 bool 612 bool
609 613
610config ARM_THUMB 614config ARM_THUMB
611 bool "Support Thumb user binaries" 615 bool "Support Thumb user binaries" if !CPU_THUMBONLY
612 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON 616 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
613 default y 617 default y
614 help 618 help
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 4e333fa2756f..9e51be96f635 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -33,7 +33,6 @@ obj-$(CONFIG_CPU_PABRT_LEGACY) += pabort-legacy.o
33obj-$(CONFIG_CPU_PABRT_V6) += pabort-v6.o 33obj-$(CONFIG_CPU_PABRT_V6) += pabort-v6.o
34obj-$(CONFIG_CPU_PABRT_V7) += pabort-v7.o 34obj-$(CONFIG_CPU_PABRT_V7) += pabort-v7.o
35 35
36obj-$(CONFIG_CPU_CACHE_V3) += cache-v3.o
37obj-$(CONFIG_CPU_CACHE_V4) += cache-v4.o 36obj-$(CONFIG_CPU_CACHE_V4) += cache-v4.o
38obj-$(CONFIG_CPU_CACHE_V4WT) += cache-v4wt.o 37obj-$(CONFIG_CPU_CACHE_V4WT) += cache-v4wt.o
39obj-$(CONFIG_CPU_CACHE_V4WB) += cache-v4wb.o 38obj-$(CONFIG_CPU_CACHE_V4WB) += cache-v4wb.o
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index db26e2e543f4..6f4585b89078 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -961,12 +961,14 @@ static int __init alignment_init(void)
961 return -ENOMEM; 961 return -ENOMEM;
962#endif 962#endif
963 963
964#ifdef CONFIG_CPU_CP15
964 if (cpu_is_v6_unaligned()) { 965 if (cpu_is_v6_unaligned()) {
965 cr_alignment &= ~CR_A; 966 cr_alignment &= ~CR_A;
966 cr_no_alignment &= ~CR_A; 967 cr_no_alignment &= ~CR_A;
967 set_cr(cr_alignment); 968 set_cr(cr_alignment);
968 ai_usermode = safe_usermode(ai_usermode, false); 969 ai_usermode = safe_usermode(ai_usermode, false);
969 } 970 }
971#endif
970 972
971 hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN, 973 hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
972 "alignment exception"); 974 "alignment exception");
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index dd3d59122cc3..48bc3c0a87ce 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -343,6 +343,7 @@ void __init feroceon_l2_init(int __l2_wt_override)
343 outer_cache.inv_range = feroceon_l2_inv_range; 343 outer_cache.inv_range = feroceon_l2_inv_range;
344 outer_cache.clean_range = feroceon_l2_clean_range; 344 outer_cache.clean_range = feroceon_l2_clean_range;
345 outer_cache.flush_range = feroceon_l2_flush_range; 345 outer_cache.flush_range = feroceon_l2_flush_range;
346 outer_cache.inv_all = l2_inv_all;
346 347
347 enable_l2(); 348 enable_l2();
348 349
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
deleted file mode 100644
index 8a3fadece8d3..000000000000
--- a/arch/arm/mm/cache-v3.S
+++ /dev/null
@@ -1,137 +0,0 @@
1/*
2 * linux/arch/arm/mm/cache-v3.S
3 *
4 * Copyright (C) 1997-2002 Russell king
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <linux/init.h>
12#include <asm/page.h>
13#include "proc-macros.S"
14
15/*
16 * flush_icache_all()
17 *
18 * Unconditionally clean and invalidate the entire icache.
19 */
20ENTRY(v3_flush_icache_all)
21 mov pc, lr
22ENDPROC(v3_flush_icache_all)
23
24/*
25 * flush_user_cache_all()
26 *
27 * Invalidate all cache entries in a particular address
28 * space.
29 *
30 * - mm - mm_struct describing address space
31 */
32ENTRY(v3_flush_user_cache_all)
33 /* FALLTHROUGH */
34/*
35 * flush_kern_cache_all()
36 *
37 * Clean and invalidate the entire cache.
38 */
39ENTRY(v3_flush_kern_cache_all)
40 /* FALLTHROUGH */
41
42/*
43 * flush_user_cache_range(start, end, flags)
44 *
45 * Invalidate a range of cache entries in the specified
46 * address space.
47 *
48 * - start - start address (may not be aligned)
49 * - end - end address (exclusive, may not be aligned)
50 * - flags - vma_area_struct flags describing address space
51 */
52ENTRY(v3_flush_user_cache_range)
53 mov ip, #0
54 mcreq p15, 0, ip, c7, c0, 0 @ flush ID cache
55 mov pc, lr
56
57/*
58 * coherent_kern_range(start, end)
59 *
60 * Ensure coherency between the Icache and the Dcache in the
61 * region described by start. If you have non-snooping
62 * Harvard caches, you need to implement this function.
63 *
64 * - start - virtual start address
65 * - end - virtual end address
66 */
67ENTRY(v3_coherent_kern_range)
68 /* FALLTHROUGH */
69
70/*
71 * coherent_user_range(start, end)
72 *
73 * Ensure coherency between the Icache and the Dcache in the
74 * region described by start. If you have non-snooping
75 * Harvard caches, you need to implement this function.
76 *
77 * - start - virtual start address
78 * - end - virtual end address
79 */
80ENTRY(v3_coherent_user_range)
81 mov r0, #0
82 mov pc, lr
83
84/*
85 * flush_kern_dcache_area(void *page, size_t size)
86 *
87 * Ensure no D cache aliasing occurs, either with itself or
88 * the I cache
89 *
90 * - addr - kernel address
91 * - size - region size
92 */
93ENTRY(v3_flush_kern_dcache_area)
94 /* FALLTHROUGH */
95
96/*
97 * dma_flush_range(start, end)
98 *
99 * Clean and invalidate the specified virtual address range.
100 *
101 * - start - virtual start address
102 * - end - virtual end address
103 */
104ENTRY(v3_dma_flush_range)
105 mov r0, #0
106 mcr p15, 0, r0, c7, c0, 0 @ flush ID cache
107 mov pc, lr
108
109/*
110 * dma_unmap_area(start, size, dir)
111 * - start - kernel virtual start address
112 * - size - size of region
113 * - dir - DMA direction
114 */
115ENTRY(v3_dma_unmap_area)
116 teq r2, #DMA_TO_DEVICE
117 bne v3_dma_flush_range
118 /* FALLTHROUGH */
119
120/*
121 * dma_map_area(start, size, dir)
122 * - start - kernel virtual start address
123 * - size - size of region
124 * - dir - DMA direction
125 */
126ENTRY(v3_dma_map_area)
127 mov pc, lr
128ENDPROC(v3_dma_unmap_area)
129ENDPROC(v3_dma_map_area)
130
131 .globl v3_flush_kern_cache_louis
132 .equ v3_flush_kern_cache_louis, v3_flush_kern_cache_all
133
134 __INITDATA
135
136 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
137 define_cache_functions v3
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index 43e5d77be677..a7ba68f59f0c 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -58,7 +58,7 @@ ENTRY(v4_flush_kern_cache_all)
58ENTRY(v4_flush_user_cache_range) 58ENTRY(v4_flush_user_cache_range)
59#ifdef CONFIG_CPU_CP15 59#ifdef CONFIG_CPU_CP15
60 mov ip, #0 60 mov ip, #0
61 mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache 61 mcr p15, 0, ip, c7, c7, 0 @ flush ID cache
62 mov pc, lr 62 mov pc, lr
63#else 63#else
64 /* FALLTHROUGH */ 64 /* FALLTHROUGH */
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index e9db6b4bf65a..ef3e0f3aac96 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -823,16 +823,17 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset,
823 if (PageHighMem(page)) { 823 if (PageHighMem(page)) {
824 if (len + offset > PAGE_SIZE) 824 if (len + offset > PAGE_SIZE)
825 len = PAGE_SIZE - offset; 825 len = PAGE_SIZE - offset;
826 vaddr = kmap_high_get(page); 826
827 if (vaddr) { 827 if (cache_is_vipt_nonaliasing()) {
828 vaddr += offset;
829 op(vaddr, len, dir);
830 kunmap_high(page);
831 } else if (cache_is_vipt()) {
832 /* unmapped pages might still be cached */
833 vaddr = kmap_atomic(page); 828 vaddr = kmap_atomic(page);
834 op(vaddr + offset, len, dir); 829 op(vaddr + offset, len, dir);
835 kunmap_atomic(vaddr); 830 kunmap_atomic(vaddr);
831 } else {
832 vaddr = kmap_high_get(page);
833 if (vaddr) {
834 op(vaddr + offset, len, dir);
835 kunmap_high(page);
836 }
836 } 837 }
837 } else { 838 } else {
838 vaddr = page_address(page) + offset; 839 vaddr = page_address(page) + offset;
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 1c8f7f564175..0d473cce501c 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -170,15 +170,18 @@ void __flush_dcache_page(struct address_space *mapping, struct page *page)
170 if (!PageHighMem(page)) { 170 if (!PageHighMem(page)) {
171 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); 171 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
172 } else { 172 } else {
173 void *addr = kmap_high_get(page); 173 void *addr;
174 if (addr) { 174
175 __cpuc_flush_dcache_area(addr, PAGE_SIZE); 175 if (cache_is_vipt_nonaliasing()) {
176 kunmap_high(page);
177 } else if (cache_is_vipt()) {
178 /* unmapped pages might still be cached */
179 addr = kmap_atomic(page); 176 addr = kmap_atomic(page);
180 __cpuc_flush_dcache_area(addr, PAGE_SIZE); 177 __cpuc_flush_dcache_area(addr, PAGE_SIZE);
181 kunmap_atomic(addr); 178 kunmap_atomic(addr);
179 } else {
180 addr = kmap_high_get(page);
181 if (addr) {
182 __cpuc_flush_dcache_area(addr, PAGE_SIZE);
183 kunmap_high(page);
184 }
182 } 185 }
183 } 186 }
184 187
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 78978945492a..e0d8565671a6 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -34,6 +34,7 @@
34#include <asm/mach/pci.h> 34#include <asm/mach/pci.h>
35 35
36#include "mm.h" 36#include "mm.h"
37#include "tcm.h"
37 38
38/* 39/*
39 * empty_zero_page is a special page that is used for 40 * empty_zero_page is a special page that is used for
@@ -112,6 +113,7 @@ static struct cachepolicy cache_policies[] __initdata = {
112 } 113 }
113}; 114};
114 115
116#ifdef CONFIG_CPU_CP15
115/* 117/*
116 * These are useful for identifying cache coherency 118 * These are useful for identifying cache coherency
117 * problems by allowing the cache or the cache and 119 * problems by allowing the cache or the cache and
@@ -210,6 +212,22 @@ void adjust_cr(unsigned long mask, unsigned long set)
210} 212}
211#endif 213#endif
212 214
215#else /* ifdef CONFIG_CPU_CP15 */
216
217static int __init early_cachepolicy(char *p)
218{
219 pr_warning("cachepolicy kernel parameter not supported without cp15\n");
220}
221early_param("cachepolicy", early_cachepolicy);
222
223static int __init noalign_setup(char *__unused)
224{
225 pr_warning("noalign kernel parameter not supported without cp15\n");
226}
227__setup("noalign", noalign_setup);
228
229#endif /* ifdef CONFIG_CPU_CP15 / else */
230
213#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN 231#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
214#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE 232#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
215 233
@@ -1277,6 +1295,7 @@ void __init paging_init(struct machine_desc *mdesc)
1277 dma_contiguous_remap(); 1295 dma_contiguous_remap();
1278 devicemaps_init(mdesc); 1296 devicemaps_init(mdesc);
1279 kmap_init(); 1297 kmap_init();
1298 tcm_init();
1280 1299
1281 top_pmd = pmd_off_k(0xffff0000); 1300 top_pmd = pmd_off_k(0xffff0000);
1282 1301
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index dc5de5d53f20..fde2d2a794cf 100644
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -77,24 +77,27 @@ __arm740_setup:
77 mcr p15, 0, r0, c6, c0 @ set area 0, default 77 mcr p15, 0, r0, c6, c0 @ set area 0, default
78 78
79 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM 79 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
80 ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB) 80 ldr r3, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
81 mov r2, #10 @ 11 is the minimum (4KB) 81 mov r4, #10 @ 11 is the minimum (4KB)
821: add r2, r2, #1 @ area size *= 2 821: add r4, r4, #1 @ area size *= 2
83 mov r1, r1, lsr #1 83 movs r3, r3, lsr #1
84 bne 1b @ count not zero r-shift 84 bne 1b @ count not zero r-shift
85 orr r0, r0, r2, lsl #1 @ the area register value 85 orr r0, r0, r4, lsl #1 @ the area register value
86 orr r0, r0, #1 @ set enable bit 86 orr r0, r0, #1 @ set enable bit
87 mcr p15, 0, r0, c6, c1 @ set area 1, RAM 87 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
88 88
89 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH 89 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
90 ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB) 90 ldr r3, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
91 mov r2, #10 @ 11 is the minimum (4KB) 91 cmp r3, #0
921: add r2, r2, #1 @ area size *= 2 92 moveq r0, #0
93 mov r1, r1, lsr #1 93 beq 2f
94 mov r4, #10 @ 11 is the minimum (4KB)
951: add r4, r4, #1 @ area size *= 2
96 movs r3, r3, lsr #1
94 bne 1b @ count not zero r-shift 97 bne 1b @ count not zero r-shift
95 orr r0, r0, r2, lsl #1 @ the area register value 98 orr r0, r0, r4, lsl #1 @ the area register value
96 orr r0, r0, #1 @ set enable bit 99 orr r0, r0, #1 @ set enable bit
97 mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH 1002: mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
98 101
99 mov r0, #0x06 102 mov r0, #0x06
100 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable 103 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
@@ -137,13 +140,14 @@ __arm740_proc_info:
137 .long 0x41807400 140 .long 0x41807400
138 .long 0xfffffff0 141 .long 0xfffffff0
139 .long 0 142 .long 0
143 .long 0
140 b __arm740_setup 144 b __arm740_setup
141 .long cpu_arch_name 145 .long cpu_arch_name
142 .long cpu_elf_name 146 .long cpu_elf_name
143 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT 147 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_26BIT
144 .long cpu_arm740_name 148 .long cpu_arm740_name
145 .long arm740_processor_functions 149 .long arm740_processor_functions
146 .long 0 150 .long 0
147 .long 0 151 .long 0
148 .long v3_cache_fns @ cache model 152 .long v4_cache_fns @ cache model
149 .size __arm740_proc_info, . - __arm740_proc_info 153 .size __arm740_proc_info, . - __arm740_proc_info
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 2c3b9421ab5e..2556cf1c2da1 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -387,7 +387,7 @@ ENTRY(cpu_arm920_set_pte_ext)
387/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ 387/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
388.globl cpu_arm920_suspend_size 388.globl cpu_arm920_suspend_size
389.equ cpu_arm920_suspend_size, 4 * 3 389.equ cpu_arm920_suspend_size, 4 * 3
390#ifdef CONFIG_PM_SLEEP 390#ifdef CONFIG_ARM_CPU_SUSPEND
391ENTRY(cpu_arm920_do_suspend) 391ENTRY(cpu_arm920_do_suspend)
392 stmfd sp!, {r4 - r6, lr} 392 stmfd sp!, {r4 - r6, lr}
393 mrc p15, 0, r4, c13, c0, 0 @ PID 393 mrc p15, 0, r4, c13, c0, 0 @ PID
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index f1803f7e2972..344c8a548cc0 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -402,7 +402,7 @@ ENTRY(cpu_arm926_set_pte_ext)
402/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ 402/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
403.globl cpu_arm926_suspend_size 403.globl cpu_arm926_suspend_size
404.equ cpu_arm926_suspend_size, 4 * 3 404.equ cpu_arm926_suspend_size, 4 * 3
405#ifdef CONFIG_PM_SLEEP 405#ifdef CONFIG_ARM_CPU_SUSPEND
406ENTRY(cpu_arm926_do_suspend) 406ENTRY(cpu_arm926_do_suspend)
407 stmfd sp!, {r4 - r6, lr} 407 stmfd sp!, {r4 - r6, lr}
408 mrc p15, 0, r4, c13, c0, 0 @ PID 408 mrc p15, 0, r4, c13, c0, 0 @ PID
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index 82f9cdc751d6..0b60dd3d742a 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -350,7 +350,7 @@ ENTRY(cpu_mohawk_set_pte_ext)
350 350
351.globl cpu_mohawk_suspend_size 351.globl cpu_mohawk_suspend_size
352.equ cpu_mohawk_suspend_size, 4 * 6 352.equ cpu_mohawk_suspend_size, 4 * 6
353#ifdef CONFIG_PM_SLEEP 353#ifdef CONFIG_ARM_CPU_SUSPEND
354ENTRY(cpu_mohawk_do_suspend) 354ENTRY(cpu_mohawk_do_suspend)
355 stmfd sp!, {r4 - r9, lr} 355 stmfd sp!, {r4 - r9, lr}
356 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode 356 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 3aa0da11fd84..d92dfd081429 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -172,7 +172,7 @@ ENTRY(cpu_sa1100_set_pte_ext)
172 172
173.globl cpu_sa1100_suspend_size 173.globl cpu_sa1100_suspend_size
174.equ cpu_sa1100_suspend_size, 4 * 3 174.equ cpu_sa1100_suspend_size, 4 * 3
175#ifdef CONFIG_PM_SLEEP 175#ifdef CONFIG_ARM_CPU_SUSPEND
176ENTRY(cpu_sa1100_do_suspend) 176ENTRY(cpu_sa1100_do_suspend)
177 stmfd sp!, {r4 - r6, lr} 177 stmfd sp!, {r4 - r6, lr}
178 mrc p15, 0, r4, c3, c0, 0 @ domain ID 178 mrc p15, 0, r4, c3, c0, 0 @ domain ID
diff --git a/arch/arm/mm/proc-syms.c b/arch/arm/mm/proc-syms.c
index 3e6210b4d6d4..054b491ff764 100644
--- a/arch/arm/mm/proc-syms.c
+++ b/arch/arm/mm/proc-syms.c
@@ -17,7 +17,9 @@
17 17
18#ifndef MULTI_CPU 18#ifndef MULTI_CPU
19EXPORT_SYMBOL(cpu_dcache_clean_area); 19EXPORT_SYMBOL(cpu_dcache_clean_area);
20#ifdef CONFIG_MMU
20EXPORT_SYMBOL(cpu_set_pte_ext); 21EXPORT_SYMBOL(cpu_set_pte_ext);
22#endif
21#else 23#else
22EXPORT_SYMBOL(processor); 24EXPORT_SYMBOL(processor);
23#endif 25#endif
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index bcaaa8de9325..919405e20b80 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -80,12 +80,10 @@ ENTRY(cpu_v6_do_idle)
80 mov pc, lr 80 mov pc, lr
81 81
82ENTRY(cpu_v6_dcache_clean_area) 82ENTRY(cpu_v6_dcache_clean_area)
83#ifndef TLB_CAN_READ_FROM_L1_CACHE
841: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 831: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
85 add r0, r0, #D_CACHE_LINE_SIZE 84 add r0, r0, #D_CACHE_LINE_SIZE
86 subs r1, r1, #D_CACHE_LINE_SIZE 85 subs r1, r1, #D_CACHE_LINE_SIZE
87 bhi 1b 86 bhi 1b
88#endif
89 mov pc, lr 87 mov pc, lr
90 88
91/* 89/*
@@ -138,7 +136,7 @@ ENTRY(cpu_v6_set_pte_ext)
138/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */ 136/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
139.globl cpu_v6_suspend_size 137.globl cpu_v6_suspend_size
140.equ cpu_v6_suspend_size, 4 * 6 138.equ cpu_v6_suspend_size, 4 * 6
141#ifdef CONFIG_PM_SLEEP 139#ifdef CONFIG_ARM_CPU_SUSPEND
142ENTRY(cpu_v6_do_suspend) 140ENTRY(cpu_v6_do_suspend)
143 stmfd sp!, {r4 - r9, lr} 141 stmfd sp!, {r4 - r9, lr}
144 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 142 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index 78f520bc0e99..9704097c450e 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -110,7 +110,8 @@ ENTRY(cpu_v7_set_pte_ext)
110 ARM( str r3, [r0, #2048]! ) 110 ARM( str r3, [r0, #2048]! )
111 THUMB( add r0, r0, #2048 ) 111 THUMB( add r0, r0, #2048 )
112 THUMB( str r3, [r0] ) 112 THUMB( str r3, [r0] )
113 mcr p15, 0, r0, c7, c10, 1 @ flush_pte 113 ALT_SMP(mov pc,lr)
114 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
114#endif 115#endif
115 mov pc, lr 116 mov pc, lr
116ENDPROC(cpu_v7_set_pte_ext) 117ENDPROC(cpu_v7_set_pte_ext)
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 6ffd78c0f9ab..363027e811d6 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -73,7 +73,8 @@ ENTRY(cpu_v7_set_pte_ext)
73 tst r3, #1 << (55 - 32) @ L_PTE_DIRTY 73 tst r3, #1 << (55 - 32) @ L_PTE_DIRTY
74 orreq r2, #L_PTE_RDONLY 74 orreq r2, #L_PTE_RDONLY
751: strd r2, r3, [r0] 751: strd r2, r3, [r0]
76 mcr p15, 0, r0, c7, c10, 1 @ flush_pte 76 ALT_SMP(mov pc, lr)
77 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
77#endif 78#endif
78 mov pc, lr 79 mov pc, lr
79ENDPROC(cpu_v7_set_pte_ext) 80ENDPROC(cpu_v7_set_pte_ext)
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index f584d3f5b37c..2c73a7301ff7 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -75,14 +75,14 @@ ENTRY(cpu_v7_do_idle)
75ENDPROC(cpu_v7_do_idle) 75ENDPROC(cpu_v7_do_idle)
76 76
77ENTRY(cpu_v7_dcache_clean_area) 77ENTRY(cpu_v7_dcache_clean_area)
78#ifndef TLB_CAN_READ_FROM_L1_CACHE 78 ALT_SMP(mov pc, lr) @ MP extensions imply L1 PTW
79 ALT_UP(W(nop))
79 dcache_line_size r2, r3 80 dcache_line_size r2, r3
801: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 811: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
81 add r0, r0, r2 82 add r0, r0, r2
82 subs r1, r1, r2 83 subs r1, r1, r2
83 bhi 1b 84 bhi 1b
84 dsb 85 dsb
85#endif
86 mov pc, lr 86 mov pc, lr
87ENDPROC(cpu_v7_dcache_clean_area) 87ENDPROC(cpu_v7_dcache_clean_area)
88 88
@@ -402,6 +402,8 @@ __v7_ca9mp_proc_info:
402 __v7_proc __v7_ca9mp_setup 402 __v7_proc __v7_ca9mp_setup
403 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info 403 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
404 404
405#endif /* CONFIG_ARM_LPAE */
406
405 /* 407 /*
406 * Marvell PJ4B processor. 408 * Marvell PJ4B processor.
407 */ 409 */
@@ -411,7 +413,6 @@ __v7_pj4b_proc_info:
411 .long 0xfffffff0 413 .long 0xfffffff0
412 __v7_proc __v7_pj4b_setup 414 __v7_proc __v7_pj4b_setup
413 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info 415 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
414#endif /* CONFIG_ARM_LPAE */
415 416
416 /* 417 /*
417 * ARM Ltd. Cortex A7 processor. 418 * ARM Ltd. Cortex A7 processor.
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index eb93d6487f35..e8efd83b6f25 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -413,7 +413,7 @@ ENTRY(cpu_xsc3_set_pte_ext)
413 413
414.globl cpu_xsc3_suspend_size 414.globl cpu_xsc3_suspend_size
415.equ cpu_xsc3_suspend_size, 4 * 6 415.equ cpu_xsc3_suspend_size, 4 * 6
416#ifdef CONFIG_PM_SLEEP 416#ifdef CONFIG_ARM_CPU_SUSPEND
417ENTRY(cpu_xsc3_do_suspend) 417ENTRY(cpu_xsc3_do_suspend)
418 stmfd sp!, {r4 - r9, lr} 418 stmfd sp!, {r4 - r9, lr}
419 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode 419 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 25510361aa18..e766f889bfd6 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -528,7 +528,7 @@ ENTRY(cpu_xscale_set_pte_ext)
528 528
529.globl cpu_xscale_suspend_size 529.globl cpu_xscale_suspend_size
530.equ cpu_xscale_suspend_size, 4 * 6 530.equ cpu_xscale_suspend_size, 4 * 6
531#ifdef CONFIG_PM_SLEEP 531#ifdef CONFIG_ARM_CPU_SUSPEND
532ENTRY(cpu_xscale_do_suspend) 532ENTRY(cpu_xscale_do_suspend)
533 stmfd sp!, {r4 - r9, lr} 533 stmfd sp!, {r4 - r9, lr}
534 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode 534 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
diff --git a/arch/arm/mm/tcm.h b/arch/arm/mm/tcm.h
new file mode 100644
index 000000000000..8015ad434a40
--- /dev/null
+++ b/arch/arm/mm/tcm.h
@@ -0,0 +1,17 @@
1/*
2 * Copyright (C) 2008-2009 ST-Ericsson AB
3 * License terms: GNU General Public License (GPL) version 2
4 * TCM memory handling for ARM systems
5 *
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
7 * Author: Rickard Andersson <rickard.andersson@stericsson.com>
8 */
9
10#ifdef CONFIG_HAVE_TCM
11void __init tcm_init(void);
12#else
13/* No TCM support, just blank inlines to be optimized out */
14inline void tcm_init(void)
15{
16}
17#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-18 16:39:33 -0500