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-rw-r--r--arch/arm/mm/Kconfig50
-rw-r--r--arch/arm/mm/init.c2
-rw-r--r--arch/arm/mm/proc-arm1020.S1
-rw-r--r--arch/arm/mm/proc-arm1020e.S1
-rw-r--r--arch/arm/mm/proc-arm1022.S1
-rw-r--r--arch/arm/mm/proc-arm1026.S1
-rw-r--r--arch/arm/mm/proc-arm6_7.S2
-rw-r--r--arch/arm/mm/proc-arm720.S1
-rw-r--r--arch/arm/mm/proc-arm740.S1
-rw-r--r--arch/arm/mm/proc-arm7tdmi.S1
-rw-r--r--arch/arm/mm/proc-arm920.S1
-rw-r--r--arch/arm/mm/proc-arm922.S1
-rw-r--r--arch/arm/mm/proc-arm925.S1
-rw-r--r--arch/arm/mm/proc-arm926.S1
-rw-r--r--arch/arm/mm/proc-arm940.S1
-rw-r--r--arch/arm/mm/proc-arm946.S1
-rw-r--r--arch/arm/mm/proc-arm9tdmi.S1
-rw-r--r--arch/arm/mm/proc-feroceon.S44
-rw-r--r--arch/arm/mm/proc-sa110.S1
-rw-r--r--arch/arm/mm/proc-sa1100.S1
-rw-r--r--arch/arm/mm/proc-v6.S15
-rw-r--r--arch/arm/mm/proc-v7.S1
-rw-r--r--arch/arm/mm/proc-xsc3.S1
-rw-r--r--arch/arm/mm/proc-xscale.S1
24 files changed, 68 insertions, 64 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 76348f060f27..a92a577c1b65 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -18,6 +18,7 @@ config CPU_ARM610
18 select CPU_CP15_MMU 18 select CPU_CP15_MMU
19 select CPU_COPY_V3 if MMU 19 select CPU_COPY_V3 if MMU
20 select CPU_TLB_V3 if MMU 20 select CPU_TLB_V3 if MMU
21 select CPU_PABRT_NOIFAR
21 help 22 help
22 The ARM610 is the successor to the ARM3 processor 23 The ARM610 is the successor to the ARM3 processor
23 and was produced by VLSI Technology Inc. 24 and was produced by VLSI Technology Inc.
@@ -31,6 +32,7 @@ config CPU_ARM7TDMI
31 depends on !MMU 32 depends on !MMU
32 select CPU_32v4T 33 select CPU_32v4T
33 select CPU_ABRT_LV4T 34 select CPU_ABRT_LV4T
35 select CPU_PABRT_NOIFAR
34 select CPU_CACHE_V4 36 select CPU_CACHE_V4
35 help 37 help
36 A 32-bit RISC microprocessor based on the ARM7 processor core 38 A 32-bit RISC microprocessor based on the ARM7 processor core
@@ -49,6 +51,7 @@ config CPU_ARM710
49 select CPU_CP15_MMU 51 select CPU_CP15_MMU
50 select CPU_COPY_V3 if MMU 52 select CPU_COPY_V3 if MMU
51 select CPU_TLB_V3 if MMU 53 select CPU_TLB_V3 if MMU
54 select CPU_PABRT_NOIFAR
52 help 55 help
53 A 32-bit RISC microprocessor based on the ARM7 processor core 56 A 32-bit RISC microprocessor based on the ARM7 processor core
54 designed by Advanced RISC Machines Ltd. The ARM710 is the 57 designed by Advanced RISC Machines Ltd. The ARM710 is the
@@ -64,6 +67,7 @@ config CPU_ARM720T
64 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X 67 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
65 select CPU_32v4T 68 select CPU_32v4T
66 select CPU_ABRT_LV4T 69 select CPU_ABRT_LV4T
70 select CPU_PABRT_NOIFAR
67 select CPU_CACHE_V4 71 select CPU_CACHE_V4
68 select CPU_CACHE_VIVT 72 select CPU_CACHE_VIVT
69 select CPU_CP15_MMU 73 select CPU_CP15_MMU
@@ -82,6 +86,7 @@ config CPU_ARM740T
82 depends on !MMU 86 depends on !MMU
83 select CPU_32v4T 87 select CPU_32v4T
84 select CPU_ABRT_LV4T 88 select CPU_ABRT_LV4T
89 select CPU_PABRT_NOIFAR
85 select CPU_CACHE_V3 # although the core is v4t 90 select CPU_CACHE_V3 # although the core is v4t
86 select CPU_CP15_MPU 91 select CPU_CP15_MPU
87 help 92 help
@@ -98,6 +103,7 @@ config CPU_ARM9TDMI
98 depends on !MMU 103 depends on !MMU
99 select CPU_32v4T 104 select CPU_32v4T
100 select CPU_ABRT_NOMMU 105 select CPU_ABRT_NOMMU
106 select CPU_PABRT_NOIFAR
101 select CPU_CACHE_V4 107 select CPU_CACHE_V4
102 help 108 help
103 A 32-bit RISC microprocessor based on the ARM9 processor core 109 A 32-bit RISC microprocessor based on the ARM9 processor core
@@ -113,6 +119,7 @@ config CPU_ARM920T
113 default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200 119 default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
114 select CPU_32v4T 120 select CPU_32v4T
115 select CPU_ABRT_EV4T 121 select CPU_ABRT_EV4T
122 select CPU_PABRT_NOIFAR
116 select CPU_CACHE_V4WT 123 select CPU_CACHE_V4WT
117 select CPU_CACHE_VIVT 124 select CPU_CACHE_VIVT
118 select CPU_CP15_MMU 125 select CPU_CP15_MMU
@@ -135,6 +142,7 @@ config CPU_ARM922T
135 default y if ARCH_LH7A40X || ARCH_KS8695 142 default y if ARCH_LH7A40X || ARCH_KS8695
136 select CPU_32v4T 143 select CPU_32v4T
137 select CPU_ABRT_EV4T 144 select CPU_ABRT_EV4T
145 select CPU_PABRT_NOIFAR
138 select CPU_CACHE_V4WT 146 select CPU_CACHE_V4WT
139 select CPU_CACHE_VIVT 147 select CPU_CACHE_VIVT
140 select CPU_CP15_MMU 148 select CPU_CP15_MMU
@@ -155,6 +163,7 @@ config CPU_ARM925T
155 default y if ARCH_OMAP15XX 163 default y if ARCH_OMAP15XX
156 select CPU_32v4T 164 select CPU_32v4T
157 select CPU_ABRT_EV4T 165 select CPU_ABRT_EV4T
166 select CPU_PABRT_NOIFAR
158 select CPU_CACHE_V4WT 167 select CPU_CACHE_V4WT
159 select CPU_CACHE_VIVT 168 select CPU_CACHE_VIVT
160 select CPU_CP15_MMU 169 select CPU_CP15_MMU
@@ -175,6 +184,7 @@ config CPU_ARM926T
175 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI 184 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
176 select CPU_32v5 185 select CPU_32v5
177 select CPU_ABRT_EV5TJ 186 select CPU_ABRT_EV5TJ
187 select CPU_PABRT_NOIFAR
178 select CPU_CACHE_VIVT 188 select CPU_CACHE_VIVT
179 select CPU_CP15_MMU 189 select CPU_CP15_MMU
180 select CPU_COPY_V4WB if MMU 190 select CPU_COPY_V4WB if MMU
@@ -193,6 +203,7 @@ config CPU_ARM940T
193 depends on !MMU 203 depends on !MMU
194 select CPU_32v4T 204 select CPU_32v4T
195 select CPU_ABRT_NOMMU 205 select CPU_ABRT_NOMMU
206 select CPU_PABRT_NOIFAR
196 select CPU_CACHE_VIVT 207 select CPU_CACHE_VIVT
197 select CPU_CP15_MPU 208 select CPU_CP15_MPU
198 help 209 help
@@ -210,6 +221,7 @@ config CPU_ARM946E
210 depends on !MMU 221 depends on !MMU
211 select CPU_32v5 222 select CPU_32v5
212 select CPU_ABRT_NOMMU 223 select CPU_ABRT_NOMMU
224 select CPU_PABRT_NOIFAR
213 select CPU_CACHE_VIVT 225 select CPU_CACHE_VIVT
214 select CPU_CP15_MPU 226 select CPU_CP15_MPU
215 help 227 help
@@ -226,6 +238,7 @@ config CPU_ARM1020
226 depends on ARCH_INTEGRATOR 238 depends on ARCH_INTEGRATOR
227 select CPU_32v5 239 select CPU_32v5
228 select CPU_ABRT_EV4T 240 select CPU_ABRT_EV4T
241 select CPU_PABRT_NOIFAR
229 select CPU_CACHE_V4WT 242 select CPU_CACHE_V4WT
230 select CPU_CACHE_VIVT 243 select CPU_CACHE_VIVT
231 select CPU_CP15_MMU 244 select CPU_CP15_MMU
@@ -244,6 +257,7 @@ config CPU_ARM1020E
244 depends on ARCH_INTEGRATOR 257 depends on ARCH_INTEGRATOR
245 select CPU_32v5 258 select CPU_32v5
246 select CPU_ABRT_EV4T 259 select CPU_ABRT_EV4T
260 select CPU_PABRT_NOIFAR
247 select CPU_CACHE_V4WT 261 select CPU_CACHE_V4WT
248 select CPU_CACHE_VIVT 262 select CPU_CACHE_VIVT
249 select CPU_CP15_MMU 263 select CPU_CP15_MMU
@@ -257,6 +271,7 @@ config CPU_ARM1022
257 depends on ARCH_INTEGRATOR 271 depends on ARCH_INTEGRATOR
258 select CPU_32v5 272 select CPU_32v5
259 select CPU_ABRT_EV4T 273 select CPU_ABRT_EV4T
274 select CPU_PABRT_NOIFAR
260 select CPU_CACHE_VIVT 275 select CPU_CACHE_VIVT
261 select CPU_CP15_MMU 276 select CPU_CP15_MMU
262 select CPU_COPY_V4WB if MMU # can probably do better 277 select CPU_COPY_V4WB if MMU # can probably do better
@@ -275,6 +290,7 @@ config CPU_ARM1026
275 depends on ARCH_INTEGRATOR 290 depends on ARCH_INTEGRATOR
276 select CPU_32v5 291 select CPU_32v5
277 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 292 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
293 select CPU_PABRT_NOIFAR
278 select CPU_CACHE_VIVT 294 select CPU_CACHE_VIVT
279 select CPU_CP15_MMU 295 select CPU_CP15_MMU
280 select CPU_COPY_V4WB if MMU # can probably do better 296 select CPU_COPY_V4WB if MMU # can probably do better
@@ -293,6 +309,7 @@ config CPU_SA110
293 select CPU_32v3 if ARCH_RPC 309 select CPU_32v3 if ARCH_RPC
294 select CPU_32v4 if !ARCH_RPC 310 select CPU_32v4 if !ARCH_RPC
295 select CPU_ABRT_EV4 311 select CPU_ABRT_EV4
312 select CPU_PABRT_NOIFAR
296 select CPU_CACHE_V4WB 313 select CPU_CACHE_V4WB
297 select CPU_CACHE_VIVT 314 select CPU_CACHE_VIVT
298 select CPU_CP15_MMU 315 select CPU_CP15_MMU
@@ -314,6 +331,7 @@ config CPU_SA1100
314 default y 331 default y
315 select CPU_32v4 332 select CPU_32v4
316 select CPU_ABRT_EV4 333 select CPU_ABRT_EV4
334 select CPU_PABRT_NOIFAR
317 select CPU_CACHE_V4WB 335 select CPU_CACHE_V4WB
318 select CPU_CACHE_VIVT 336 select CPU_CACHE_VIVT
319 select CPU_CP15_MMU 337 select CPU_CP15_MMU
@@ -326,6 +344,7 @@ config CPU_XSCALE
326 default y 344 default y
327 select CPU_32v5 345 select CPU_32v5
328 select CPU_ABRT_EV5T 346 select CPU_ABRT_EV5T
347 select CPU_PABRT_NOIFAR
329 select CPU_CACHE_VIVT 348 select CPU_CACHE_VIVT
330 select CPU_CP15_MMU 349 select CPU_CP15_MMU
331 select CPU_TLB_V4WBI if MMU 350 select CPU_TLB_V4WBI if MMU
@@ -337,6 +356,7 @@ config CPU_XSC3
337 default y 356 default y
338 select CPU_32v5 357 select CPU_32v5
339 select CPU_ABRT_EV5T 358 select CPU_ABRT_EV5T
359 select CPU_PABRT_NOIFAR
340 select CPU_CACHE_VIVT 360 select CPU_CACHE_VIVT
341 select CPU_CP15_MMU 361 select CPU_CP15_MMU
342 select CPU_TLB_V4WBI if MMU 362 select CPU_TLB_V4WBI if MMU
@@ -345,10 +365,11 @@ config CPU_XSC3
345# Feroceon 365# Feroceon
346config CPU_FEROCEON 366config CPU_FEROCEON
347 bool 367 bool
348 depends on ARCH_ORION 368 depends on ARCH_ORION5X
349 default y 369 default y
350 select CPU_32v5 370 select CPU_32v5
351 select CPU_ABRT_EV5T 371 select CPU_ABRT_EV5T
372 select CPU_PABRT_NOIFAR
352 select CPU_CACHE_VIVT 373 select CPU_CACHE_VIVT
353 select CPU_CP15_MMU 374 select CPU_CP15_MMU
354 select CPU_COPY_V4WB if MMU 375 select CPU_COPY_V4WB if MMU
@@ -366,11 +387,12 @@ config CPU_FEROCEON_OLD_ID
366# ARMv6 387# ARMv6
367config CPU_V6 388config CPU_V6
368 bool "Support ARM V6 processor" 389 bool "Support ARM V6 processor"
369 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A 390 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
370 default y if ARCH_MX3 391 default y if ARCH_MX3
371 default y if ARCH_MSM7X00A 392 default y if ARCH_MSM7X00A
372 select CPU_32v6 393 select CPU_32v6
373 select CPU_ABRT_EV6 394 select CPU_ABRT_EV6
395 select CPU_PABRT_NOIFAR
374 select CPU_CACHE_V6 396 select CPU_CACHE_V6
375 select CPU_CACHE_VIPT 397 select CPU_CACHE_VIPT
376 select CPU_CP15_MMU 398 select CPU_CP15_MMU
@@ -393,10 +415,11 @@ config CPU_32v6K
393# ARMv7 415# ARMv7
394config CPU_V7 416config CPU_V7
395 bool "Support ARM V7 processor" 417 bool "Support ARM V7 processor"
396 depends on ARCH_INTEGRATOR 418 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB
397 select CPU_32v6K 419 select CPU_32v6K
398 select CPU_32v7 420 select CPU_32v7
399 select CPU_ABRT_EV7 421 select CPU_ABRT_EV7
422 select CPU_PABRT_IFAR
400 select CPU_CACHE_V7 423 select CPU_CACHE_V7
401 select CPU_CACHE_VIPT 424 select CPU_CACHE_VIPT
402 select CPU_CP15_MMU 425 select CPU_CP15_MMU
@@ -458,6 +481,12 @@ config CPU_ABRT_EV6
458config CPU_ABRT_EV7 481config CPU_ABRT_EV7
459 bool 482 bool
460 483
484config CPU_PABRT_IFAR
485 bool
486
487config CPU_PABRT_NOIFAR
488 bool
489
461# The cache model 490# The cache model
462config CPU_CACHE_V3 491config CPU_CACHE_V3
463 bool 492 bool
@@ -572,6 +601,13 @@ config ARM_THUMB
572 601
573 If you don't know what this all is, saying Y is a safe choice. 602 If you don't know what this all is, saying Y is a safe choice.
574 603
604config ARM_THUMBEE
605 bool "Enable ThumbEE CPU extension"
606 depends on CPU_V7
607 help
608 Say Y here if you have a CPU with the ThumbEE extension and code to
609 make use of it. Say N for code that can run on CPUs without ThumbEE.
610
575config CPU_BIG_ENDIAN 611config CPU_BIG_ENDIAN
576 bool "Build big-endian kernel" 612 bool "Build big-endian kernel"
577 depends on ARCH_SUPPORTS_BIG_ENDIAN 613 depends on ARCH_SUPPORTS_BIG_ENDIAN
@@ -622,7 +658,7 @@ config CPU_DCACHE_SIZE
622 658
623config CPU_DCACHE_WRITETHROUGH 659config CPU_DCACHE_WRITETHROUGH
624 bool "Force write through D-cache" 660 bool "Force write through D-cache"
625 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FEROCEON) && !CPU_DCACHE_DISABLE 661 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
626 default y if CPU_ARM925T 662 default y if CPU_ARM925T
627 help 663 help
628 Say Y here to use the data cache in writethrough mode. Unless you 664 Say Y here to use the data cache in writethrough mode. Unless you
@@ -671,5 +707,9 @@ config OUTER_CACHE
671 default n 707 default n
672 708
673config CACHE_L2X0 709config CACHE_L2X0
674 bool 710 bool "Enable the L2x0 outer cache controller"
711 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
712 default y
675 select OUTER_CACHE 713 select OUTER_CACHE
714 help
715 This option enables the L2x0 PrimeCell.
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index ec00f26bffa4..b657f1719af0 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -48,8 +48,6 @@ void show_mem(void)
48 48
49 printk("Mem-info:\n"); 49 printk("Mem-info:\n");
50 show_free_areas(); 50 show_free_areas();
51 printk("Free swap: %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10));
52
53 for_each_online_node(node) { 51 for_each_online_node(node) {
54 pg_data_t *n = NODE_DATA(node); 52 pg_data_t *n = NODE_DATA(node);
55 struct page *map = n->node_mem_map - n->node_start_pfn; 53 struct page *map = n->node_mem_map - n->node_start_pfn;
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 700c04d6996e..5673f4d6113b 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -471,6 +471,7 @@ arm1020_crval:
471 .type arm1020_processor_functions, #object 471 .type arm1020_processor_functions, #object
472arm1020_processor_functions: 472arm1020_processor_functions:
473 .word v4t_early_abort 473 .word v4t_early_abort
474 .word pabort_noifar
474 .word cpu_arm1020_proc_init 475 .word cpu_arm1020_proc_init
475 .word cpu_arm1020_proc_fin 476 .word cpu_arm1020_proc_fin
476 .word cpu_arm1020_reset 477 .word cpu_arm1020_reset
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 1cc206ab5eae..4343fdb0e9e5 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -452,6 +452,7 @@ arm1020e_crval:
452 .type arm1020e_processor_functions, #object 452 .type arm1020e_processor_functions, #object
453arm1020e_processor_functions: 453arm1020e_processor_functions:
454 .word v4t_early_abort 454 .word v4t_early_abort
455 .word pabort_noifar
455 .word cpu_arm1020e_proc_init 456 .word cpu_arm1020e_proc_init
456 .word cpu_arm1020e_proc_fin 457 .word cpu_arm1020e_proc_fin
457 .word cpu_arm1020e_reset 458 .word cpu_arm1020e_reset
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index aff0ea08e2f8..2a4ea1659e96 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -435,6 +435,7 @@ arm1022_crval:
435 .type arm1022_processor_functions, #object 435 .type arm1022_processor_functions, #object
436arm1022_processor_functions: 436arm1022_processor_functions:
437 .word v4t_early_abort 437 .word v4t_early_abort
438 .word pabort_noifar
438 .word cpu_arm1022_proc_init 439 .word cpu_arm1022_proc_init
439 .word cpu_arm1022_proc_fin 440 .word cpu_arm1022_proc_fin
440 .word cpu_arm1022_reset 441 .word cpu_arm1022_reset
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 65e43a109085..77a1babd421c 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -430,6 +430,7 @@ arm1026_crval:
430 .type arm1026_processor_functions, #object 430 .type arm1026_processor_functions, #object
431arm1026_processor_functions: 431arm1026_processor_functions:
432 .word v5t_early_abort 432 .word v5t_early_abort
433 .word pabort_noifar
433 .word cpu_arm1026_proc_init 434 .word cpu_arm1026_proc_init
434 .word cpu_arm1026_proc_fin 435 .word cpu_arm1026_proc_fin
435 .word cpu_arm1026_reset 436 .word cpu_arm1026_reset
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 123a7dc7a433..c371fc87776e 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -293,6 +293,7 @@ __arm7_setup: mov r0, #0
293 .type arm6_processor_functions, #object 293 .type arm6_processor_functions, #object
294ENTRY(arm6_processor_functions) 294ENTRY(arm6_processor_functions)
295 .word cpu_arm6_data_abort 295 .word cpu_arm6_data_abort
296 .word pabort_noifar
296 .word cpu_arm6_proc_init 297 .word cpu_arm6_proc_init
297 .word cpu_arm6_proc_fin 298 .word cpu_arm6_proc_fin
298 .word cpu_arm6_reset 299 .word cpu_arm6_reset
@@ -309,6 +310,7 @@ ENTRY(arm6_processor_functions)
309 .type arm7_processor_functions, #object 310 .type arm7_processor_functions, #object
310ENTRY(arm7_processor_functions) 311ENTRY(arm7_processor_functions)
311 .word cpu_arm7_data_abort 312 .word cpu_arm7_data_abort
313 .word pabort_noifar
312 .word cpu_arm7_proc_init 314 .word cpu_arm7_proc_init
313 .word cpu_arm7_proc_fin 315 .word cpu_arm7_proc_fin
314 .word cpu_arm7_reset 316 .word cpu_arm7_reset
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index dc763be43362..d64f8e6f75ab 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -198,6 +198,7 @@ arm720_crval:
198 .type arm720_processor_functions, #object 198 .type arm720_processor_functions, #object
199ENTRY(arm720_processor_functions) 199ENTRY(arm720_processor_functions)
200 .word v4t_late_abort 200 .word v4t_late_abort
201 .word pabort_noifar
201 .word cpu_arm720_proc_init 202 .word cpu_arm720_proc_init
202 .word cpu_arm720_proc_fin 203 .word cpu_arm720_proc_fin
203 .word cpu_arm720_reset 204 .word cpu_arm720_reset
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 7069f495cf9b..3a57376c8bc9 100644
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -126,6 +126,7 @@ __arm740_setup:
126 .type arm740_processor_functions, #object 126 .type arm740_processor_functions, #object
127ENTRY(arm740_processor_functions) 127ENTRY(arm740_processor_functions)
128 .word v4t_late_abort 128 .word v4t_late_abort
129 .word pabort_noifar
129 .word cpu_arm740_proc_init 130 .word cpu_arm740_proc_init
130 .word cpu_arm740_proc_fin 131 .word cpu_arm740_proc_fin
131 .word cpu_arm740_reset 132 .word cpu_arm740_reset
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index d091c2571823..7b3ecdeb5370 100644
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -64,6 +64,7 @@ __arm7tdmi_setup:
64 .type arm7tdmi_processor_functions, #object 64 .type arm7tdmi_processor_functions, #object
65ENTRY(arm7tdmi_processor_functions) 65ENTRY(arm7tdmi_processor_functions)
66 .word v4t_late_abort 66 .word v4t_late_abort
67 .word pabort_noifar
67 .word cpu_arm7tdmi_proc_init 68 .word cpu_arm7tdmi_proc_init
68 .word cpu_arm7tdmi_proc_fin 69 .word cpu_arm7tdmi_proc_fin
69 .word cpu_arm7tdmi_reset 70 .word cpu_arm7tdmi_reset
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 75c945ed6c4d..28cdb060df45 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -417,6 +417,7 @@ arm920_crval:
417 .type arm920_processor_functions, #object 417 .type arm920_processor_functions, #object
418arm920_processor_functions: 418arm920_processor_functions:
419 .word v4t_early_abort 419 .word v4t_early_abort
420 .word pabort_noifar
420 .word cpu_arm920_proc_init 421 .word cpu_arm920_proc_init
421 .word cpu_arm920_proc_fin 422 .word cpu_arm920_proc_fin
422 .word cpu_arm920_reset 423 .word cpu_arm920_reset
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index ffb751b877ff..94ddcb4a4b76 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -421,6 +421,7 @@ arm922_crval:
421 .type arm922_processor_functions, #object 421 .type arm922_processor_functions, #object
422arm922_processor_functions: 422arm922_processor_functions:
423 .word v4t_early_abort 423 .word v4t_early_abort
424 .word pabort_noifar
424 .word cpu_arm922_proc_init 425 .word cpu_arm922_proc_init
425 .word cpu_arm922_proc_fin 426 .word cpu_arm922_proc_fin
426 .word cpu_arm922_reset 427 .word cpu_arm922_reset
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 44c2c997819f..065087afb772 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -484,6 +484,7 @@ arm925_crval:
484 .type arm925_processor_functions, #object 484 .type arm925_processor_functions, #object
485arm925_processor_functions: 485arm925_processor_functions:
486 .word v4t_early_abort 486 .word v4t_early_abort
487 .word pabort_noifar
487 .word cpu_arm925_proc_init 488 .word cpu_arm925_proc_init
488 .word cpu_arm925_proc_fin 489 .word cpu_arm925_proc_fin
489 .word cpu_arm925_reset 490 .word cpu_arm925_reset
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 194ef48968e6..997db8472b5c 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -437,6 +437,7 @@ arm926_crval:
437 .type arm926_processor_functions, #object 437 .type arm926_processor_functions, #object
438arm926_processor_functions: 438arm926_processor_functions:
439 .word v5tj_early_abort 439 .word v5tj_early_abort
440 .word pabort_noifar
440 .word cpu_arm926_proc_init 441 .word cpu_arm926_proc_init
441 .word cpu_arm926_proc_fin 442 .word cpu_arm926_proc_fin
442 .word cpu_arm926_reset 443 .word cpu_arm926_reset
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 786c593778f0..44ead902bd54 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -321,6 +321,7 @@ __arm940_setup:
321 .type arm940_processor_functions, #object 321 .type arm940_processor_functions, #object
322ENTRY(arm940_processor_functions) 322ENTRY(arm940_processor_functions)
323 .word nommu_early_abort 323 .word nommu_early_abort
324 .word pabort_noifar
324 .word cpu_arm940_proc_init 325 .word cpu_arm940_proc_init
325 .word cpu_arm940_proc_fin 326 .word cpu_arm940_proc_fin
326 .word cpu_arm940_reset 327 .word cpu_arm940_reset
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index a60c1421d450..2218b0c01330 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -376,6 +376,7 @@ __arm946_setup:
376 .type arm946_processor_functions, #object 376 .type arm946_processor_functions, #object
377ENTRY(arm946_processor_functions) 377ENTRY(arm946_processor_functions)
378 .word nommu_early_abort 378 .word nommu_early_abort
379 .word pabort_noifar
379 .word cpu_arm946_proc_init 380 .word cpu_arm946_proc_init
380 .word cpu_arm946_proc_fin 381 .word cpu_arm946_proc_fin
381 .word cpu_arm946_reset 382 .word cpu_arm946_reset
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index 4848eeac86b6..c85c1f50e396 100644
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -64,6 +64,7 @@ __arm9tdmi_setup:
64 .type arm9tdmi_processor_functions, #object 64 .type arm9tdmi_processor_functions, #object
65ENTRY(arm9tdmi_processor_functions) 65ENTRY(arm9tdmi_processor_functions)
66 .word nommu_early_abort 66 .word nommu_early_abort
67 .word pabort_noifar
67 .word cpu_arm9tdmi_proc_init 68 .word cpu_arm9tdmi_proc_init
68 .word cpu_arm9tdmi_proc_fin 69 .word cpu_arm9tdmi_proc_fin
69 .word cpu_arm9tdmi_reset 70 .word cpu_arm9tdmi_reset
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index fa0dc7e6f0ea..3ceb6785a345 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -118,12 +118,8 @@ ENTRY(feroceon_flush_kern_cache_all)
118 mov r2, #VM_EXEC 118 mov r2, #VM_EXEC
119 mov ip, #0 119 mov ip, #0
120__flush_whole_cache: 120__flush_whole_cache:
121#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
122 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
123#else
1241: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate 1211: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
125 bne 1b 122 bne 1b
126#endif
127 tst r2, #VM_EXEC 123 tst r2, #VM_EXEC
128 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 124 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
129 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 125 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
@@ -145,21 +141,12 @@ ENTRY(feroceon_flush_user_cache_range)
145 cmp r3, #CACHE_DLIMIT 141 cmp r3, #CACHE_DLIMIT
146 bgt __flush_whole_cache 142 bgt __flush_whole_cache
1471: tst r2, #VM_EXEC 1431: tst r2, #VM_EXEC
148#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
149 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
150 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
151 add r0, r0, #CACHE_DLINESIZE
152 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
153 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
154 add r0, r0, #CACHE_DLINESIZE
155#else
156 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 144 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
157 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
158 add r0, r0, #CACHE_DLINESIZE 146 add r0, r0, #CACHE_DLINESIZE
159 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 147 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
161 add r0, r0, #CACHE_DLINESIZE 149 add r0, r0, #CACHE_DLINESIZE
162#endif
163 cmp r0, r1 150 cmp r0, r1
164 blo 1b 151 blo 1b
165 tst r2, #VM_EXEC 152 tst r2, #VM_EXEC
@@ -232,12 +219,10 @@ ENTRY(feroceon_flush_kern_dcache_page)
232 * (same as v4wb) 219 * (same as v4wb)
233 */ 220 */
234ENTRY(feroceon_dma_inv_range) 221ENTRY(feroceon_dma_inv_range)
235#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
236 tst r0, #CACHE_DLINESIZE - 1 222 tst r0, #CACHE_DLINESIZE - 1
237 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 223 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
238 tst r1, #CACHE_DLINESIZE - 1 224 tst r1, #CACHE_DLINESIZE - 1
239 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 225 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
240#endif
241 bic r0, r0, #CACHE_DLINESIZE - 1 226 bic r0, r0, #CACHE_DLINESIZE - 1
2421: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 2271: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
243 add r0, r0, #CACHE_DLINESIZE 228 add r0, r0, #CACHE_DLINESIZE
@@ -257,13 +242,11 @@ ENTRY(feroceon_dma_inv_range)
257 * (same as v4wb) 242 * (same as v4wb)
258 */ 243 */
259ENTRY(feroceon_dma_clean_range) 244ENTRY(feroceon_dma_clean_range)
260#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
261 bic r0, r0, #CACHE_DLINESIZE - 1 245 bic r0, r0, #CACHE_DLINESIZE - 1
2621: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2461: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
263 add r0, r0, #CACHE_DLINESIZE 247 add r0, r0, #CACHE_DLINESIZE
264 cmp r0, r1 248 cmp r0, r1
265 blo 1b 249 blo 1b
266#endif
267 mcr p15, 0, r0, c7, c10, 4 @ drain WB 250 mcr p15, 0, r0, c7, c10, 4 @ drain WB
268 mov pc, lr 251 mov pc, lr
269 252
@@ -278,11 +261,7 @@ ENTRY(feroceon_dma_clean_range)
278ENTRY(feroceon_dma_flush_range) 261ENTRY(feroceon_dma_flush_range)
279 bic r0, r0, #CACHE_DLINESIZE - 1 262 bic r0, r0, #CACHE_DLINESIZE - 1
2801: 2631:
281#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
282 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 264 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
283#else
284 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
285#endif
286 add r0, r0, #CACHE_DLINESIZE 265 add r0, r0, #CACHE_DLINESIZE
287 cmp r0, r1 266 cmp r0, r1
288 blo 1b 267 blo 1b
@@ -301,12 +280,10 @@ ENTRY(feroceon_cache_fns)
301 .long feroceon_dma_flush_range 280 .long feroceon_dma_flush_range
302 281
303ENTRY(cpu_feroceon_dcache_clean_area) 282ENTRY(cpu_feroceon_dcache_clean_area)
304#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
3051: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2831: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
306 add r0, r0, #CACHE_DLINESIZE 284 add r0, r0, #CACHE_DLINESIZE
307 subs r1, r1, #CACHE_DLINESIZE 285 subs r1, r1, #CACHE_DLINESIZE
308 bhi 1b 286 bhi 1b
309#endif
310 mcr p15, 0, r0, c7, c10, 4 @ drain WB 287 mcr p15, 0, r0, c7, c10, 4 @ drain WB
311 mov pc, lr 288 mov pc, lr
312 289
@@ -323,13 +300,9 @@ ENTRY(cpu_feroceon_dcache_clean_area)
323ENTRY(cpu_feroceon_switch_mm) 300ENTRY(cpu_feroceon_switch_mm)
324#ifdef CONFIG_MMU 301#ifdef CONFIG_MMU
325 mov ip, #0 302 mov ip, #0
326#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
327 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
328#else
329@ && 'Clean & Invalidate whole DCache' 303@ && 'Clean & Invalidate whole DCache'
3301: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate 3041: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
331 bne 1b 305 bne 1b
332#endif
333 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 306 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
334 mcr p15, 0, ip, c7, c10, 4 @ drain WB 307 mcr p15, 0, ip, c7, c10, 4 @ drain WB
335 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 308 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
@@ -362,16 +335,9 @@ ENTRY(cpu_feroceon_set_pte_ext)
362 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? 335 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
363 movne r2, #0 336 movne r2, #0
364 337
365#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
366 eor r3, r2, #0x0a @ C & small page?
367 tst r3, #0x0b
368 biceq r2, r2, #4
369#endif
370 str r2, [r0] @ hardware version 338 str r2, [r0] @ hardware version
371 mov r0, r0 339 mov r0, r0
372#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
373 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 340 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
374#endif
375 mcr p15, 0, r0, c7, c10, 4 @ drain WB 341 mcr p15, 0, r0, c7, c10, 4 @ drain WB
376#endif 342#endif
377 mov pc, lr 343 mov pc, lr
@@ -387,20 +353,11 @@ __feroceon_setup:
387 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 353 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
388#endif 354#endif
389 355
390
391#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
392 mov r0, #4 @ disable write-back on caches explicitly
393 mcr p15, 7, r0, c15, c0, 0
394#endif
395
396 adr r5, feroceon_crval 356 adr r5, feroceon_crval
397 ldmia r5, {r5, r6} 357 ldmia r5, {r5, r6}
398 mrc p15, 0, r0, c1, c0 @ get control register v4 358 mrc p15, 0, r0, c1, c0 @ get control register v4
399 bic r0, r0, r5 359 bic r0, r0, r5
400 orr r0, r0, r6 360 orr r0, r0, r6
401#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
402 orr r0, r0, #0x4000 @ .1.. .... .... ....
403#endif
404 mov pc, lr 361 mov pc, lr
405 .size __feroceon_setup, . - __feroceon_setup 362 .size __feroceon_setup, . - __feroceon_setup
406 363
@@ -423,6 +380,7 @@ feroceon_crval:
423 .type feroceon_processor_functions, #object 380 .type feroceon_processor_functions, #object
424feroceon_processor_functions: 381feroceon_processor_functions:
425 .word v5t_early_abort 382 .word v5t_early_abort
383 .word pabort_noifar
426 .word cpu_feroceon_proc_init 384 .word cpu_feroceon_proc_init
427 .word cpu_feroceon_proc_fin 385 .word cpu_feroceon_proc_fin
428 .word cpu_feroceon_reset 386 .word cpu_feroceon_reset
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 6e226e12989f..9818195dbf11 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -216,6 +216,7 @@ sa110_crval:
216 .type sa110_processor_functions, #object 216 .type sa110_processor_functions, #object
217ENTRY(sa110_processor_functions) 217ENTRY(sa110_processor_functions)
218 .word v4_early_abort 218 .word v4_early_abort
219 .word pabort_noifar
219 .word cpu_sa110_proc_init 220 .word cpu_sa110_proc_init
220 .word cpu_sa110_proc_fin 221 .word cpu_sa110_proc_fin
221 .word cpu_sa110_reset 222 .word cpu_sa110_reset
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 9afb11d089fe..c5fe27ad2892 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -231,6 +231,7 @@ sa1100_crval:
231 .type sa1100_processor_functions, #object 231 .type sa1100_processor_functions, #object
232ENTRY(sa1100_processor_functions) 232ENTRY(sa1100_processor_functions)
233 .word v4_early_abort 233 .word v4_early_abort
234 .word pabort_noifar
234 .word cpu_sa1100_proc_init 235 .word cpu_sa1100_proc_init
235 .word cpu_sa1100_proc_fin 236 .word cpu_sa1100_proc_fin
236 .word cpu_sa1100_reset 237 .word cpu_sa1100_reset
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index eb42e5b94863..5702ec58b2a2 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -17,10 +17,6 @@
17#include <asm/pgtable-hwdef.h> 17#include <asm/pgtable-hwdef.h>
18#include <asm/pgtable.h> 18#include <asm/pgtable.h>
19 19
20#ifdef CONFIG_SMP
21#include <asm/hardware/arm_scu.h>
22#endif
23
24#include "proc-macros.S" 20#include "proc-macros.S"
25 21
26#define D_CACHE_LINE_SIZE 32 22#define D_CACHE_LINE_SIZE 32
@@ -187,20 +183,10 @@ cpu_v6_name:
187 */ 183 */
188__v6_setup: 184__v6_setup:
189#ifdef CONFIG_SMP 185#ifdef CONFIG_SMP
190 /* Set up the SCU on core 0 only */
191 mrc p15, 0, r0, c0, c0, 5 @ CPU core number
192 ands r0, r0, #15
193 ldreq r0, =SCU_BASE
194 ldreq r5, [r0, #SCU_CTRL]
195 orreq r5, r5, #1
196 streq r5, [r0, #SCU_CTRL]
197
198#ifndef CONFIG_CPU_DCACHE_DISABLE
199 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode 186 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
200 orr r0, r0, #0x20 187 orr r0, r0, #0x20
201 mcr p15, 0, r0, c1, c0, 1 188 mcr p15, 0, r0, c1, c0, 1
202#endif 189#endif
203#endif
204 190
205 mov r0, #0 191 mov r0, #0
206 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache 192 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
@@ -233,6 +219,7 @@ v6_crval:
233 .type v6_processor_functions, #object 219 .type v6_processor_functions, #object
234ENTRY(v6_processor_functions) 220ENTRY(v6_processor_functions)
235 .word v6_early_abort 221 .word v6_early_abort
222 .word pabort_noifar
236 .word cpu_v6_proc_init 223 .word cpu_v6_proc_init
237 .word cpu_v6_proc_fin 224 .word cpu_v6_proc_fin
238 .word cpu_v6_reset 225 .word cpu_v6_reset
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index e0acc5ae6f6f..b49f9a4c82c8 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -205,6 +205,7 @@ __v7_setup_stack:
205 .type v7_processor_functions, #object 205 .type v7_processor_functions, #object
206ENTRY(v7_processor_functions) 206ENTRY(v7_processor_functions)
207 .word v7_early_abort 207 .word v7_early_abort
208 .word pabort_ifar
208 .word cpu_v7_proc_init 209 .word cpu_v7_proc_init
209 .word cpu_v7_proc_fin 210 .word cpu_v7_proc_fin
210 .word cpu_v7_reset 211 .word cpu_v7_reset
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index d95921a2ab99..3533741a76f6 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -450,6 +450,7 @@ xsc3_crval:
450 .type xsc3_processor_functions, #object 450 .type xsc3_processor_functions, #object
451ENTRY(xsc3_processor_functions) 451ENTRY(xsc3_processor_functions)
452 .word v5t_early_abort 452 .word v5t_early_abort
453 .word pabort_noifar
453 .word cpu_xsc3_proc_init 454 .word cpu_xsc3_proc_init
454 .word cpu_xsc3_proc_fin 455 .word cpu_xsc3_proc_fin
455 .word cpu_xsc3_reset 456 .word cpu_xsc3_reset
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 016690b9d564..2dd85273976f 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -527,6 +527,7 @@ xscale_crval:
527 .type xscale_processor_functions, #object 527 .type xscale_processor_functions, #object
528ENTRY(xscale_processor_functions) 528ENTRY(xscale_processor_functions)
529 .word v5t_early_abort 529 .word v5t_early_abort
530 .word pabort_noifar
530 .word cpu_xscale_proc_init 531 .word cpu_xscale_proc_init
531 .word cpu_xscale_proc_fin 532 .word cpu_xscale_proc_fin
532 .word cpu_xscale_reset 533 .word cpu_xscale_reset
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 00:24:50 -0500