7 files changed, 28 insertions, 17 deletions

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index ae69809a9e47..7eb94e6fc376 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -798,6 +798,7 @@ config NEED_KUSER_HELPERS
 
 config KUSER_HELPERS
         bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
+        depends on MMU
         default y
         help
           Warning: disabling this option may break user programs.
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 55f9d6e0cc88..5e65ca8dea62 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -956,7 +956,7 @@ static u32 cache_id_part_number_from_dt;
  * @associativity: variable to return the calculated associativity in
  * @max_way_size: the maximum size in bytes for the cache ways
  */
-static void __init l2x0_cache_size_of_parse(const struct device_node *np,
+static int __init l2x0_cache_size_of_parse(const struct device_node *np,
                                             u32 *aux_val, u32 *aux_mask,
                                             u32 *associativity,
                                             u32 max_way_size)
@@ -974,7 +974,7 @@ static void __init l2x0_cache_size_of_parse(const struct device_node *np,
         of_property_read_u32(np, "cache-line-size", &line_size);
 
         if (!cache_size || !sets)
-                return;
+                return -ENODEV;
 
         /* All these l2 caches have the same line = block size actually */
         if (!line_size) {
@@ -1009,7 +1009,7 @@ static void __init l2x0_cache_size_of_parse(const struct device_node *np,
 
         if (way_size > max_way_size) {
                 pr_err("L2C OF: set size %dKB is too large\n", way_size);
-                return;
+                return -EINVAL;
         }
 
         pr_info("L2C OF: override cache size: %d bytes (%dKB)\n",
@@ -1027,7 +1027,7 @@ static void __init l2x0_cache_size_of_parse(const struct device_node *np,
         if (way_size_bits < 1 || way_size_bits > 6) {
                 pr_err("L2C OF: cache way size illegal: %dKB is not mapped\n",
                        way_size);
-                return;
+                return -EINVAL;
         }
 
         mask |= L2C_AUX_CTRL_WAY_SIZE_MASK;
@@ -1036,6 +1036,8 @@ static void __init l2x0_cache_size_of_parse(const struct device_node *np,
         *aux_val &= ~mask;
         *aux_val |= val;
         *aux_mask &= ~mask;
+
+        return 0;
 }
 
 static void __init l2x0_of_parse(const struct device_node *np,
@@ -1046,6 +1048,7 @@ static void __init l2x0_of_parse(const struct device_node *np,
         u32 dirty = 0;
         u32 val = 0, mask = 0;
         u32 assoc;
+        int ret;
 
         of_property_read_u32(np, "arm,tag-latency", &tag);
         if (tag) {
@@ -1068,7 +1071,10 @@ static void __init l2x0_of_parse(const struct device_node *np,
                 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
         }
 
-        l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K);
+        ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K);
+        if (ret)
+                return;
+
         if (assoc > 8) {
                 pr_err("l2x0 of: cache setting yield too high associativity\n");
                 pr_err("l2x0 of: %d calculated, max 8\n", assoc);
@@ -1125,6 +1131,7 @@ static void __init l2c310_of_parse(const struct device_node *np,
         u32 tag[3] = { 0, 0, 0 };
         u32 filter[2] = { 0, 0 };
         u32 assoc;
+        int ret;
 
         of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
         if (tag[0] && tag[1] && tag[2])
@@ -1152,7 +1159,10 @@ static void __init l2c310_of_parse(const struct device_node *np,
                                l2x0_base + L310_ADDR_FILTER_START);
         }
 
-        l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K);
+        ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K);
+        if (ret)
+                return;
+
         switch (assoc) {
         case 16:
                 *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK;
@@ -1164,8 +1174,8 @@ static void __init l2c310_of_parse(const struct device_node *np,
                 *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK;
                 break;
         default:
-                pr_err("PL310 OF: cache setting yield illegal associativity\n");
-                pr_err("PL310 OF: %d calculated, only 8 and 16 legal\n", assoc);
+                pr_err("L2C-310 OF cache associativity %d invalid, only 8 or 16 permitted\n",
+                       assoc);
                 break;
         }
 }
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index c245d903927f..e8907117861e 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1198,7 +1198,6 @@ __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
 {
         return dma_common_pages_remap(pages, size,
                         VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller);
-        return NULL;
 }
 
 /*
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index 45aeaaca9052..e17ed00828d7 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -127,8 +127,11 @@ void *kmap_atomic_pfn(unsigned long pfn)
 {
         unsigned long vaddr;
         int idx, type;
+        struct page *page = pfn_to_page(pfn);
 
         pagefault_disable();
+        if (!PageHighMem(page))
+                return page_address(page);
 
         type = kmap_atomic_idx_push();
         idx = type + KM_TYPE_NR * smp_processor_id();
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 92bba32d9230..9481f85c56e6 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -559,10 +559,10 @@ void __init mem_init(void)
 #ifdef CONFIG_MODULES
                         "    modules : 0x%08lx - 0x%08lx   (%4ld MB)\n"
 #endif
-                        "      .text : 0x%p" " - 0x%p" "   (%4d kB)\n"
-                        "      .init : 0x%p" " - 0x%p" "   (%4d kB)\n"
-                        "      .data : 0x%p" " - 0x%p" "   (%4d kB)\n"
-                        "       .bss : 0x%p" " - 0x%p" "   (%4d kB)\n",
+                        "      .text : 0x%p" " - 0x%p" "   (%4td kB)\n"
+                        "      .init : 0x%p" " - 0x%p" "   (%4td kB)\n"
+                        "      .data : 0x%p" " - 0x%p" "   (%4td kB)\n"
+                        "       .bss : 0x%p" " - 0x%p" "   (%4td kB)\n",
 
                         MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) +
                                 (PAGE_SIZE)),
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index b3a947863ac7..22ac2a6fbfe3 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -270,7 +270,6 @@ __v7_pj4b_setup:
 /* Auxiliary Debug Modes Control 1 Register */
 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
-#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
 
 /* Auxiliary Debug Modes Control 2 Register */
@@ -293,7 +292,6 @@ __v7_pj4b_setup:
         /* Auxiliary Debug Modes Control 1 Register */
         mrc     p15, 1, r0, c15, c1, 1
         orr     r0, r0, #PJ4B_CLEAN_LINE
-        orr     r0, r0, #PJ4B_BCK_OFF_STREX
         orr     r0, r0, #PJ4B_INTER_PARITY
         bic     r0, r0, #PJ4B_STATIC_BP
         mcr     p15, 1, r0, c15, c1, 1
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 23259f104c66..afa2b3c4df4a 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -535,7 +535,7 @@ ENTRY(cpu_xscale_do_suspend)
         mrc     p15, 0, r5, c15, c1, 0  @ CP access reg
         mrc     p15, 0, r6, c13, c0, 0  @ PID
         mrc     p15, 0, r7, c3, c0, 0   @ domain ID
-        mrc     p15, 0, r8, c1, c1, 0   @ auxiliary control reg
+        mrc     p15, 0, r8, c1, c0, 1   @ auxiliary control reg
         mrc     p15, 0, r9, c1, c0, 0   @ control reg
         bic     r4, r4, #2              @ clear frequency change bit
         stmia   r0, {r4 - r9}           @ store cp regs
@@ -552,7 +552,7 @@ ENTRY(cpu_xscale_do_resume)
         mcr     p15, 0, r6, c13, c0, 0  @ PID
         mcr     p15, 0, r7, c3, c0, 0   @ domain ID
         mcr     p15, 0, r1, c2, c0, 0   @ translation table base addr
-        mcr     p15, 0, r8, c1, c1, 0   @ auxiliary control reg
+        mcr     p15, 0, r8, c1, c0, 1   @ auxiliary control reg
         mov     r0, r9                  @ control register
         b       cpu_resume_mmu
 ENDPROC(cpu_xscale_do_resume)