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-rw-r--r--arch/arm/mm/Kconfig9
-rw-r--r--arch/arm/mm/Makefile1
-rw-r--r--arch/arm/mm/abort-lv4t.S7
-rw-r--r--arch/arm/mm/abort-nommu.S19
-rw-r--r--arch/arm/mm/proc-arm940.S2
-rw-r--r--arch/arm/mm/proc-arm946.S2
-rw-r--r--arch/arm/mm/proc-arm9tdmi.S2
7 files changed, 35 insertions, 7 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index ae427de27ce0..6c1bd424ea61 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -97,7 +97,7 @@ config CPU_ARM9TDMI
97 bool "Support ARM9TDMI processor" 97 bool "Support ARM9TDMI processor"
98 depends on !MMU 98 depends on !MMU
99 select CPU_32v4T 99 select CPU_32v4T
100 select CPU_ABRT_EV4T 100 select CPU_ABRT_NOMMU
101 select CPU_CACHE_V4 101 select CPU_CACHE_V4
102 help 102 help
103 A 32-bit RISC microprocessor based on the ARM9 processor core 103 A 32-bit RISC microprocessor based on the ARM9 processor core
@@ -192,7 +192,7 @@ config CPU_ARM940T
192 bool "Support ARM940T processor" if ARCH_INTEGRATOR 192 bool "Support ARM940T processor" if ARCH_INTEGRATOR
193 depends on !MMU 193 depends on !MMU
194 select CPU_32v4T 194 select CPU_32v4T
195 select CPU_ABRT_EV4T 195 select CPU_ABRT_NOMMU
196 select CPU_CACHE_VIVT 196 select CPU_CACHE_VIVT
197 select CPU_CP15_MPU 197 select CPU_CP15_MPU
198 help 198 help
@@ -209,7 +209,7 @@ config CPU_ARM946E
209 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR 209 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
210 depends on !MMU 210 depends on !MMU
211 select CPU_32v5 211 select CPU_32v5
212 select CPU_ABRT_EV5T 212 select CPU_ABRT_NOMMU
213 select CPU_CACHE_VIVT 213 select CPU_CACHE_VIVT
214 select CPU_CP15_MPU 214 select CPU_CP15_MPU
215 help 215 help
@@ -392,6 +392,9 @@ config CPU_32v6
392 bool 392 bool
393 393
394# The abort model 394# The abort model
395config CPU_ABRT_NOMMU
396 bool
397
395config CPU_ABRT_EV4 398config CPU_ABRT_EV4
396 bool 399 bool
397 400
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index ed81b9ef10cb..d2f5672ecf62 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_MODULES) += proc-syms.o
17obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o 17obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o
18obj-$(CONFIG_DISCONTIGMEM) += discontig.o 18obj-$(CONFIG_DISCONTIGMEM) += discontig.o
19 19
20obj-$(CONFIG_CPU_ABRT_NOMMU) += abort-nommu.o
20obj-$(CONFIG_CPU_ABRT_EV4) += abort-ev4.o 21obj-$(CONFIG_CPU_ABRT_EV4) += abort-ev4.o
21obj-$(CONFIG_CPU_ABRT_EV4T) += abort-ev4t.o 22obj-$(CONFIG_CPU_ABRT_EV4T) += abort-ev4t.o
22obj-$(CONFIG_CPU_ABRT_LV4T) += abort-lv4t.o 23obj-$(CONFIG_CPU_ABRT_LV4T) += abort-lv4t.o
diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S
index db743e510214..9fb7b0e25ea1 100644
--- a/arch/arm/mm/abort-lv4t.S
+++ b/arch/arm/mm/abort-lv4t.S
@@ -19,11 +19,16 @@
19 */ 19 */
20ENTRY(v4t_late_abort) 20ENTRY(v4t_late_abort)
21 tst r3, #PSR_T_BIT @ check for thumb mode 21 tst r3, #PSR_T_BIT @ check for thumb mode
22#ifdef CONFIG_CPU_CP15_MMU
22 mrc p15, 0, r1, c5, c0, 0 @ get FSR 23 mrc p15, 0, r1, c5, c0, 0 @ get FSR
23 mrc p15, 0, r0, c6, c0, 0 @ get FAR 24 mrc p15, 0, r0, c6, c0, 0 @ get FAR
25 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
26#else
27 mov r0, #0 @ clear r0, r1 (no FSR/FAR)
28 mov r1, #0
29#endif
24 bne .data_thumb_abort 30 bne .data_thumb_abort
25 ldr r8, [r2] @ read arm instruction 31 ldr r8, [r2] @ read arm instruction
26 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
27 tst r8, #1 << 20 @ L = 1 -> write? 32 tst r8, #1 << 20 @ L = 1 -> write?
28 orreq r1, r1, #1 << 11 @ yes. 33 orreq r1, r1, #1 << 11 @ yes.
29 and r7, r8, #15 << 24 34 and r7, r8, #15 << 24
diff --git a/arch/arm/mm/abort-nommu.S b/arch/arm/mm/abort-nommu.S
new file mode 100644
index 000000000000..a7cc7f9ee45d
--- /dev/null
+++ b/arch/arm/mm/abort-nommu.S
@@ -0,0 +1,19 @@
1#include <linux/linkage.h>
2#include <asm/assembler.h>
3/*
4 * Function: nommu_early_abort
5 *
6 * Params : r2 = address of aborted instruction
7 * : r3 = saved SPSR
8 *
9 * Returns : r0 = 0 (abort address)
10 * : r1 = 0 (FSR)
11 *
12 * Note: There is no FSR/FAR on !CPU_CP15_MMU cores.
13 * Just fill zero into the registers.
14 */
15 .align 5
16ENTRY(nommu_early_abort)
17 mov r0, #0 @ clear r0, r1 (no FSR/FAR)
18 mov r1, #0
19 mov pc, lr
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 14846ac2d0e6..2397f4b6e151 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -320,7 +320,7 @@ __arm940_setup:
320 */ 320 */
321 .type arm940_processor_functions, #object 321 .type arm940_processor_functions, #object
322ENTRY(arm940_processor_functions) 322ENTRY(arm940_processor_functions)
323 .word v4t_early_abort 323 .word nommu_early_abort
324 .word cpu_arm940_proc_init 324 .word cpu_arm940_proc_init
325 .word cpu_arm940_proc_fin 325 .word cpu_arm940_proc_fin
326 .word cpu_arm940_reset 326 .word cpu_arm940_reset
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 6dc7942c4cfe..e18617564421 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -375,7 +375,7 @@ __arm946_setup:
375 */ 375 */
376 .type arm946_processor_functions, #object 376 .type arm946_processor_functions, #object
377ENTRY(arm946_processor_functions) 377ENTRY(arm946_processor_functions)
378 .word v5t_early_abort 378 .word nommu_early_abort
379 .word cpu_arm946_proc_init 379 .word cpu_arm946_proc_init
380 .word cpu_arm946_proc_fin 380 .word cpu_arm946_proc_fin
381 .word cpu_arm946_reset 381 .word cpu_arm946_reset
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index 95c90f13caa8..918ebf65d4f6 100644
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -63,7 +63,7 @@ __arm9tdmi_setup:
63 */ 63 */
64 .type arm9tdmi_processor_functions, #object 64 .type arm9tdmi_processor_functions, #object
65ENTRY(arm9tdmi_processor_functions) 65ENTRY(arm9tdmi_processor_functions)
66 .word v4t_early_abort 66 .word nommu_early_abort
67 .word cpu_arm9tdmi_proc_init 67 .word cpu_arm9tdmi_proc_init
68 .word cpu_arm9tdmi_proc_fin 68 .word cpu_arm9tdmi_proc_fin
69 .word cpu_arm9tdmi_reset 69 .word cpu_arm9tdmi_reset