2 files changed, 22 insertions, 17 deletions

diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
index e33fe4229d05..3c655c54e231 100644
--- a/arch/arm/mm/mm-armv.c
+++ b/arch/arm/mm/mm-armv.c
@@ -383,6 +383,7 @@ static void __init build_mem_type_table(void)
 {
         struct cachepolicy *cp;
         unsigned int cr = get_cr();
+        unsigned int user_pgprot;
         int cpu_arch = cpu_architecture();
         int i;
 
@@ -408,6 +409,9 @@ static void __init build_mem_type_table(void)
                 }
         }
 
+        cp = &cache_policies[cachepolicy];
+        user_pgprot = cp->pte;
+
         /*
          * ARMv6 and above have extended page tables.
          */
@@ -426,11 +430,18 @@ static void __init build_mem_type_table(void)
                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 
+                /*
+                 * Mark the device area as "shared device"
+                 */
                 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
                 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
-        }
 
-        cp = &cache_policies[cachepolicy];
+                /*
+                 * User pages need to be mapped with the ASID
+                 * (iow, non-global)
+                 */
+                user_pgprot |= L_PTE_ASID;
+        }
 
         if (cpu_arch >= CPU_ARCH_ARMv5) {
                 mem_types[MT_LOW_VECTORS].prot_pte |= cp->pte & PTE_CACHEABLE;
@@ -448,7 +459,7 @@ static void __init build_mem_type_table(void)
 
         for (i = 0; i < 16; i++) {
                 unsigned long v = pgprot_val(protection_map[i]);
-                v &= (~(PTE_BUFFERABLE|PTE_CACHEABLE)) | cp->pte;
+                v &= (~(PTE_BUFFERABLE|PTE_CACHEABLE)) | user_pgprot;
                 protection_map[i] = __pgprot(v);
         }
 
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 352db98ee269..3429ddcf65d1 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -111,12 +111,6 @@ ENTRY(cpu_v6_switch_mm)
         mcr     p15, 0, r1, c13, c0, 1          @ set context ID
         mov     pc, lr
 
-#define nG      (1 << 11)
-#define APX     (1 << 9)
-#define AP1     (1 << 5)
-#define AP0     (1 << 4)
-#define XN      (1 << 0)
-
 /*
  *      cpu_v6_set_pte(ptep, pte)
  *
@@ -139,24 +133,24 @@ ENTRY(cpu_v6_switch_mm)
 ENTRY(cpu_v6_set_pte)
         str     r1, [r0], #-2048                @ linux version
 
-        bic     r2, r1, #0x00000ff0
+        bic     r2, r1, #0x000007f0
         bic     r2, r2, #0x00000003
-        orr     r2, r2, #AP0 | 2
+        orr     r2, r2, #PTE_EXT_AP0 | 2
 
         tst     r1, #L_PTE_WRITE
         tstne   r1, #L_PTE_DIRTY
-        orreq   r2, r2, #APX
+        orreq   r2, r2, #PTE_EXT_APX
 
         tst     r1, #L_PTE_USER
-        orrne   r2, r2, #AP1 | nG
-        tstne   r2, #APX
-        bicne   r2, r2, #APX | AP0
+        orrne   r2, r2, #PTE_EXT_AP1
+        tstne   r2, #PTE_EXT_APX
+        bicne   r2, r2, #PTE_EXT_APX | PTE_EXT_AP0
 
         tst     r1, #L_PTE_YOUNG
-        biceq   r2, r2, #APX | AP1 | AP0
+        biceq   r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK
 
 @       tst     r1, #L_PTE_EXEC
-@       orreq   r2, r2, #XN
+@       orreq   r2, r2, #PTE_EXT_XN
 
         tst     r1, #L_PTE_PRESENT
         moveq   r2, #0