3 files changed, 9 insertions, 5 deletions

diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index d921c1024ae0..2c6c2a7c05a0 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -96,15 +96,16 @@ ENTRY(v6_coherent_user_range)
 #ifdef HARVARD_CACHE
         bic     r0, r0, #CACHE_LINE_SIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D line
-        mcr     p15, 0, r0, c7, c5, 1           @ invalidate I line
         add     r0, r0, #CACHE_LINE_SIZE
         cmp     r0, r1
         blo     1b
 #endif
-        mcr     p15, 0, r0, c7, c5, 6           @ invalidate BTB
-#ifdef HARVARD_CACHE
         mov     r0, #0
+#ifdef HARVARD_CACHE
         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
+        mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
+#else
+        mcr     p15, 0, r0, c7, c5, 6           @ invalidate BTB
 #endif
         mov     pc, lr
 
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 330695b6b19d..b103e56806bd 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -24,14 +24,16 @@
 static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
 {
         unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
+        const int zero = 0;
 
         set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL));
         flush_tlb_kernel_page(to);
 
         asm(    "mcrr   p15, 0, %1, %0, c14\n"
-        "       mcrr    p15, 0, %1, %0, c5\n"
+        "       mcr     p15, 0, %2, c7, c10, 4\n"
+        "       mcr     p15, 0, %2, c7, c5, 0\n"
             :
-            : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES)
+            : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)
             : "cc");
 }
 
diff --git a/arch/arm/mm/tlb-v6.S b/arch/arm/mm/tlb-v6.S
index 6f76b89ef46e..fd6adde39091 100644
--- a/arch/arm/mm/tlb-v6.S
+++ b/arch/arm/mm/tlb-v6.S
@@ -80,6 +80,7 @@ ENTRY(v6wbi_flush_kern_tlb_range)
         add     r0, r0, #PAGE_SZ
         cmp     r0, r1
         blo     1b
+        mcr     p15, 0, r2, c7, c10, 4          @ data synchronization barrier
         mov     pc, lr
 
         .section ".text.init", #alloc, #execinstr