5 files changed, 74 insertions, 5 deletions

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 5f80f184cd32..b4f220dd5eb8 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -46,7 +46,7 @@ config CPU_ARM710
 config CPU_ARM720T
         bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
         default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
-        select CPU_32v4
+        select CPU_32v4T
         select CPU_ABRT_LV4T
         select CPU_CACHE_V4
         select CPU_CACHE_VIVT
@@ -64,7 +64,7 @@ config CPU_ARM920T
         bool "Support ARM920T processor"
         depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
         default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
-        select CPU_32v4
+        select CPU_32v4T
         select CPU_ABRT_EV4T
         select CPU_CACHE_V4WT
         select CPU_CACHE_VIVT
@@ -85,7 +85,7 @@ config CPU_ARM922T
         bool "Support ARM922T processor" if ARCH_INTEGRATOR
         depends on ARCH_LH7A40X || ARCH_INTEGRATOR
         default y if ARCH_LH7A40X
-        select CPU_32v4
+        select CPU_32v4T
         select CPU_ABRT_EV4T
         select CPU_CACHE_V4WT
         select CPU_CACHE_VIVT
@@ -104,7 +104,7 @@ config CPU_ARM925T
         bool "Support ARM925T processor" if ARCH_OMAP1
         depends on ARCH_OMAP15XX
         default y if ARCH_OMAP15XX
-        select CPU_32v4
+        select CPU_32v4T
         select CPU_ABRT_EV4T
         select CPU_CACHE_V4WT
         select CPU_CACHE_VIVT
@@ -285,6 +285,11 @@ config CPU_32v4
         select TLS_REG_EMUL if SMP || !MMU
         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 
+config CPU_32v4T
+        bool
+        select TLS_REG_EMUL if SMP || !MMU
+        select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
+
 config CPU_32v5
         bool
         select TLS_REG_EMUL if SMP || !MMU
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index b103e56806bd..d438ce41cdd5 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -87,6 +87,32 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
         if (cache_is_vipt_aliasing())
                 flush_pfn_alias(pfn, user_addr);
 }
+
+void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
+                         unsigned long uaddr, void *kaddr,
+                         unsigned long len, int write)
+{
+        if (cache_is_vivt()) {
+                if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
+                        unsigned long addr = (unsigned long)kaddr;
+                        __cpuc_coherent_kern_range(addr, addr + len);
+                }
+                return;
+        }
+
+        if (cache_is_vipt_aliasing()) {
+                flush_pfn_alias(page_to_pfn(page), uaddr);
+                return;
+        }
+
+        /* VIPT non-aliasing cache */
+        if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask) &&
+            vma->vm_flags | VM_EXEC) {
+                unsigned long addr = (unsigned long)kaddr;
+                /* only flushing the kernel mapping on non-aliasing VIPT */
+                __cpuc_coherent_kern_range(addr, addr + len);
+        }
+}
 #else
 #define flush_pfn_alias(pfn,vaddr)      do { } while (0)
 #endif
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index dba7dddfe57d..88a999df0ab3 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -363,7 +363,9 @@ EXPORT_SYMBOL(__ioremap);
 
 void __iounmap(void __iomem *addr)
 {
+#ifndef CONFIG_SMP
         struct vm_struct **p, *tmp;
+#endif
         unsigned int section_mapping = 0;
 
         addr = (void __iomem *)(PAGE_MASK & (unsigned long)addr);
diff --git a/arch/arm/mm/proc-syms.c b/arch/arm/mm/proc-syms.c
index 6c5f0fe578a5..ab143557e688 100644
--- a/arch/arm/mm/proc-syms.c
+++ b/arch/arm/mm/proc-syms.c
@@ -13,6 +13,7 @@
 #include <asm/cacheflush.h>
 #include <asm/proc-fns.h>
 #include <asm/tlbflush.h>
+#include <asm/page.h>
 
 #ifndef MULTI_CPU
 EXPORT_SYMBOL(cpu_dcache_clean_area);
@@ -30,6 +31,13 @@ EXPORT_SYMBOL(__cpuc_coherent_kern_range);
 EXPORT_SYMBOL(cpu_cache);
 #endif
 
+#ifndef MULTI_USER
+EXPORT_SYMBOL(__cpu_clear_user_page);
+EXPORT_SYMBOL(__cpu_copy_user_page);
+#else
+EXPORT_SYMBOL(cpu_user);
+#endif
+
 /*
  * No module should need to touch the TLB (and currently
  * no modules do.  We export this for "loadkernel" support
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 521538671f4c..561bff73a036 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -536,6 +536,11 @@ cpu_80200_name:
         .asciz  "XScale-80200"
         .size   cpu_80200_name, . - cpu_80200_name
 
+        .type   cpu_80219_name, #object
+cpu_80219_name:
+        .asciz  "XScale-80219"
+        .size   cpu_80219_name, . - cpu_80219_name
+
         .type   cpu_8032x_name, #object
 cpu_8032x_name:
         .asciz  "XScale-IOP8032x Family"
@@ -613,10 +618,33 @@ __80200_proc_info:
         .long   xscale_cache_fns
         .size   __80200_proc_info, . - __80200_proc_info
 
+        .type   __80219_proc_info,#object
+__80219_proc_info:
+        .long   0x69052e20
+        .long   0xffffffe0
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_BUFFERABLE | \
+                PMD_SECT_CACHEABLE | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        b       __xscale_setup
+        .long   cpu_arch_name
+        .long   cpu_elf_name
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+        .long   cpu_80219_name
+        .long   xscale_processor_functions
+        .long   v4wbi_tlb_fns
+        .long   xscale_mc_user_fns
+        .long   xscale_cache_fns
+        .size   __80219_proc_info, . - __80219_proc_info
+
         .type   __8032x_proc_info,#object
 __8032x_proc_info:
         .long   0x69052420
-        .long   0xfffff5e0      @ mask should accomodate IOP80219 also
+        .long   0xffffffe0
         .long   PMD_TYPE_SECT | \
                 PMD_SECT_BUFFERABLE | \
                 PMD_SECT_CACHEABLE | \