4 files changed, 25 insertions, 156 deletions

diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 65bfe84b6d67..0b6c4db44e08 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -238,9 +238,9 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
         up_read(&mm->mmap_sem);
 
         /*
-         * Handle the "normal" case first
+         * Handle the "normal" case first - VM_FAULT_MAJOR / VM_FAULT_MINOR
          */
-        if (fault > 0)
+        if (fault >= VM_FAULT_MINOR)
                 return 0;
 
         /*
@@ -261,7 +261,7 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
                 do_exit(SIGKILL);
                 return 0;
 
-        case 0:
+        case VM_FAULT_SIGBUS:
                 /*
                  * We had some memory, but were unable to
                  * successfully fix up this page fault.
diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
index e33fe4229d05..3c655c54e231 100644
--- a/arch/arm/mm/mm-armv.c
+++ b/arch/arm/mm/mm-armv.c
@@ -383,6 +383,7 @@ static void __init build_mem_type_table(void)
 {
         struct cachepolicy *cp;
         unsigned int cr = get_cr();
+        unsigned int user_pgprot;
         int cpu_arch = cpu_architecture();
         int i;
 
@@ -408,6 +409,9 @@ static void __init build_mem_type_table(void)
                 }
         }
 
+        cp = &cache_policies[cachepolicy];
+        user_pgprot = cp->pte;
+
         /*
          * ARMv6 and above have extended page tables.
          */
@@ -426,11 +430,18 @@ static void __init build_mem_type_table(void)
                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 
+                /*
+                 * Mark the device area as "shared device"
+                 */
                 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
                 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
-        }
 
-        cp = &cache_policies[cachepolicy];
+                /*
+                 * User pages need to be mapped with the ASID
+                 * (iow, non-global)
+                 */
+                user_pgprot |= L_PTE_ASID;
+        }
 
         if (cpu_arch >= CPU_ARCH_ARMv5) {
                 mem_types[MT_LOW_VECTORS].prot_pte |= cp->pte & PTE_CACHEABLE;
@@ -448,7 +459,7 @@ static void __init build_mem_type_table(void)
 
         for (i = 0; i < 16; i++) {
                 unsigned long v = pgprot_val(protection_map[i]);
-                v &= (~(PTE_BUFFERABLE|PTE_CACHEABLE)) | cp->pte;
+                v &= (~(PTE_BUFFERABLE|PTE_CACHEABLE)) | user_pgprot;
                 protection_map[i] = __pgprot(v);
         }
 
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 352db98ee269..3429ddcf65d1 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -111,12 +111,6 @@ ENTRY(cpu_v6_switch_mm)
         mcr     p15, 0, r1, c13, c0, 1          @ set context ID
         mov     pc, lr
 
-#define nG      (1 << 11)
-#define APX     (1 << 9)
-#define AP1     (1 << 5)
-#define AP0     (1 << 4)
-#define XN      (1 << 0)
-
 /*
  *      cpu_v6_set_pte(ptep, pte)
  *
@@ -139,24 +133,24 @@ ENTRY(cpu_v6_switch_mm)
 ENTRY(cpu_v6_set_pte)
         str     r1, [r0], #-2048                @ linux version
 
-        bic     r2, r1, #0x00000ff0
+        bic     r2, r1, #0x000007f0
         bic     r2, r2, #0x00000003
-        orr     r2, r2, #AP0 | 2
+        orr     r2, r2, #PTE_EXT_AP0 | 2
 
         tst     r1, #L_PTE_WRITE
         tstne   r1, #L_PTE_DIRTY
-        orreq   r2, r2, #APX
+        orreq   r2, r2, #PTE_EXT_APX
 
         tst     r1, #L_PTE_USER
-        orrne   r2, r2, #AP1 | nG
-        tstne   r2, #APX
-        bicne   r2, r2, #APX | AP0
+        orrne   r2, r2, #PTE_EXT_AP1
+        tstne   r2, #PTE_EXT_APX
+        bicne   r2, r2, #PTE_EXT_APX | PTE_EXT_AP0
 
         tst     r1, #L_PTE_YOUNG
-        biceq   r2, r2, #APX | AP1 | AP0
+        biceq   r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK
 
 @       tst     r1, #L_PTE_EXEC
-@       orreq   r2, r2, #XN
+@       orreq   r2, r2, #PTE_EXT_XN
 
         tst     r1, #L_PTE_PRESENT
         moveq   r2, #0
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 2d977b4eeeab..b88de2700146 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -370,142 +370,6 @@ ENTRY(cpu_xscale_dcache_clean_area)
         bhi     1b
         mov     pc, lr
 
-/* ================================ CACHE LOCKING============================
- *
- * The XScale MicroArchitecture implements support for locking entries into
- * the data and instruction cache.  The following functions implement the core
- * low level instructions needed to accomplish the locking.  The developer's
- * manual states that the code that performs the locking must be in non-cached
- * memory.  To accomplish this, the code in xscale-cache-lock.c copies the
- * following functions from the cache into a non-cached memory region that
- * is allocated through consistent_alloc().
- *
- */
-        .align  5
-/*
- * xscale_icache_lock
- *
- * r0: starting address to lock
- * r1: end address to lock
- */
-ENTRY(xscale_icache_lock)
-
-iLockLoop:
-        bic     r0, r0, #CACHELINESIZE - 1
-        mcr     p15, 0, r0, c9, c1, 0   @ lock into cache
-        cmp     r0, r1                  @ are we done?
-        add     r0, r0, #CACHELINESIZE  @ advance to next cache line
-        bls     iLockLoop
-        mov     pc, lr
-
-/*
- * xscale_icache_unlock
- */
-ENTRY(xscale_icache_unlock)
-        mcr     p15, 0, r0, c9, c1, 1   @ Unlock icache
-        mov     pc, lr
-
-/*
- * xscale_dcache_lock
- *
- * r0: starting address to lock
- * r1: end address to lock
- */
-ENTRY(xscale_dcache_lock)
-        mcr     p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
-        mov     r2, #1
-        mcr     p15, 0, r2, c9, c2, 0   @ Put dcache in lock mode
-        cpwait  ip                      @ Wait for completion
-
-        mrs     r2, cpsr
-        orr     r3, r2, #PSR_F_BIT | PSR_I_BIT
-dLockLoop:
-        msr     cpsr_c, r3
-        mcr     p15, 0, r0, c7, c10, 1  @ Write back line if it is dirty
-        mcr     p15, 0, r0, c7, c6, 1   @ Flush/invalidate line
-        msr     cpsr_c, r2
-        ldr     ip, [r0], #CACHELINESIZE @ Preload 32 bytes into cache from
-                                        @ location [r0]. Post-increment
-                                        @ r3 to next cache line
-        cmp     r0, r1                  @ Are we done?
-        bls     dLockLoop
-
-        mcr     p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
-        mov     r2, #0
-        mcr     p15, 0, r2, c9, c2, 0   @ Get out of lock mode
-        cpwait_ret lr, ip
-
-/*
- * xscale_dcache_unlock
- */
-ENTRY(xscale_dcache_unlock)
-        mcr     p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
-        mcr     p15, 0, ip, c9, c2, 1   @ Unlock cache
-        mov     pc, lr
-
-/*
- * Needed to determine the length of the code that needs to be copied.
- */
-        .align  5
-ENTRY(xscale_cache_dummy)
-        mov     pc, lr
-
-/* ================================ TLB LOCKING==============================
- *
- * The XScale MicroArchitecture implements support for locking entries into
- * the Instruction and Data TLBs.  The following functions provide the
- * low level support for supporting these under Linux.  xscale-lock.c
- * implements some higher level management code.  Most of the following
- * is taken straight out of the Developer's Manual.
- */
-
-/*
- * Lock I-TLB entry
- *
- * r0: Virtual address to translate and lock
- */
-        .align  5
-ENTRY(xscale_itlb_lock)
-        mrs     r2, cpsr
-        orr     r3, r2, #PSR_F_BIT | PSR_I_BIT
-        msr     cpsr_c, r3                      @ Disable interrupts
-        mcr     p15, 0, r0, c8, c5, 1           @ Invalidate I-TLB entry
-        mcr     p15, 0, r0, c10, c4, 0          @ Translate and lock
-        msr     cpsr_c, r2                      @ Restore interrupts
-        cpwait_ret lr, ip
-
-/*
- * Lock D-TLB entry
- *
- * r0: Virtual address to translate and lock
- */
-        .align  5
-ENTRY(xscale_dtlb_lock)
-        mrs     r2, cpsr
-        orr     r3, r2, #PSR_F_BIT | PSR_I_BIT
-        msr     cpsr_c, r3                      @ Disable interrupts
-        mcr     p15, 0, r0, c8, c6, 1           @ Invalidate D-TLB entry
-        mcr     p15, 0, r0, c10, c8, 0          @ Translate and lock
-        msr     cpsr_c, r2                      @ Restore interrupts
-        cpwait_ret lr, ip
-
-/*
- * Unlock all I-TLB entries
- */
-        .align  5
-ENTRY(xscale_itlb_unlock)
-        mcr     p15, 0, ip, c10, c4, 1          @ Unlock I-TLB
-        mcr     p15, 0, ip, c8, c5, 0           @ Invalidate I-TLB
-        cpwait_ret lr, ip
-
-/*
- * Unlock all D-TLB entries
- */
-ENTRY(xscale_dtlb_unlock)
-        mcr     p15, 0, ip, c10, c8, 1          @ Unlock D-TBL
-        mcr     p15, 0, ip, c8, c6, 0           @ Invalidate D-TLB
-        cpwait_ret lr, ip
-
 /* =============================== PageTable ============================== */
 
 #define PTE_CACHE_WRITE_ALLOCATE 0