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-rw-r--r--arch/arm/mm/Kconfig4
-rw-r--r--arch/arm/mm/ioremap.c227
-rw-r--r--arch/arm/mm/mm-armv.c37
-rw-r--r--arch/arm/mm/proc-arm1020.S19
-rw-r--r--arch/arm/mm/proc-arm1020e.S39
-rw-r--r--arch/arm/mm/proc-arm1022.S39
-rw-r--r--arch/arm/mm/proc-arm1026.S39
-rw-r--r--arch/arm/mm/proc-arm6_7.S16
-rw-r--r--arch/arm/mm/proc-arm720.S23
-rw-r--r--arch/arm/mm/proc-arm920.S33
-rw-r--r--arch/arm/mm/proc-arm922.S33
-rw-r--r--arch/arm/mm/proc-arm925.S39
-rw-r--r--arch/arm/mm/proc-arm926.S36
-rw-r--r--arch/arm/mm/proc-macros.S10
-rw-r--r--arch/arm/mm/proc-sa110.S19
-rw-r--r--arch/arm/mm/proc-sa1100.S21
-rw-r--r--arch/arm/mm/proc-v6.S19
-rw-r--r--arch/arm/mm/proc-xsc3.S28
-rw-r--r--arch/arm/mm/proc-xscale.S63
19 files changed, 480 insertions, 264 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c4bca753165b..5f80f184cd32 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -121,8 +121,8 @@ config CPU_ARM925T
121# ARM926T 121# ARM926T
122config CPU_ARM926T 122config CPU_ARM926T
123 bool "Support ARM926T processor" 123 bool "Support ARM926T processor"
124 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 124 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
125 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 125 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
126 select CPU_32v5 126 select CPU_32v5
127 select CPU_ABRT_EV5TJ 127 select CPU_ABRT_EV5TJ
128 select CPU_CACHE_VIVT 128 select CPU_CACHE_VIVT
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 7691cfdba567..7eac87f05180 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -27,7 +27,16 @@
27 27
28#include <asm/cacheflush.h> 28#include <asm/cacheflush.h>
29#include <asm/io.h> 29#include <asm/io.h>
30#include <asm/mmu_context.h>
31#include <asm/pgalloc.h>
30#include <asm/tlbflush.h> 32#include <asm/tlbflush.h>
33#include <asm/sizes.h>
34
35/*
36 * Used by ioremap() and iounmap() code to mark (super)section-mapped
37 * I/O regions in vm_struct->flags field.
38 */
39#define VM_ARM_SECTION_MAPPING 0x80000000
31 40
32static inline void 41static inline void
33remap_area_pte(pte_t * pte, unsigned long address, unsigned long size, 42remap_area_pte(pte_t * pte, unsigned long address, unsigned long size,
@@ -113,10 +122,168 @@ remap_area_pages(unsigned long start, unsigned long pfn,
113 dir++; 122 dir++;
114 } while (address && (address < end)); 123 } while (address && (address < end));
115 124
116 flush_cache_vmap(start, end);
117 return err; 125 return err;
118} 126}
119 127
128
129void __check_kvm_seq(struct mm_struct *mm)
130{
131 unsigned int seq;
132
133 do {
134 seq = init_mm.context.kvm_seq;
135 memcpy(pgd_offset(mm, VMALLOC_START),
136 pgd_offset_k(VMALLOC_START),
137 sizeof(pgd_t) * (pgd_index(VMALLOC_END) -
138 pgd_index(VMALLOC_START)));
139 mm->context.kvm_seq = seq;
140 } while (seq != init_mm.context.kvm_seq);
141}
142
143#ifndef CONFIG_SMP
144/*
145 * Section support is unsafe on SMP - If you iounmap and ioremap a region,
146 * the other CPUs will not see this change until their next context switch.
147 * Meanwhile, (eg) if an interrupt comes in on one of those other CPUs
148 * which requires the new ioremap'd region to be referenced, the CPU will
149 * reference the _old_ region.
150 *
151 * Note that get_vm_area() allocates a guard 4K page, so we need to mask
152 * the size back to 1MB aligned or we will overflow in the loop below.
153 */
154static void unmap_area_sections(unsigned long virt, unsigned long size)
155{
156 unsigned long addr = virt, end = virt + (size & ~SZ_1M);
157 pgd_t *pgd;
158
159 flush_cache_vunmap(addr, end);
160 pgd = pgd_offset_k(addr);
161 do {
162 pmd_t pmd, *pmdp = pmd_offset(pgd, addr);
163
164 pmd = *pmdp;
165 if (!pmd_none(pmd)) {
166 /*
167 * Clear the PMD from the page table, and
168 * increment the kvm sequence so others
169 * notice this change.
170 *
171 * Note: this is still racy on SMP machines.
172 */
173 pmd_clear(pmdp);
174 init_mm.context.kvm_seq++;
175
176 /*
177 * Free the page table, if there was one.
178 */
179 if ((pmd_val(pmd) & PMD_TYPE_MASK) == PMD_TYPE_TABLE)
180 pte_free_kernel(pmd_page_kernel(pmd));
181 }
182
183 addr += PGDIR_SIZE;
184 pgd++;
185 } while (addr < end);
186
187 /*
188 * Ensure that the active_mm is up to date - we want to
189 * catch any use-after-iounmap cases.
190 */
191 if (current->active_mm->context.kvm_seq != init_mm.context.kvm_seq)
192 __check_kvm_seq(current->active_mm);
193
194 flush_tlb_kernel_range(virt, end);
195}
196
197static int
198remap_area_sections(unsigned long virt, unsigned long pfn,
199 unsigned long size, unsigned long flags)
200{
201 unsigned long prot, addr = virt, end = virt + size;
202 pgd_t *pgd;
203
204 /*
205 * Remove and free any PTE-based mapping, and
206 * sync the current kernel mapping.
207 */
208 unmap_area_sections(virt, size);
209
210 prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO) |
211 (flags & (L_PTE_CACHEABLE | L_PTE_BUFFERABLE));
212
213 /*
214 * ARMv6 and above need XN set to prevent speculative prefetches
215 * hitting IO.
216 */
217 if (cpu_architecture() >= CPU_ARCH_ARMv6)
218 prot |= PMD_SECT_XN;
219
220 pgd = pgd_offset_k(addr);
221 do {
222 pmd_t *pmd = pmd_offset(pgd, addr);
223
224 pmd[0] = __pmd(__pfn_to_phys(pfn) | prot);
225 pfn += SZ_1M >> PAGE_SHIFT;
226 pmd[1] = __pmd(__pfn_to_phys(pfn) | prot);
227 pfn += SZ_1M >> PAGE_SHIFT;
228 flush_pmd_entry(pmd);
229
230 addr += PGDIR_SIZE;
231 pgd++;
232 } while (addr < end);
233
234 return 0;
235}
236
237static int
238remap_area_supersections(unsigned long virt, unsigned long pfn,
239 unsigned long size, unsigned long flags)
240{
241 unsigned long prot, addr = virt, end = virt + size;
242 pgd_t *pgd;
243
244 /*
245 * Remove and free any PTE-based mapping, and
246 * sync the current kernel mapping.
247 */
248 unmap_area_sections(virt, size);
249
250 prot = PMD_TYPE_SECT | PMD_SECT_SUPER | PMD_SECT_AP_WRITE |
251 PMD_DOMAIN(DOMAIN_IO) |
252 (flags & (L_PTE_CACHEABLE | L_PTE_BUFFERABLE));
253
254 /*
255 * ARMv6 and above need XN set to prevent speculative prefetches
256 * hitting IO.
257 */
258 if (cpu_architecture() >= CPU_ARCH_ARMv6)
259 prot |= PMD_SECT_XN;
260
261 pgd = pgd_offset_k(virt);
262 do {
263 unsigned long super_pmd_val, i;
264
265 super_pmd_val = __pfn_to_phys(pfn) | prot;
266 super_pmd_val |= ((pfn >> (32 - PAGE_SHIFT)) & 0xf) << 20;
267
268 for (i = 0; i < 8; i++) {
269 pmd_t *pmd = pmd_offset(pgd, addr);
270
271 pmd[0] = __pmd(super_pmd_val);
272 pmd[1] = __pmd(super_pmd_val);
273 flush_pmd_entry(pmd);
274
275 addr += PGDIR_SIZE;
276 pgd++;
277 }
278
279 pfn += SUPERSECTION_SIZE >> PAGE_SHIFT;
280 } while (addr < end);
281
282 return 0;
283}
284#endif
285
286
120/* 287/*
121 * Remap an arbitrary physical address space into the kernel virtual 288 * Remap an arbitrary physical address space into the kernel virtual
122 * address space. Needed when the kernel wants to access high addresses 289 * address space. Needed when the kernel wants to access high addresses
@@ -133,18 +300,42 @@ void __iomem *
133__ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size, 300__ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
134 unsigned long flags) 301 unsigned long flags)
135{ 302{
303 int err;
136 unsigned long addr; 304 unsigned long addr;
137 struct vm_struct * area; 305 struct vm_struct * area;
306 unsigned int cr = get_cr();
307
308 /*
309 * High mappings must be supersection aligned
310 */
311 if (pfn >= 0x100000 && (__pfn_to_phys(pfn) & ~SUPERSECTION_MASK))
312 return NULL;
138 313
139 area = get_vm_area(size, VM_IOREMAP); 314 area = get_vm_area(size, VM_IOREMAP);
140 if (!area) 315 if (!area)
141 return NULL; 316 return NULL;
142 addr = (unsigned long)area->addr; 317 addr = (unsigned long)area->addr;
143 if (remap_area_pages(addr, pfn, size, flags)) { 318
319#ifndef CONFIG_SMP
320 if ((((cpu_architecture() >= CPU_ARCH_ARMv6) && (cr & CR_XP)) ||
321 cpu_is_xsc3()) &&
322 !((__pfn_to_phys(pfn) | size | addr) & ~SUPERSECTION_MASK)) {
323 area->flags |= VM_ARM_SECTION_MAPPING;
324 err = remap_area_supersections(addr, pfn, size, flags);
325 } else if (!((__pfn_to_phys(pfn) | size | addr) & ~PMD_MASK)) {
326 area->flags |= VM_ARM_SECTION_MAPPING;
327 err = remap_area_sections(addr, pfn, size, flags);
328 } else
329#endif
330 err = remap_area_pages(addr, pfn, size, flags);
331
332 if (err) {
144 vunmap((void *)addr); 333 vunmap((void *)addr);
145 return NULL; 334 return NULL;
146 } 335 }
147 return (void __iomem *) (offset + (char *)addr); 336
337 flush_cache_vmap(addr, addr + size);
338 return (void __iomem *) (offset + addr);
148} 339}
149EXPORT_SYMBOL(__ioremap_pfn); 340EXPORT_SYMBOL(__ioremap_pfn);
150 341
@@ -173,6 +364,34 @@ EXPORT_SYMBOL(__ioremap);
173 364
174void __iounmap(void __iomem *addr) 365void __iounmap(void __iomem *addr)
175{ 366{
176 vunmap((void *)(PAGE_MASK & (unsigned long)addr)); 367 struct vm_struct **p, *tmp;
368 unsigned int section_mapping = 0;
369
370 addr = (void __iomem *)(PAGE_MASK & (unsigned long)addr);
371
372 /*
373 * If this is a section based mapping we need to handle it
374 * specially as the VM subysystem does not know how to handle
375 * such a beast. We need the lock here b/c we need to clear
376 * all the mappings before the area can be reclaimed
377 * by someone else.
378 */
379 write_lock(&vmlist_lock);
380 for (p = &vmlist ; (tmp = *p) ; p = &tmp->next) {
381 if((tmp->flags & VM_IOREMAP) && (tmp->addr == addr)) {
382 if (tmp->flags & VM_ARM_SECTION_MAPPING) {
383 *p = tmp->next;
384 unmap_area_sections((unsigned long)tmp->addr,
385 tmp->size);
386 kfree(tmp);
387 section_mapping = 1;
388 }
389 break;
390 }
391 }
392 write_unlock(&vmlist_lock);
393
394 if (!section_mapping)
395 vunmap(addr);
177} 396}
178EXPORT_SYMBOL(__iounmap); 397EXPORT_SYMBOL(__iounmap);
diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
index b0242c6ea066..38769f5862bc 100644
--- a/arch/arm/mm/mm-armv.c
+++ b/arch/arm/mm/mm-armv.c
@@ -302,16 +302,16 @@ static struct mem_types mem_types[] __initdata = {
302 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 302 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
303 L_PTE_WRITE, 303 L_PTE_WRITE,
304 .prot_l1 = PMD_TYPE_TABLE, 304 .prot_l1 = PMD_TYPE_TABLE,
305 .prot_sect = PMD_TYPE_SECT | PMD_SECT_UNCACHED | 305 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
306 PMD_SECT_AP_WRITE, 306 PMD_SECT_AP_WRITE,
307 .domain = DOMAIN_IO, 307 .domain = DOMAIN_IO,
308 }, 308 },
309 [MT_CACHECLEAN] = { 309 [MT_CACHECLEAN] = {
310 .prot_sect = PMD_TYPE_SECT, 310 .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
311 .domain = DOMAIN_KERNEL, 311 .domain = DOMAIN_KERNEL,
312 }, 312 },
313 [MT_MINICLEAN] = { 313 [MT_MINICLEAN] = {
314 .prot_sect = PMD_TYPE_SECT | PMD_SECT_MINICACHE, 314 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_MINICACHE,
315 .domain = DOMAIN_KERNEL, 315 .domain = DOMAIN_KERNEL,
316 }, 316 },
317 [MT_LOW_VECTORS] = { 317 [MT_LOW_VECTORS] = {
@@ -327,25 +327,25 @@ static struct mem_types mem_types[] __initdata = {
327 .domain = DOMAIN_USER, 327 .domain = DOMAIN_USER,
328 }, 328 },
329 [MT_MEMORY] = { 329 [MT_MEMORY] = {
330 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 330 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_AP_WRITE,
331 .domain = DOMAIN_KERNEL, 331 .domain = DOMAIN_KERNEL,
332 }, 332 },
333 [MT_ROM] = { 333 [MT_ROM] = {
334 .prot_sect = PMD_TYPE_SECT, 334 .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
335 .domain = DOMAIN_KERNEL, 335 .domain = DOMAIN_KERNEL,
336 }, 336 },
337 [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */ 337 [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */
338 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 338 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
339 L_PTE_WRITE, 339 L_PTE_WRITE,
340 .prot_l1 = PMD_TYPE_TABLE, 340 .prot_l1 = PMD_TYPE_TABLE,
341 .prot_sect = PMD_TYPE_SECT | PMD_SECT_UNCACHED | 341 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
342 PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE | 342 PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE |
343 PMD_SECT_TEX(1), 343 PMD_SECT_TEX(1),
344 .domain = DOMAIN_IO, 344 .domain = DOMAIN_IO,
345 }, 345 },
346 [MT_NONSHARED_DEVICE] = { 346 [MT_NONSHARED_DEVICE] = {
347 .prot_l1 = PMD_TYPE_TABLE, 347 .prot_l1 = PMD_TYPE_TABLE,
348 .prot_sect = PMD_TYPE_SECT | PMD_SECT_NONSHARED_DEV | 348 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_NONSHARED_DEV |
349 PMD_SECT_AP_WRITE, 349 PMD_SECT_AP_WRITE,
350 .domain = DOMAIN_IO, 350 .domain = DOMAIN_IO,
351 } 351 }
@@ -375,14 +375,21 @@ void __init build_mem_type_table(void)
375 ecc_mask = 0; 375 ecc_mask = 0;
376 } 376 }
377 377
378 if (cpu_arch <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) { 378 /*
379 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 379 * Xscale must not have PMD bit 4 set for section mappings.
380 */
381 if (cpu_is_xscale())
382 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
383 mem_types[i].prot_sect &= ~PMD_BIT4;
384
385 /*
386 * ARMv5 and lower, excluding Xscale, bit 4 must be set for
387 * page tables.
388 */
389 if (cpu_arch < CPU_ARCH_ARMv6 && !cpu_is_xscale())
390 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
380 if (mem_types[i].prot_l1) 391 if (mem_types[i].prot_l1)
381 mem_types[i].prot_l1 |= PMD_BIT4; 392 mem_types[i].prot_l1 |= PMD_BIT4;
382 if (mem_types[i].prot_sect)
383 mem_types[i].prot_sect |= PMD_BIT4;
384 }
385 }
386 393
387 cp = &cache_policies[cachepolicy]; 394 cp = &cache_policies[cachepolicy];
388 kern_pgprot = user_pgprot = cp->pte; 395 kern_pgprot = user_pgprot = cp->pte;
@@ -406,8 +413,8 @@ void __init build_mem_type_table(void)
406 * bit 4 becomes XN which we must clear for the 413 * bit 4 becomes XN which we must clear for the
407 * kernel memory mapping. 414 * kernel memory mapping.
408 */ 415 */
409 mem_types[MT_MEMORY].prot_sect &= ~PMD_BIT4; 416 mem_types[MT_MEMORY].prot_sect &= ~PMD_SECT_XN;
410 mem_types[MT_ROM].prot_sect &= ~PMD_BIT4; 417 mem_types[MT_ROM].prot_sect &= ~PMD_SECT_XN;
411 418
412 /* 419 /*
413 * Mark cache clean areas and XIP ROM read only 420 * Mark cache clean areas and XIP ROM read only
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index cc609666df05..700297ae4a55 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -439,11 +439,12 @@ __arm1020_setup:
439#ifdef CONFIG_MMU 439#ifdef CONFIG_MMU
440 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 440 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
441#endif 441#endif
442
443 adr r5, arm1020_crval
444 ldmia r5, {r5, r6}
442 mrc p15, 0, r0, c1, c0 @ get control register v4 445 mrc p15, 0, r0, c1, c0 @ get control register v4
443 ldr r5, arm1020_cr1_clear
444 bic r0, r0, r5 446 bic r0, r0, r5
445 ldr r5, arm1020_cr1_set 447 orr r0, r0, r6
446 orr r0, r0, r5
447#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 448#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
448 orr r0, r0, #0x4000 @ .R.. .... .... .... 449 orr r0, r0, #0x4000 @ .R.. .... .... ....
449#endif 450#endif
@@ -455,12 +456,9 @@ __arm1020_setup:
455 * .RVI ZFRS BLDP WCAM 456 * .RVI ZFRS BLDP WCAM
456 * .011 1001 ..11 0101 457 * .011 1001 ..11 0101
457 */ 458 */
458 .type arm1020_cr1_clear, #object 459 .type arm1020_crval, #object
459 .type arm1020_cr1_set, #object 460arm1020_crval:
460arm1020_cr1_clear: 461 crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
461 .word 0x593f
462arm1020_cr1_set:
463 .word 0x3935
464 462
465 __INITDATA 463 __INITDATA
466 464
@@ -526,6 +524,9 @@ __arm1020_proc_info:
526 .long PMD_TYPE_SECT | \ 524 .long PMD_TYPE_SECT | \
527 PMD_SECT_AP_WRITE | \ 525 PMD_SECT_AP_WRITE | \
528 PMD_SECT_AP_READ 526 PMD_SECT_AP_READ
527 .long PMD_TYPE_SECT | \
528 PMD_SECT_AP_WRITE | \
529 PMD_SECT_AP_READ
529 b __arm1020_setup 530 b __arm1020_setup
530 .long cpu_arch_name 531 .long cpu_arch_name
531 .long cpu_elf_name 532 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 117a946c28c8..0c33a5ed5a61 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -421,11 +421,11 @@ __arm1020e_setup:
421#ifdef CONFIG_MMU 421#ifdef CONFIG_MMU
422 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 422 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
423#endif 423#endif
424 adr r5, arm1020e_crval
425 ldmia r5, {r5, r6}
424 mrc p15, 0, r0, c1, c0 @ get control register v4 426 mrc p15, 0, r0, c1, c0 @ get control register v4
425 ldr r5, arm1020e_cr1_clear
426 bic r0, r0, r5 427 bic r0, r0, r5
427 ldr r5, arm1020e_cr1_set 428 orr r0, r0, r6
428 orr r0, r0, r5
429#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 429#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
430 orr r0, r0, #0x4000 @ .R.. .... .... .... 430 orr r0, r0, #0x4000 @ .R.. .... .... ....
431#endif 431#endif
@@ -437,12 +437,9 @@ __arm1020e_setup:
437 * .RVI ZFRS BLDP WCAM 437 * .RVI ZFRS BLDP WCAM
438 * .011 1001 ..11 0101 438 * .011 1001 ..11 0101
439 */ 439 */
440 .type arm1020e_cr1_clear, #object 440 .type arm1020e_crval, #object
441 .type arm1020e_cr1_set, #object 441arm1020e_crval:
442arm1020e_cr1_clear: 442 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
443 .word 0x5f3f
444arm1020e_cr1_set:
445 .word 0x3935
446 443
447 __INITDATA 444 __INITDATA
448 445
@@ -476,25 +473,7 @@ cpu_elf_name:
476 473
477 .type cpu_arm1020e_name, #object 474 .type cpu_arm1020e_name, #object
478cpu_arm1020e_name: 475cpu_arm1020e_name:
479 .ascii "ARM1020E" 476 .asciz "ARM1020E"
480#ifndef CONFIG_CPU_ICACHE_DISABLE
481 .ascii "i"
482#endif
483#ifndef CONFIG_CPU_DCACHE_DISABLE
484 .ascii "d"
485#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
486 .ascii "(wt)"
487#else
488 .ascii "(wb)"
489#endif
490#endif
491#ifndef CONFIG_CPU_BPREDICT_DISABLE
492 .ascii "B"
493#endif
494#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
495 .ascii "RR"
496#endif
497 .ascii "\0"
498 .size cpu_arm1020e_name, . - cpu_arm1020e_name 477 .size cpu_arm1020e_name, . - cpu_arm1020e_name
499 478
500 .align 479 .align
@@ -509,6 +488,10 @@ __arm1020e_proc_info:
509 PMD_BIT4 | \ 488 PMD_BIT4 | \
510 PMD_SECT_AP_WRITE | \ 489 PMD_SECT_AP_WRITE | \
511 PMD_SECT_AP_READ 490 PMD_SECT_AP_READ
491 .long PMD_TYPE_SECT | \
492 PMD_BIT4 | \
493 PMD_SECT_AP_WRITE | \
494 PMD_SECT_AP_READ
512 b __arm1020e_setup 495 b __arm1020e_setup
513 .long cpu_arch_name 496 .long cpu_arch_name
514 .long cpu_elf_name 497 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 39b7c102180a..566a55653072 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -403,11 +403,11 @@ __arm1022_setup:
403#ifdef CONFIG_MMU 403#ifdef CONFIG_MMU
404 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 404 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
405#endif 405#endif
406 adr r5, arm1022_crval
407 ldmia r5, {r5, r6}
406 mrc p15, 0, r0, c1, c0 @ get control register v4 408 mrc p15, 0, r0, c1, c0 @ get control register v4
407 ldr r5, arm1022_cr1_clear
408 bic r0, r0, r5 409 bic r0, r0, r5
409 ldr r5, arm1022_cr1_set 410 orr r0, r0, r6
410 orr r0, r0, r5
411#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 411#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
412 orr r0, r0, #0x4000 @ .R.............. 412 orr r0, r0, #0x4000 @ .R..............
413#endif 413#endif
@@ -420,12 +420,9 @@ __arm1022_setup:
420 * .011 1001 ..11 0101 420 * .011 1001 ..11 0101
421 * 421 *
422 */ 422 */
423 .type arm1022_cr1_clear, #object 423 .type arm1022_crval, #object
424 .type arm1022_cr1_set, #object 424arm1022_crval:
425arm1022_cr1_clear: 425 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
426 .word 0x7f3f
427arm1022_cr1_set:
428 .word 0x3935
429 426
430 __INITDATA 427 __INITDATA
431 428
@@ -459,25 +456,7 @@ cpu_elf_name:
459 456
460 .type cpu_arm1022_name, #object 457 .type cpu_arm1022_name, #object
461cpu_arm1022_name: 458cpu_arm1022_name:
462 .ascii "arm1022" 459 .asciz "ARM1022"
463#ifndef CONFIG_CPU_ICACHE_DISABLE
464 .ascii "i"
465#endif
466#ifndef CONFIG_CPU_DCACHE_DISABLE
467 .ascii "d"
468#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
469 .ascii "(wt)"
470#else
471 .ascii "(wb)"
472#endif
473#endif
474#ifndef CONFIG_CPU_BPREDICT_DISABLE
475 .ascii "B"
476#endif
477#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
478 .ascii "RR"
479#endif
480 .ascii "\0"
481 .size cpu_arm1022_name, . - cpu_arm1022_name 460 .size cpu_arm1022_name, . - cpu_arm1022_name
482 461
483 .align 462 .align
@@ -492,6 +471,10 @@ __arm1022_proc_info:
492 PMD_BIT4 | \ 471 PMD_BIT4 | \
493 PMD_SECT_AP_WRITE | \ 472 PMD_SECT_AP_WRITE | \
494 PMD_SECT_AP_READ 473 PMD_SECT_AP_READ
474 .long PMD_TYPE_SECT | \
475 PMD_BIT4 | \
476 PMD_SECT_AP_WRITE | \
477 PMD_SECT_AP_READ
495 b __arm1022_setup 478 b __arm1022_setup
496 .long cpu_arch_name 479 .long cpu_arch_name
497 .long cpu_elf_name 480 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 33e1ab8eb1d6..6ea76321d0df 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -398,11 +398,11 @@ __arm1026_setup:
398 mov r0, #4 @ explicitly disable writeback 398 mov r0, #4 @ explicitly disable writeback
399 mcr p15, 7, r0, c15, c0, 0 399 mcr p15, 7, r0, c15, c0, 0
400#endif 400#endif
401 adr r5, arm1026_crval
402 ldmia r5, {r5, r6}
401 mrc p15, 0, r0, c1, c0 @ get control register v4 403 mrc p15, 0, r0, c1, c0 @ get control register v4
402 ldr r5, arm1026_cr1_clear
403 bic r0, r0, r5 404 bic r0, r0, r5
404 ldr r5, arm1026_cr1_set 405 orr r0, r0, r6
405 orr r0, r0, r5
406#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 406#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
407 orr r0, r0, #0x4000 @ .R.. .... .... .... 407 orr r0, r0, #0x4000 @ .R.. .... .... ....
408#endif 408#endif
@@ -415,12 +415,9 @@ __arm1026_setup:
415 * .011 1001 ..11 0101 415 * .011 1001 ..11 0101
416 * 416 *
417 */ 417 */
418 .type arm1026_cr1_clear, #object 418 .type arm1026_crval, #object
419 .type arm1026_cr1_set, #object 419arm1026_crval:
420arm1026_cr1_clear: 420 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
421 .word 0x7f3f
422arm1026_cr1_set:
423 .word 0x3935
424 421
425 __INITDATA 422 __INITDATA
426 423
@@ -455,25 +452,7 @@ cpu_elf_name:
455 452
456 .type cpu_arm1026_name, #object 453 .type cpu_arm1026_name, #object
457cpu_arm1026_name: 454cpu_arm1026_name:
458 .ascii "ARM1026EJ-S" 455 .asciz "ARM1026EJ-S"
459#ifndef CONFIG_CPU_ICACHE_DISABLE
460 .ascii "i"
461#endif
462#ifndef CONFIG_CPU_DCACHE_DISABLE
463 .ascii "d"
464#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
465 .ascii "(wt)"
466#else
467 .ascii "(wb)"
468#endif
469#endif
470#ifndef CONFIG_CPU_BPREDICT_DISABLE
471 .ascii "B"
472#endif
473#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
474 .ascii "RR"
475#endif
476 .ascii "\0"
477 .size cpu_arm1026_name, . - cpu_arm1026_name 456 .size cpu_arm1026_name, . - cpu_arm1026_name
478 457
479 .align 458 .align
@@ -488,6 +467,10 @@ __arm1026_proc_info:
488 PMD_BIT4 | \ 467 PMD_BIT4 | \
489 PMD_SECT_AP_WRITE | \ 468 PMD_SECT_AP_WRITE | \
490 PMD_SECT_AP_READ 469 PMD_SECT_AP_READ
470 .long PMD_TYPE_SECT | \
471 PMD_BIT4 | \
472 PMD_SECT_AP_WRITE | \
473 PMD_SECT_AP_READ
491 b __arm1026_setup 474 b __arm1026_setup
492 .long cpu_arch_name 475 .long cpu_arch_name
493 .long cpu_elf_name 476 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 7a705edfa4b2..0432e4806888 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -355,6 +355,10 @@ __arm6_proc_info:
355 .long 0x41560600 355 .long 0x41560600
356 .long 0xfffffff0 356 .long 0xfffffff0
357 .long 0x00000c1e 357 .long 0x00000c1e
358 .long PMD_TYPE_SECT | \
359 PMD_BIT4 | \
360 PMD_SECT_AP_WRITE | \
361 PMD_SECT_AP_READ
358 b __arm6_setup 362 b __arm6_setup
359 .long cpu_arch_name 363 .long cpu_arch_name
360 .long cpu_elf_name 364 .long cpu_elf_name
@@ -371,6 +375,10 @@ __arm610_proc_info:
371 .long 0x41560610 375 .long 0x41560610
372 .long 0xfffffff0 376 .long 0xfffffff0
373 .long 0x00000c1e 377 .long 0x00000c1e
378 .long PMD_TYPE_SECT | \
379 PMD_BIT4 | \
380 PMD_SECT_AP_WRITE | \
381 PMD_SECT_AP_READ
374 b __arm6_setup 382 b __arm6_setup
375 .long cpu_arch_name 383 .long cpu_arch_name
376 .long cpu_elf_name 384 .long cpu_elf_name
@@ -387,6 +395,10 @@ __arm7_proc_info:
387 .long 0x41007000 395 .long 0x41007000
388 .long 0xffffff00 396 .long 0xffffff00
389 .long 0x00000c1e 397 .long 0x00000c1e
398 .long PMD_TYPE_SECT | \
399 PMD_BIT4 | \
400 PMD_SECT_AP_WRITE | \
401 PMD_SECT_AP_READ
390 b __arm7_setup 402 b __arm7_setup
391 .long cpu_arch_name 403 .long cpu_arch_name
392 .long cpu_elf_name 404 .long cpu_elf_name
@@ -408,6 +420,10 @@ __arm710_proc_info:
408 PMD_BIT4 | \ 420 PMD_BIT4 | \
409 PMD_SECT_AP_WRITE | \ 421 PMD_SECT_AP_WRITE | \
410 PMD_SECT_AP_READ 422 PMD_SECT_AP_READ
423 .long PMD_TYPE_SECT | \
424 PMD_BIT4 | \
425 PMD_SECT_AP_WRITE | \
426 PMD_SECT_AP_READ
411 b __arm7_setup 427 b __arm7_setup
412 .long cpu_arch_name 428 .long cpu_arch_name
413 .long cpu_elf_name 429 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 86102467d37f..0e6946ab6e5b 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -169,11 +169,11 @@ __arm720_setup:
169#ifdef CONFIG_MMU 169#ifdef CONFIG_MMU
170 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) 170 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
171#endif 171#endif
172 adr r5, arm720_crval
173 ldmia r5, {r5, r6}
172 mrc p15, 0, r0, c1, c0 @ get control register 174 mrc p15, 0, r0, c1, c0 @ get control register
173 ldr r5, arm720_cr1_clear
174 bic r0, r0, r5 175 bic r0, r0, r5
175 ldr r5, arm720_cr1_set 176 orr r0, r0, r6
176 orr r0, r0, r5
177 mov pc, lr @ __ret (head.S) 177 mov pc, lr @ __ret (head.S)
178 .size __arm720_setup, . - __arm720_setup 178 .size __arm720_setup, . - __arm720_setup
179 179
@@ -183,12 +183,9 @@ __arm720_setup:
183 * ..1. 1001 ..11 1101 183 * ..1. 1001 ..11 1101
184 * 184 *
185 */ 185 */
186 .type arm720_cr1_clear, #object 186 .type arm720_crval, #object
187 .type arm720_cr1_set, #object 187arm720_crval:
188arm720_cr1_clear: 188 crval clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
189 .word 0x2f3f
190arm720_cr1_set:
191 .word 0x213d
192 189
193 __INITDATA 190 __INITDATA
194 191
@@ -246,6 +243,10 @@ __arm710_proc_info:
246 PMD_BIT4 | \ 243 PMD_BIT4 | \
247 PMD_SECT_AP_WRITE | \ 244 PMD_SECT_AP_WRITE | \
248 PMD_SECT_AP_READ 245 PMD_SECT_AP_READ
246 .long PMD_TYPE_SECT | \
247 PMD_BIT4 | \
248 PMD_SECT_AP_WRITE | \
249 PMD_SECT_AP_READ
249 b __arm710_setup @ cpu_flush 250 b __arm710_setup @ cpu_flush
250 .long cpu_arch_name @ arch_name 251 .long cpu_arch_name @ arch_name
251 .long cpu_elf_name @ elf_name 252 .long cpu_elf_name @ elf_name
@@ -267,6 +268,10 @@ __arm720_proc_info:
267 PMD_BIT4 | \ 268 PMD_BIT4 | \
268 PMD_SECT_AP_WRITE | \ 269 PMD_SECT_AP_WRITE | \
269 PMD_SECT_AP_READ 270 PMD_SECT_AP_READ
271 .long PMD_TYPE_SECT | \
272 PMD_BIT4 | \
273 PMD_SECT_AP_WRITE | \
274 PMD_SECT_AP_READ
270 b __arm720_setup @ cpu_flush 275 b __arm720_setup @ cpu_flush
271 .long cpu_arch_name @ arch_name 276 .long cpu_arch_name @ arch_name
272 .long cpu_elf_name @ elf_name 277 .long cpu_elf_name @ elf_name
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 6f0db29ab842..4adb46b3a4e0 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -390,11 +390,11 @@ __arm920_setup:
390#ifdef CONFIG_MMU 390#ifdef CONFIG_MMU
391 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 391 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
392#endif 392#endif
393 adr r5, arm920_crval
394 ldmia r5, {r5, r6}
393 mrc p15, 0, r0, c1, c0 @ get control register v4 395 mrc p15, 0, r0, c1, c0 @ get control register v4
394 ldr r5, arm920_cr1_clear
395 bic r0, r0, r5 396 bic r0, r0, r5
396 ldr r5, arm920_cr1_set 397 orr r0, r0, r6
397 orr r0, r0, r5
398 mov pc, lr 398 mov pc, lr
399 .size __arm920_setup, . - __arm920_setup 399 .size __arm920_setup, . - __arm920_setup
400 400
@@ -404,12 +404,9 @@ __arm920_setup:
404 * ..11 0001 ..11 0101 404 * ..11 0001 ..11 0101
405 * 405 *
406 */ 406 */
407 .type arm920_cr1_clear, #object 407 .type arm920_crval, #object
408 .type arm920_cr1_set, #object 408arm920_crval:
409arm920_cr1_clear: 409 crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
410 .word 0x3f3f
411arm920_cr1_set:
412 .word 0x3135
413 410
414 __INITDATA 411 __INITDATA
415 412
@@ -443,19 +440,7 @@ cpu_elf_name:
443 440
444 .type cpu_arm920_name, #object 441 .type cpu_arm920_name, #object
445cpu_arm920_name: 442cpu_arm920_name:
446 .ascii "ARM920T" 443 .asciz "ARM920T"
447#ifndef CONFIG_CPU_ICACHE_DISABLE
448 .ascii "i"
449#endif
450#ifndef CONFIG_CPU_DCACHE_DISABLE
451 .ascii "d"
452#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
453 .ascii "(wt)"
454#else
455 .ascii "(wb)"
456#endif
457#endif
458 .ascii "\0"
459 .size cpu_arm920_name, . - cpu_arm920_name 444 .size cpu_arm920_name, . - cpu_arm920_name
460 445
461 .align 446 .align
@@ -472,6 +457,10 @@ __arm920_proc_info:
472 PMD_BIT4 | \ 457 PMD_BIT4 | \
473 PMD_SECT_AP_WRITE | \ 458 PMD_SECT_AP_WRITE | \
474 PMD_SECT_AP_READ 459 PMD_SECT_AP_READ
460 .long PMD_TYPE_SECT | \
461 PMD_BIT4 | \
462 PMD_SECT_AP_WRITE | \
463 PMD_SECT_AP_READ
475 b __arm920_setup 464 b __arm920_setup
476 .long cpu_arch_name 465 .long cpu_arch_name
477 .long cpu_elf_name 466 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 1ad464cc7bcb..571f082f0247 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -394,11 +394,11 @@ __arm922_setup:
394#ifdef CONFIG_MMU 394#ifdef CONFIG_MMU
395 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 395 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
396#endif 396#endif
397 adr r5, arm922_crval
398 ldmia r5, {r5, r6}
397 mrc p15, 0, r0, c1, c0 @ get control register v4 399 mrc p15, 0, r0, c1, c0 @ get control register v4
398 ldr r5, arm922_cr1_clear
399 bic r0, r0, r5 400 bic r0, r0, r5
400 ldr r5, arm922_cr1_set 401 orr r0, r0, r6
401 orr r0, r0, r5
402 mov pc, lr 402 mov pc, lr
403 .size __arm922_setup, . - __arm922_setup 403 .size __arm922_setup, . - __arm922_setup
404 404
@@ -408,12 +408,9 @@ __arm922_setup:
408 * ..11 0001 ..11 0101 408 * ..11 0001 ..11 0101
409 * 409 *
410 */ 410 */
411 .type arm922_cr1_clear, #object 411 .type arm922_crval, #object
412 .type arm922_cr1_set, #object 412arm922_crval:
413arm922_cr1_clear: 413 crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
414 .word 0x3f3f
415arm922_cr1_set:
416 .word 0x3135
417 414
418 __INITDATA 415 __INITDATA
419 416
@@ -447,19 +444,7 @@ cpu_elf_name:
447 444
448 .type cpu_arm922_name, #object 445 .type cpu_arm922_name, #object
449cpu_arm922_name: 446cpu_arm922_name:
450 .ascii "ARM922T" 447 .asciz "ARM922T"
451#ifndef CONFIG_CPU_ICACHE_DISABLE
452 .ascii "i"
453#endif
454#ifndef CONFIG_CPU_DCACHE_DISABLE
455 .ascii "d"
456#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
457 .ascii "(wt)"
458#else
459 .ascii "(wb)"
460#endif
461#endif
462 .ascii "\0"
463 .size cpu_arm922_name, . - cpu_arm922_name 448 .size cpu_arm922_name, . - cpu_arm922_name
464 449
465 .align 450 .align
@@ -476,6 +461,10 @@ __arm922_proc_info:
476 PMD_BIT4 | \ 461 PMD_BIT4 | \
477 PMD_SECT_AP_WRITE | \ 462 PMD_SECT_AP_WRITE | \
478 PMD_SECT_AP_READ 463 PMD_SECT_AP_READ
464 .long PMD_TYPE_SECT | \
465 PMD_BIT4 | \
466 PMD_SECT_AP_WRITE | \
467 PMD_SECT_AP_READ
479 b __arm922_setup 468 b __arm922_setup
480 .long cpu_arch_name 469 .long cpu_arch_name
481 .long cpu_elf_name 470 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index a55d56ce2264..ad15f8503d51 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -454,11 +454,10 @@ __arm925_setup:
454 mcr p15, 7, r0, c15, c0, 0 454 mcr p15, 7, r0, c15, c0, 0
455#endif 455#endif
456 456
457 adr r5, {r5, r6}
457 mrc p15, 0, r0, c1, c0 @ get control register v4 458 mrc p15, 0, r0, c1, c0 @ get control register v4
458 ldr r5, arm925_cr1_clear
459 bic r0, r0, r5 459 bic r0, r0, r5
460 ldr r5, arm925_cr1_set 460 orr r0, r0, r6
461 orr r0, r0, r5
462#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 461#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
463 orr r0, r0, #0x4000 @ .1.. .... .... .... 462 orr r0, r0, #0x4000 @ .1.. .... .... ....
464#endif 463#endif
@@ -471,12 +470,9 @@ __arm925_setup:
471 * .011 0001 ..11 1101 470 * .011 0001 ..11 1101
472 * 471 *
473 */ 472 */
474 .type arm925_cr1_clear, #object 473 .type arm925_crval, #object
475 .type arm925_cr1_set, #object 474arm925_crval:
476arm925_cr1_clear: 475 crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
477 .word 0x7f3f
478arm925_cr1_set:
479 .word 0x313d
480 476
481 __INITDATA 477 __INITDATA
482 478
@@ -510,22 +506,7 @@ cpu_elf_name:
510 506
511 .type cpu_arm925_name, #object 507 .type cpu_arm925_name, #object
512cpu_arm925_name: 508cpu_arm925_name:
513 .ascii "ARM925T" 509 .asciz "ARM925T"
514#ifndef CONFIG_CPU_ICACHE_DISABLE
515 .ascii "i"
516#endif
517#ifndef CONFIG_CPU_DCACHE_DISABLE
518 .ascii "d"
519#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
520 .ascii "(wt)"
521#else
522 .ascii "(wb)"
523#endif
524#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
525 .ascii "RR"
526#endif
527#endif
528 .ascii "\0"
529 .size cpu_arm925_name, . - cpu_arm925_name 510 .size cpu_arm925_name, . - cpu_arm925_name
530 511
531 .align 512 .align
@@ -540,6 +521,10 @@ __arm925_proc_info:
540 PMD_BIT4 | \ 521 PMD_BIT4 | \
541 PMD_SECT_AP_WRITE | \ 522 PMD_SECT_AP_WRITE | \
542 PMD_SECT_AP_READ 523 PMD_SECT_AP_READ
524 .long PMD_TYPE_SECT | \
525 PMD_BIT4 | \
526 PMD_SECT_AP_WRITE | \
527 PMD_SECT_AP_READ
543 b __arm925_setup 528 b __arm925_setup
544 .long cpu_arch_name 529 .long cpu_arch_name
545 .long cpu_elf_name 530 .long cpu_elf_name
@@ -559,6 +544,10 @@ __arm915_proc_info:
559 PMD_BIT4 | \ 544 PMD_BIT4 | \
560 PMD_SECT_AP_WRITE | \ 545 PMD_SECT_AP_WRITE | \
561 PMD_SECT_AP_READ 546 PMD_SECT_AP_READ
547 .long PMD_TYPE_SECT | \
548 PMD_BIT4 | \
549 PMD_SECT_AP_WRITE | \
550 PMD_SECT_AP_READ
562 b __arm925_setup 551 b __arm925_setup
563 .long cpu_arch_name 552 .long cpu_arch_name
564 .long cpu_elf_name 553 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 20275967663d..1e89d4080474 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -403,11 +403,11 @@ __arm926_setup:
403 mcr p15, 7, r0, c15, c0, 0 403 mcr p15, 7, r0, c15, c0, 0
404#endif 404#endif
405 405
406 adr r5, arm926_crval
407 ldmia r5, {r5, r6}
406 mrc p15, 0, r0, c1, c0 @ get control register v4 408 mrc p15, 0, r0, c1, c0 @ get control register v4
407 ldr r5, arm926_cr1_clear
408 bic r0, r0, r5 409 bic r0, r0, r5
409 ldr r5, arm926_cr1_set 410 orr r0, r0, r6
410 orr r0, r0, r5
411#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 411#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
412 orr r0, r0, #0x4000 @ .1.. .... .... .... 412 orr r0, r0, #0x4000 @ .1.. .... .... ....
413#endif 413#endif
@@ -420,12 +420,9 @@ __arm926_setup:
420 * .011 0001 ..11 0101 420 * .011 0001 ..11 0101
421 * 421 *
422 */ 422 */
423 .type arm926_cr1_clear, #object 423 .type arm926_crval, #object
424 .type arm926_cr1_set, #object 424arm926_crval:
425arm926_cr1_clear: 425 crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
426 .word 0x7f3f
427arm926_cr1_set:
428 .word 0x3135
429 426
430 __INITDATA 427 __INITDATA
431 428
@@ -459,22 +456,7 @@ cpu_elf_name:
459 456
460 .type cpu_arm926_name, #object 457 .type cpu_arm926_name, #object
461cpu_arm926_name: 458cpu_arm926_name:
462 .ascii "ARM926EJ-S" 459 .asciz "ARM926EJ-S"
463#ifndef CONFIG_CPU_ICACHE_DISABLE
464 .ascii "i"
465#endif
466#ifndef CONFIG_CPU_DCACHE_DISABLE
467 .ascii "d"
468#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
469 .ascii "(wt)"
470#else
471 .ascii "(wb)"
472#endif
473#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
474 .ascii "RR"
475#endif
476#endif
477 .ascii "\0"
478 .size cpu_arm926_name, . - cpu_arm926_name 460 .size cpu_arm926_name, . - cpu_arm926_name
479 461
480 .align 462 .align
@@ -491,6 +473,10 @@ __arm926_proc_info:
491 PMD_BIT4 | \ 473 PMD_BIT4 | \
492 PMD_SECT_AP_WRITE | \ 474 PMD_SECT_AP_WRITE | \
493 PMD_SECT_AP_READ 475 PMD_SECT_AP_READ
476 .long PMD_TYPE_SECT | \
477 PMD_BIT4 | \
478 PMD_SECT_AP_WRITE | \
479 PMD_SECT_AP_READ
494 b __arm926_setup 480 b __arm926_setup
495 .long cpu_arch_name 481 .long cpu_arch_name
496 .long cpu_elf_name 482 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 7cfc2604a1ee..9e2c89eb2115 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -49,3 +49,13 @@
49 .macro asid, rd, rn 49 .macro asid, rd, rn
50 and \rd, \rn, #255 50 and \rd, \rn, #255
51 .endm 51 .endm
52
53 .macro crval, clear, mmuset, ucset
54#ifdef CONFIG_MMU
55 .word \clear
56 .word \mmuset
57#else
58 .word \clear
59 .word \ucset
60#endif
61 .endm
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 5a760a2c629c..e812246277cf 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -185,11 +185,12 @@ __sa110_setup:
185#ifdef CONFIG_MMU 185#ifdef CONFIG_MMU
186 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4 186 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
187#endif 187#endif
188
189 adr r5, sa110_crval
190 ldmia r5, {r5, r6}
188 mrc p15, 0, r0, c1, c0 @ get control register v4 191 mrc p15, 0, r0, c1, c0 @ get control register v4
189 ldr r5, sa110_cr1_clear
190 bic r0, r0, r5 192 bic r0, r0, r5
191 ldr r5, sa110_cr1_set 193 orr r0, r0, r6
192 orr r0, r0, r5
193 mov pc, lr 194 mov pc, lr
194 .size __sa110_setup, . - __sa110_setup 195 .size __sa110_setup, . - __sa110_setup
195 196
@@ -199,12 +200,9 @@ __sa110_setup:
199 * ..01 0001 ..11 1101 200 * ..01 0001 ..11 1101
200 * 201 *
201 */ 202 */
202 .type sa110_cr1_clear, #object 203 .type sa110_crval, #object
203 .type sa110_cr1_set, #object 204sa110_crval:
204sa110_cr1_clear: 205 crval clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
205 .word 0x3f3f
206sa110_cr1_set:
207 .word 0x113d
208 206
209 __INITDATA 207 __INITDATA
210 208
@@ -255,6 +253,9 @@ __sa110_proc_info:
255 PMD_SECT_CACHEABLE | \ 253 PMD_SECT_CACHEABLE | \
256 PMD_SECT_AP_WRITE | \ 254 PMD_SECT_AP_WRITE | \
257 PMD_SECT_AP_READ 255 PMD_SECT_AP_READ
256 .long PMD_TYPE_SECT | \
257 PMD_SECT_AP_WRITE | \
258 PMD_SECT_AP_READ
258 b __sa110_setup 259 b __sa110_setup
259 .long cpu_arch_name 260 .long cpu_arch_name
260 .long cpu_elf_name 261 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 0a2107ad4c32..ba32cc6296a0 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -198,11 +198,11 @@ __sa1100_setup:
198#ifdef CONFIG_MMU 198#ifdef CONFIG_MMU
199 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 199 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
200#endif 200#endif
201 adr r5, sa1100_crval
202 ldmia r5, {r5, r6}
201 mrc p15, 0, r0, c1, c0 @ get control register v4 203 mrc p15, 0, r0, c1, c0 @ get control register v4
202 ldr r5, sa1100_cr1_clear
203 bic r0, r0, r5 204 bic r0, r0, r5
204 ldr r5, sa1100_cr1_set 205 orr r0, r0, r6
205 orr r0, r0, r5
206 mov pc, lr 206 mov pc, lr
207 .size __sa1100_setup, . - __sa1100_setup 207 .size __sa1100_setup, . - __sa1100_setup
208 208
@@ -212,12 +212,9 @@ __sa1100_setup:
212 * ..11 0001 ..11 1101 212 * ..11 0001 ..11 1101
213 * 213 *
214 */ 214 */
215 .type sa1100_cr1_clear, #object 215 .type sa1100_crval, #object
216 .type sa1100_cr1_set, #object 216sa1100_crval:
217sa1100_cr1_clear: 217 crval clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
218 .word 0x3f3f
219sa1100_cr1_set:
220 .word 0x313d
221 218
222 __INITDATA 219 __INITDATA
223 220
@@ -276,6 +273,9 @@ __sa1100_proc_info:
276 PMD_SECT_CACHEABLE | \ 273 PMD_SECT_CACHEABLE | \
277 PMD_SECT_AP_WRITE | \ 274 PMD_SECT_AP_WRITE | \
278 PMD_SECT_AP_READ 275 PMD_SECT_AP_READ
276 .long PMD_TYPE_SECT | \
277 PMD_SECT_AP_WRITE | \
278 PMD_SECT_AP_READ
279 b __sa1100_setup 279 b __sa1100_setup
280 .long cpu_arch_name 280 .long cpu_arch_name
281 .long cpu_elf_name 281 .long cpu_elf_name
@@ -296,6 +296,9 @@ __sa1110_proc_info:
296 PMD_SECT_CACHEABLE | \ 296 PMD_SECT_CACHEABLE | \
297 PMD_SECT_AP_WRITE | \ 297 PMD_SECT_AP_WRITE | \
298 PMD_SECT_AP_READ 298 PMD_SECT_AP_READ
299 .long PMD_TYPE_SECT | \
300 PMD_SECT_AP_WRITE | \
301 PMD_SECT_AP_READ
299 b __sa1100_setup 302 b __sa1100_setup
300 .long cpu_arch_name 303 .long cpu_arch_name
301 .long cpu_elf_name 304 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index ca13d4d05f65..6f72549f8843 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -212,11 +212,11 @@ __v6_setup:
212 orr r0, r0, #(0xf << 20) 212 orr r0, r0, #(0xf << 20)
213 mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP 213 mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP
214#endif 214#endif
215 adr r5, v6_crval
216 ldmia r5, {r5, r6}
215 mrc p15, 0, r0, c1, c0, 0 @ read control register 217 mrc p15, 0, r0, c1, c0, 0 @ read control register
216 ldr r5, v6_cr1_clear @ get mask for bits to clear
217 bic r0, r0, r5 @ clear bits them 218 bic r0, r0, r5 @ clear bits them
218 ldr r5, v6_cr1_set @ get mask for bits to set 219 orr r0, r0, r6 @ set them
219 orr r0, r0, r5 @ set them
220 mov pc, lr @ return to head.S:__ret 220 mov pc, lr @ return to head.S:__ret
221 221
222 /* 222 /*
@@ -225,12 +225,9 @@ __v6_setup:
225 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced 225 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
226 * 0 110 0011 1.00 .111 1101 < we want 226 * 0 110 0011 1.00 .111 1101 < we want
227 */ 227 */
228 .type v6_cr1_clear, #object 228 .type v6_crval, #object
229 .type v6_cr1_set, #object 229v6_crval:
230v6_cr1_clear: 230 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
231 .word 0x01e0fb7f
232v6_cr1_set:
233 .word 0x00c0387d
234 231
235 .type v6_processor_functions, #object 232 .type v6_processor_functions, #object
236ENTRY(v6_processor_functions) 233ENTRY(v6_processor_functions)
@@ -269,6 +266,10 @@ __v6_proc_info:
269 PMD_SECT_CACHEABLE | \ 266 PMD_SECT_CACHEABLE | \
270 PMD_SECT_AP_WRITE | \ 267 PMD_SECT_AP_WRITE | \
271 PMD_SECT_AP_READ 268 PMD_SECT_AP_READ
269 .long PMD_TYPE_SECT | \
270 PMD_SECT_XN | \
271 PMD_SECT_AP_WRITE | \
272 PMD_SECT_AP_READ
272 b __v6_setup 273 b __v6_setup
273 .long cpu_arch_name 274 .long cpu_arch_name
274 .long cpu_elf_name 275 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 8d32e21fe151..4ace2d8090c7 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -426,23 +426,26 @@ __xsc3_setup:
426 orr r0, r0, #(1 << 10) @ enable L2 for LLR cache 426 orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
427#endif 427#endif
428 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg 428 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
429
430 adr r5, xsc3_crval
431 ldmia r5, {r5, r6}
429 mrc p15, 0, r0, c1, c0, 0 @ get control register 432 mrc p15, 0, r0, c1, c0, 0 @ get control register
430 bic r0, r0, #0x0002 @ .... .... .... ..A. 433 bic r0, r0, r5 @ .... .... .... ..A.
431 orr r0, r0, #0x0005 @ .... .... .... .C.M 434 orr r0, r0, r6 @ .... .... .... .C.M
432#if BTB_ENABLE 435#if BTB_ENABLE
433 bic r0, r0, #0x0200 @ .... ..R. .... .... 436 orr r0, r0, #0x00000800 @ ..VI Z..S .... ....
434 orr r0, r0, #0x3900 @ ..VI Z..S .... ....
435#else
436 bic r0, r0, #0x0a00 @ .... Z.R. .... ....
437 orr r0, r0, #0x3100 @ ..VI ...S .... ....
438#endif 437#endif
439#if L2_CACHE_ENABLE 438#if L2_CACHE_ENABLE
440 orr r0, r0, #0x4000000 @ L2 enable 439 orr r0, r0, #0x04000000 @ L2 enable
441#endif 440#endif
442 mov pc, lr 441 mov pc, lr
443 442
444 .size __xsc3_setup, . - __xsc3_setup 443 .size __xsc3_setup, . - __xsc3_setup
445 444
445 .type xsc3_crval, #object
446xsc3_crval:
447 crval clear=0x04003b02, mmuset=0x00003105, ucset=0x00001100
448
446 __INITDATA 449 __INITDATA
447 450
448/* 451/*
@@ -487,7 +490,14 @@ cpu_xsc3_name:
487__xsc3_proc_info: 490__xsc3_proc_info:
488 .long 0x69056000 491 .long 0x69056000
489 .long 0xffffe000 492 .long 0xffffe000
490 .long 0x00000c0e 493 .long PMD_TYPE_SECT | \
494 PMD_SECT_BUFFERABLE | \
495 PMD_SECT_CACHEABLE | \
496 PMD_SECT_AP_WRITE | \
497 PMD_SECT_AP_READ
498 .long PMD_TYPE_SECT | \
499 PMD_SECT_AP_WRITE | \
500 PMD_SECT_AP_READ
491 b __xsc3_setup 501 b __xsc3_setup
492 .long cpu_arch_name 502 .long cpu_arch_name
493 .long cpu_elf_name 503 .long cpu_elf_name
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 29bcc4dd6517..521538671f4c 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -138,17 +138,23 @@ ENTRY(cpu_xscale_proc_fin)
138 * to what would be the reset vector. 138 * to what would be the reset vector.
139 * 139 *
140 * loc: location to jump to for soft reset 140 * loc: location to jump to for soft reset
141 *
142 * Beware PXA270 erratum E7.
141 */ 143 */
142 .align 5 144 .align 5
143ENTRY(cpu_xscale_reset) 145ENTRY(cpu_xscale_reset)
144 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE 146 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
145 msr cpsr_c, r1 @ reset CPSR 147 msr cpsr_c, r1 @ reset CPSR
148 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
149 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
146 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 150 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
147 bic r1, r1, #0x0086 @ ........B....CA. 151 bic r1, r1, #0x0086 @ ........B....CA.
148 bic r1, r1, #0x3900 @ ..VIZ..S........ 152 bic r1, r1, #0x3900 @ ..VIZ..S........
153 sub pc, pc, #4 @ flush pipeline
154 @ *** cache line aligned ***
149 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 155 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
150 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
151 bic r1, r1, #0x0001 @ ...............M 156 bic r1, r1, #0x0001 @ ...............M
157 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
152 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 158 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
153 @ CAUTION: MMU turned off from this point. We count on the pipeline 159 @ CAUTION: MMU turned off from this point. We count on the pipeline
154 @ already containing those two last instructions to survive. 160 @ already containing those two last instructions to survive.
@@ -475,11 +481,12 @@ __xscale_setup:
475 orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde 481 orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
476 orr r0, r0, #1 << 13 @ Its undefined whether this 482 orr r0, r0, #1 << 13 @ Its undefined whether this
477 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes 483 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
484
485 adr r5, xscale_crval
486 ldmia r5, {r5, r6}
478 mrc p15, 0, r0, c1, c0, 0 @ get control register 487 mrc p15, 0, r0, c1, c0, 0 @ get control register
479 ldr r5, xscale_cr1_clear
480 bic r0, r0, r5 488 bic r0, r0, r5
481 ldr r5, xscale_cr1_set 489 orr r0, r0, r6
482 orr r0, r0, r5
483 mov pc, lr 490 mov pc, lr
484 .size __xscale_setup, . - __xscale_setup 491 .size __xscale_setup, . - __xscale_setup
485 492
@@ -489,12 +496,9 @@ __xscale_setup:
489 * ..11 1.01 .... .101 496 * ..11 1.01 .... .101
490 * 497 *
491 */ 498 */
492 .type xscale_cr1_clear, #object 499 .type xscale_crval, #object
493 .type xscale_cr1_set, #object 500xscale_crval:
494xscale_cr1_clear: 501 crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
495 .word 0x3b07
496xscale_cr1_set:
497 .word 0x3905
498 502
499 __INITDATA 503 __INITDATA
500 504
@@ -595,6 +599,9 @@ __80200_proc_info:
595 PMD_SECT_CACHEABLE | \ 599 PMD_SECT_CACHEABLE | \
596 PMD_SECT_AP_WRITE | \ 600 PMD_SECT_AP_WRITE | \
597 PMD_SECT_AP_READ 601 PMD_SECT_AP_READ
602 .long PMD_TYPE_SECT | \
603 PMD_SECT_AP_WRITE | \
604 PMD_SECT_AP_READ
598 b __xscale_setup 605 b __xscale_setup
599 .long cpu_arch_name 606 .long cpu_arch_name
600 .long cpu_elf_name 607 .long cpu_elf_name
@@ -615,6 +622,9 @@ __8032x_proc_info:
615 PMD_SECT_CACHEABLE | \ 622 PMD_SECT_CACHEABLE | \
616 PMD_SECT_AP_WRITE | \ 623 PMD_SECT_AP_WRITE | \
617 PMD_SECT_AP_READ 624 PMD_SECT_AP_READ
625 .long PMD_TYPE_SECT | \
626 PMD_SECT_AP_WRITE | \
627 PMD_SECT_AP_READ
618 b __xscale_setup 628 b __xscale_setup
619 .long cpu_arch_name 629 .long cpu_arch_name
620 .long cpu_elf_name 630 .long cpu_elf_name
@@ -635,6 +645,9 @@ __8033x_proc_info:
635 PMD_SECT_CACHEABLE | \ 645 PMD_SECT_CACHEABLE | \
636 PMD_SECT_AP_WRITE | \ 646 PMD_SECT_AP_WRITE | \
637 PMD_SECT_AP_READ 647 PMD_SECT_AP_READ
648 .long PMD_TYPE_SECT | \
649 PMD_SECT_AP_WRITE | \
650 PMD_SECT_AP_READ
638 b __xscale_setup 651 b __xscale_setup
639 .long cpu_arch_name 652 .long cpu_arch_name
640 .long cpu_elf_name 653 .long cpu_elf_name
@@ -655,6 +668,9 @@ __pxa250_proc_info:
655 PMD_SECT_CACHEABLE | \ 668 PMD_SECT_CACHEABLE | \
656 PMD_SECT_AP_WRITE | \ 669 PMD_SECT_AP_WRITE | \
657 PMD_SECT_AP_READ 670 PMD_SECT_AP_READ
671 .long PMD_TYPE_SECT | \
672 PMD_SECT_AP_WRITE | \
673 PMD_SECT_AP_READ
658 b __xscale_setup 674 b __xscale_setup
659 .long cpu_arch_name 675 .long cpu_arch_name
660 .long cpu_elf_name 676 .long cpu_elf_name
@@ -675,6 +691,9 @@ __pxa210_proc_info:
675 PMD_SECT_CACHEABLE | \ 691 PMD_SECT_CACHEABLE | \
676 PMD_SECT_AP_WRITE | \ 692 PMD_SECT_AP_WRITE | \
677 PMD_SECT_AP_READ 693 PMD_SECT_AP_READ
694 .long PMD_TYPE_SECT | \
695 PMD_SECT_AP_WRITE | \
696 PMD_SECT_AP_READ
678 b __xscale_setup 697 b __xscale_setup
679 .long cpu_arch_name 698 .long cpu_arch_name
680 .long cpu_elf_name 699 .long cpu_elf_name
@@ -695,6 +714,9 @@ __ixp2400_proc_info:
695 PMD_SECT_CACHEABLE | \ 714 PMD_SECT_CACHEABLE | \
696 PMD_SECT_AP_WRITE | \ 715 PMD_SECT_AP_WRITE | \
697 PMD_SECT_AP_READ 716 PMD_SECT_AP_READ
717 .long PMD_TYPE_SECT | \
718 PMD_SECT_AP_WRITE | \
719 PMD_SECT_AP_READ
698 b __xscale_setup 720 b __xscale_setup
699 .long cpu_arch_name 721 .long cpu_arch_name
700 .long cpu_elf_name 722 .long cpu_elf_name
@@ -715,6 +737,9 @@ __ixp2800_proc_info:
715 PMD_SECT_CACHEABLE | \ 737 PMD_SECT_CACHEABLE | \
716 PMD_SECT_AP_WRITE | \ 738 PMD_SECT_AP_WRITE | \
717 PMD_SECT_AP_READ 739 PMD_SECT_AP_READ
740 .long PMD_TYPE_SECT | \
741 PMD_SECT_AP_WRITE | \
742 PMD_SECT_AP_READ
718 b __xscale_setup 743 b __xscale_setup
719 .long cpu_arch_name 744 .long cpu_arch_name
720 .long cpu_elf_name 745 .long cpu_elf_name
@@ -735,6 +760,9 @@ __ixp42x_proc_info:
735 PMD_SECT_CACHEABLE | \ 760 PMD_SECT_CACHEABLE | \
736 PMD_SECT_AP_WRITE | \ 761 PMD_SECT_AP_WRITE | \
737 PMD_SECT_AP_READ 762 PMD_SECT_AP_READ
763 .long PMD_TYPE_SECT | \
764 PMD_SECT_AP_WRITE | \
765 PMD_SECT_AP_READ
738 b __xscale_setup 766 b __xscale_setup
739 .long cpu_arch_name 767 .long cpu_arch_name
740 .long cpu_elf_name 768 .long cpu_elf_name
@@ -750,7 +778,14 @@ __ixp42x_proc_info:
750__ixp46x_proc_info: 778__ixp46x_proc_info:
751 .long 0x69054200 779 .long 0x69054200
752 .long 0xffffff00 780 .long 0xffffff00
753 .long 0x00000c0e 781 .long PMD_TYPE_SECT | \
782 PMD_SECT_BUFFERABLE | \
783 PMD_SECT_CACHEABLE | \
784 PMD_SECT_AP_WRITE | \
785 PMD_SECT_AP_READ
786 .long PMD_TYPE_SECT | \
787 PMD_SECT_AP_WRITE | \
788 PMD_SECT_AP_READ
754 b __xscale_setup 789 b __xscale_setup
755 .long cpu_arch_name 790 .long cpu_arch_name
756 .long cpu_elf_name 791 .long cpu_elf_name
@@ -771,6 +806,9 @@ __pxa255_proc_info:
771 PMD_SECT_CACHEABLE | \ 806 PMD_SECT_CACHEABLE | \
772 PMD_SECT_AP_WRITE | \ 807 PMD_SECT_AP_WRITE | \
773 PMD_SECT_AP_READ 808 PMD_SECT_AP_READ
809 .long PMD_TYPE_SECT | \
810 PMD_SECT_AP_WRITE | \
811 PMD_SECT_AP_READ
774 b __xscale_setup 812 b __xscale_setup
775 .long cpu_arch_name 813 .long cpu_arch_name
776 .long cpu_elf_name 814 .long cpu_elf_name
@@ -791,6 +829,9 @@ __pxa270_proc_info:
791 PMD_SECT_CACHEABLE | \ 829 PMD_SECT_CACHEABLE | \
792 PMD_SECT_AP_WRITE | \ 830 PMD_SECT_AP_WRITE | \
793 PMD_SECT_AP_READ 831 PMD_SECT_AP_READ
832 .long PMD_TYPE_SECT | \
833 PMD_SECT_AP_WRITE | \
834 PMD_SECT_AP_READ
794 b __xscale_setup 835 b __xscale_setup
795 .long cpu_arch_name 836 .long cpu_arch_name
796 .long cpu_elf_name 837 .long cpu_elf_name
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-04 07:23:01 -0400