diff options
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 07f82db70945..41772960fd10 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
| @@ -175,7 +175,6 @@ __v7_setup: | |||
| 175 | mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs | 175 | mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs |
| 176 | mcr p15, 0, r10, c2, c0, 2 @ TTB control register | 176 | mcr p15, 0, r10, c2, c0, 2 @ TTB control register |
| 177 | orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB | 177 | orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB |
| 178 | mcr p15, 0, r4, c2, c0, 0 @ load TTB0 | ||
| 179 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 | 178 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 |
| 180 | mov r10, #0x1f @ domains 0, 1 = manager | 179 | mov r10, #0x1f @ domains 0, 1 = manager |
| 181 | mcr p15, 0, r10, c3, c0, 0 @ load domain access register | 180 | mcr p15, 0, r10, c3, c0, 0 @ load domain access register |