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-rw-r--r--arch/arm/mm/proc-v7.S12
1 files changed, 9 insertions, 3 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index c3f737516836..a18aace32990 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -19,17 +19,23 @@
19 19
20#include "proc-macros.S" 20#include "proc-macros.S"
21 21
22#define TTB_C (1 << 0)
23#define TTB_S (1 << 1) 22#define TTB_S (1 << 1)
24#define TTB_RGN_NC (0 << 3) 23#define TTB_RGN_NC (0 << 3)
25#define TTB_RGN_OC_WBWA (1 << 3) 24#define TTB_RGN_OC_WBWA (1 << 3)
26#define TTB_RGN_OC_WT (2 << 3) 25#define TTB_RGN_OC_WT (2 << 3)
27#define TTB_RGN_OC_WB (3 << 3) 26#define TTB_RGN_OC_WB (3 << 3)
27#define TTB_NOS (1 << 5)
28#define TTB_IRGN_NC ((0 << 0) | (0 << 6))
29#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
30#define TTB_IRGN_WT ((1 << 0) | (0 << 6))
31#define TTB_IRGN_WB ((1 << 0) | (1 << 6))
28 32
29#ifndef CONFIG_SMP 33#ifndef CONFIG_SMP
30#define TTB_FLAGS TTB_C|TTB_RGN_OC_WB @ mark PTWs cacheable, outer WB 34/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
35#define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB
31#else 36#else
32#define TTB_FLAGS TTB_C|TTB_S|TTB_RGN_OC_WBWA @ mark PTWs cacheable and shared, outer WBWA 37/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
38#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
33#endif 39#endif
34 40
35ENTRY(cpu_v7_proc_init) 41ENTRY(cpu_v7_proc_init)