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-rw-r--r--arch/arm/mm/cache-v6.S20
-rw-r--r--arch/arm/mm/cache-v7.S19
-rw-r--r--arch/arm/mm/fault-armv.c9
-rw-r--r--arch/arm/mm/fault.c5
-rw-r--r--arch/arm/mm/highmem.c2
-rw-r--r--arch/arm/mm/init.c2
6 files changed, 46 insertions, 11 deletions
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 8f5c13f4c936..295e25dd6381 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -12,6 +12,7 @@
12#include <linux/linkage.h> 12#include <linux/linkage.h>
13#include <linux/init.h> 13#include <linux/init.h>
14#include <asm/assembler.h> 14#include <asm/assembler.h>
15#include <asm/unwind.h>
15 16
16#include "proc-macros.S" 17#include "proc-macros.S"
17 18
@@ -121,11 +122,13 @@ ENTRY(v6_coherent_kern_range)
121 * - the Icache does not read data from the write buffer 122 * - the Icache does not read data from the write buffer
122 */ 123 */
123ENTRY(v6_coherent_user_range) 124ENTRY(v6_coherent_user_range)
124 125 UNWIND(.fnstart )
125#ifdef HARVARD_CACHE 126#ifdef HARVARD_CACHE
126 bic r0, r0, #CACHE_LINE_SIZE - 1 127 bic r0, r0, #CACHE_LINE_SIZE - 1
1271: mcr p15, 0, r0, c7, c10, 1 @ clean D line 1281:
129 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
128 add r0, r0, #CACHE_LINE_SIZE 130 add r0, r0, #CACHE_LINE_SIZE
1312:
129 cmp r0, r1 132 cmp r0, r1
130 blo 1b 133 blo 1b
131#endif 134#endif
@@ -143,6 +146,19 @@ ENTRY(v6_coherent_user_range)
143 mov pc, lr 146 mov pc, lr
144 147
145/* 148/*
149 * Fault handling for the cache operation above. If the virtual address in r0
150 * isn't mapped, just try the next page.
151 */
1529001:
153 mov r0, r0, lsr #12
154 mov r0, r0, lsl #12
155 add r0, r0, #4096
156 b 2b
157 UNWIND(.fnend )
158ENDPROC(v6_coherent_user_range)
159ENDPROC(v6_coherent_kern_range)
160
161/*
146 * v6_flush_kern_dcache_page(kaddr) 162 * v6_flush_kern_dcache_page(kaddr)
147 * 163 *
148 * Ensure that the data held in the page kaddr is written back 164 * Ensure that the data held in the page kaddr is written back
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index bda0ec31a4e2..e1bd9759617f 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -13,6 +13,7 @@
13#include <linux/linkage.h> 13#include <linux/linkage.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <asm/assembler.h> 15#include <asm/assembler.h>
16#include <asm/unwind.h>
16 17
17#include "proc-macros.S" 18#include "proc-macros.S"
18 19
@@ -153,13 +154,16 @@ ENTRY(v7_coherent_kern_range)
153 * - the Icache does not read data from the write buffer 154 * - the Icache does not read data from the write buffer
154 */ 155 */
155ENTRY(v7_coherent_user_range) 156ENTRY(v7_coherent_user_range)
157 UNWIND(.fnstart )
156 dcache_line_size r2, r3 158 dcache_line_size r2, r3
157 sub r3, r2, #1 159 sub r3, r2, #1
158 bic r0, r0, r3 160 bic r0, r0, r3
1591: mcr p15, 0, r0, c7, c11, 1 @ clean D line to the point of unification 1611:
162 USER( mcr p15, 0, r0, c7, c11, 1 ) @ clean D line to the point of unification
160 dsb 163 dsb
161 mcr p15, 0, r0, c7, c5, 1 @ invalidate I line 164 USER( mcr p15, 0, r0, c7, c5, 1 ) @ invalidate I line
162 add r0, r0, r2 165 add r0, r0, r2
1662:
163 cmp r0, r1 167 cmp r0, r1
164 blo 1b 168 blo 1b
165 mov r0, #0 169 mov r0, #0
@@ -167,6 +171,17 @@ ENTRY(v7_coherent_user_range)
167 dsb 171 dsb
168 isb 172 isb
169 mov pc, lr 173 mov pc, lr
174
175/*
176 * Fault handling for the cache operation above. If the virtual address in r0
177 * isn't mapped, just try the next page.
178 */
1799001:
180 mov r0, r0, lsr #12
181 mov r0, r0, lsl #12
182 add r0, r0, #4096
183 b 2b
184 UNWIND(.fnend )
170ENDPROC(v7_coherent_kern_range) 185ENDPROC(v7_coherent_kern_range)
171ENDPROC(v7_coherent_user_range) 186ENDPROC(v7_coherent_user_range)
172 187
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index bc0099d5ae85..d0d17b6a3703 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -153,14 +153,11 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
153 153
154 page = pfn_to_page(pfn); 154 page = pfn_to_page(pfn);
155 mapping = page_mapping(page); 155 mapping = page_mapping(page);
156 if (mapping) {
157#ifndef CONFIG_SMP 156#ifndef CONFIG_SMP
158 int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags); 157 if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
159 158 __flush_dcache_page(mapping, page);
160 if (dirty)
161 __flush_dcache_page(mapping, page);
162#endif 159#endif
163 160 if (mapping) {
164 if (cache_is_vivt()) 161 if (cache_is_vivt())
165 make_coherent(mapping, vma, addr, pfn); 162 make_coherent(mapping, vma, addr, pfn);
166 else if (vma->vm_flags & VM_EXEC) 163 else if (vma->vm_flags & VM_EXEC)
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index ae0e25f5a70e..10e06801afb3 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -292,6 +292,11 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
292 * down_read() 292 * down_read()
293 */ 293 */
294 might_sleep(); 294 might_sleep();
295#ifdef CONFIG_DEBUG_VM
296 if (!user_mode(regs) &&
297 !search_exception_tables(regs->ARM_pc))
298 goto no_context;
299#endif
295 } 300 }
296 301
297 fault = __do_page_fault(mm, addr, fsr, tsk); 302 fault = __do_page_fault(mm, addr, fsr, tsk);
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index 73cae57fa707..30f82fb5918c 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -46,6 +46,8 @@ void *kmap_atomic(struct page *page, enum km_type type)
46 if (!PageHighMem(page)) 46 if (!PageHighMem(page))
47 return page_address(page); 47 return page_address(page);
48 48
49 debug_kmap_atomic(type);
50
49 kmap = kmap_high_get(page); 51 kmap = kmap_high_get(page);
50 if (kmap) 52 if (kmap)
51 return kmap; 53 return kmap;
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 877c492f8e10..40940d7ce4ff 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -483,7 +483,7 @@ free_memmap(int node, unsigned long start_pfn, unsigned long end_pfn)
483 /* 483 /*
484 * Convert start_pfn/end_pfn to a struct page pointer. 484 * Convert start_pfn/end_pfn to a struct page pointer.
485 */ 485 */
486 start_pg = pfn_to_page(start_pfn); 486 start_pg = pfn_to_page(start_pfn - 1) + 1;
487 end_pg = pfn_to_page(end_pfn); 487 end_pg = pfn_to_page(end_pfn);
488 488
489 /* 489 /*