6 files changed, 81 insertions, 6 deletions
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 2c6c2a7c05a0..8f5c13f4c936 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -20,6 +20,31 @@
 #define D_CACHE_LINE_SIZE       32
 #define BTB_FLUSH_SIZE          8
+#ifdef CONFIG_ARM_ERRATA_411920
+/*
+ * Invalidate the entire I cache (this code is a workaround for the ARM1136
+ * erratum 411920 - Invalidate Instruction Cache operation can fail. This
+ * erratum is present in 1136, 1156 and 1176. It does not affect the MPCore.
+ *
+ * Registers:
+ *   r0 - set to 0
+ *   r1 - corrupted
+ */
+ENTRY(v6_icache_inval_all)
+        mov     r0, #0
+        mrs     r1, cpsr
+        cpsid   ifa                             @ disable interrupts
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate entire I-cache
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate entire I-cache
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate entire I-cache
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate entire I-cache
+        msr     cpsr_cx, r1                     @ restore interrupts
+        .rept   11                              @ ARM Ltd recommends at least
+        nop                                     @ 11 NOPs
+        .endr
+        mov     pc, lr
+#endif
 /*
 *      v6_flush_cache_all()
 *
@@ -31,8 +56,12 @@ ENTRY(v6_flush_kern_cache_all)
        mov     r0, #0
 #ifdef HARVARD_CACHE
        mcr     p15, 0, r0, c7, c14, 0          @ D cache clean+invalidate
+#ifndef CONFIG_ARM_ERRATA_411920
        mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
 #else
+        b       v6_icache_inval_all
+#endif
+#else
        mcr     p15, 0, r0, c7, c15, 0          @ Cache clean+invalidate
 #endif
        mov     pc, lr
@@ -103,8 +132,12 @@ ENTRY(v6_coherent_user_range)
        mov     r0, #0
 #ifdef HARVARD_CACHE
        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
+#ifndef CONFIG_ARM_ERRATA_411920
        mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
 #else
+        b       v6_icache_inval_all
+#endif
+#else
        mcr     p15, 0, r0, c7, c5, 6           @ invalidate BTB
 #endif
        mov     pc, lr
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 4e283481cee1..c07222eb5ce0 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -18,6 +18,10 @@
 #include "mm.h"
+#ifdef CONFIG_ARM_ERRATA_411920
+extern void v6_icache_inval_all(void);
+#endif
 #ifdef CONFIG_CPU_CACHE_VIPT
 #define ALIAS_FLUSH_START       0xffff4000
@@ -32,10 +36,15 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
        asm(    "mcrr   p15, 0, %1, %0, c14\n"
        "       mcr     p15, 0, %2, c7, c10, 4\n"
+#ifndef CONFIG_ARM_ERRATA_411920
        "       mcr     p15, 0, %2, c7, c5, 0\n"
+#endif
            :
            : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)
            : "cc");
+#ifdef CONFIG_ARM_ERRATA_411920
+        v6_icache_inval_all();
+#endif
 }
 void flush_cache_mm(struct mm_struct *mm)
@@ -48,11 +57,16 @@ void flush_cache_mm(struct mm_struct *mm)
        if (cache_is_vipt_aliasing()) {
                asm(    "mcr    p15, 0, %0, c7, c14, 0\n"
+                "       mcr     p15, 0, %0, c7, c10, 4\n"
+#ifndef CONFIG_ARM_ERRATA_411920
                "       mcr     p15, 0, %0, c7, c5, 0\n"
-                "       mcr     p15, 0, %0, c7, c10, 4"
+#endif
                    :
                    : "r" (0)
                    : "cc");
+#ifdef CONFIG_ARM_ERRATA_411920
+                v6_icache_inval_all();
+#endif
        }
 }
@@ -67,11 +81,16 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned
        if (cache_is_vipt_aliasing()) {
                asm(    "mcr    p15, 0, %0, c7, c14, 0\n"
+                "       mcr     p15, 0, %0, c7, c10, 4\n"
+#ifndef CONFIG_ARM_ERRATA_411920
                "       mcr     p15, 0, %0, c7, c5, 0\n"
-                "       mcr     p15, 0, %0, c7, c10, 4"
+#endif
                    :
                    : "r" (0)
                    : "cc");
+#ifdef CONFIG_ARM_ERRATA_411920
+                v6_icache_inval_all();
+#endif
        }
 }
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index f0cc599facb7..087e239704df 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -10,6 +10,7 @@
 *
 *  This is the "shell" of the ARMv6 processor support.
 */
+#include <linux/init.h>
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
@@ -132,7 +133,7 @@ cpu_v6_name:
        .asciz  "ARMv6-compatible processor"
        .align
-        .section ".text.init", #alloc, #execinstr
+        __INIT
 /*
 *      __v6_setup
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index d1ebec42521d..3397f1e64d76 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -9,6 +9,7 @@
 *
 *  This is the "shell" of the ARMv7 processor support.
 */
+#include <linux/init.h>
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
@@ -95,6 +96,9 @@ ENTRY(cpu_v7_switch_mm)
        mov     r2, #0
        ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
        orr     r0, r0, #TTB_FLAGS
+#ifdef CONFIG_ARM_ERRATA_430973
+        mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
+#endif
        mcr     p15, 0, r2, c13, c0, 1          @ set reserved context ID
        isb
 1:      mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
@@ -153,7 +157,7 @@ cpu_v7_name:
        .ascii  "ARMv7 Processor"
        .align
-        .section ".text.init", #alloc, #execinstr
+        __INIT
 /*
 *      __v7_setup
@@ -180,6 +184,22 @@ __v7_setup:
        stmia   r12, {r0-r5, r7, r9, r11, lr}
        bl      v7_flush_dcache_all
        ldmia   r12, {r0-r5, r7, r9, r11, lr}
+#ifdef CONFIG_ARM_ERRATA_430973
+        mrc     p15, 0, r10, c1, c0, 1          @ read aux control register
+        orr     r10, r10, #(1 << 6)             @ set IBE to 1
+        mcr     p15, 0, r10, c1, c0, 1          @ write aux control register
+#endif
+#ifdef CONFIG_ARM_ERRATA_458693
+        mrc     p15, 0, r10, c1, c0, 1          @ read aux control register
+        orr     r10, r10, #(1 << 5)             @ set L1NEON to 1
+        orr     r10, r10, #(1 << 9)             @ set PLDNOP to 1
+        mcr     p15, 0, r10, c1, c0, 1          @ write aux control register
+#endif
+#ifdef CONFIG_ARM_ERRATA_460075
+        mrc     p15, 1, r10, c9, c0, 2          @ read L2 cache aux ctrl register
+        orr     r10, r10, #(1 << 22)            @ set the Write Allocate disable bit
+        mcr     p15, 1, r10, c9, c0, 2          @ write the L2 cache aux ctrl register
+#endif
        mov     r10, #0
 #ifdef HARVARD_CACHE
        mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
diff --git a/arch/arm/mm/tlb-v6.S b/arch/arm/mm/tlb-v6.S
index 20f84bbaa9bb..73d7d89b04c4 100644
--- a/arch/arm/mm/tlb-v6.S
+++ b/arch/arm/mm/tlb-v6.S
@@ -10,6 +10,7 @@
 *  ARM architecture version 6 TLB handling functions.
 *  These assume a split I/D TLB.
 */
+#include <linux/init.h>
 #include <linux/linkage.h>
 #include <asm/asm-offsets.h>
 #include <asm/page.h>
@@ -87,7 +88,7 @@ ENTRY(v6wbi_flush_kern_tlb_range)
        mcr     p15, 0, r2, c7, c5, 4           @ prefetch flush
        mov     pc, lr
-        .section ".text.init", #alloc, #execinstr
+        __INIT
        .type   v6wbi_tlb_fns, #object
 ENTRY(v6wbi_tlb_fns)
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index 24ba5109f2e7..b637e7380ab7 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -11,6 +11,7 @@
 *  ARM architecture version 6 TLB handling functions.
 *  These assume a split I/D TLB.
 */
+#include <linux/init.h>
 #include <linux/linkage.h>
 #include <asm/asm-offsets.h>
 #include <asm/page.h>
@@ -80,7 +81,7 @@ ENTRY(v7wbi_flush_kern_tlb_range)
        mov     pc, lr
 ENDPROC(v7wbi_flush_kern_tlb_range)
-        .section ".text.init", #alloc, #execinstr
+        __INIT
        .type   v7wbi_tlb_fns, #object
 ENTRY(v7wbi_tlb_fns)