diff options
Diffstat (limited to 'arch/arm/mm')
-rw-r--r-- | arch/arm/mm/Kconfig | 2 | ||||
-rw-r--r-- | arch/arm/mm/proc-feroceon.S | 40 |
2 files changed, 1 insertions, 41 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 1b8229d9c9d5..a92a577c1b65 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig | |||
@@ -658,7 +658,7 @@ config CPU_DCACHE_SIZE | |||
658 | 658 | ||
659 | config CPU_DCACHE_WRITETHROUGH | 659 | config CPU_DCACHE_WRITETHROUGH |
660 | bool "Force write through D-cache" | 660 | bool "Force write through D-cache" |
661 | depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FEROCEON) && !CPU_DCACHE_DISABLE | 661 | depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE |
662 | default y if CPU_ARM925T | 662 | default y if CPU_ARM925T |
663 | help | 663 | help |
664 | Say Y here to use the data cache in writethrough mode. Unless you | 664 | Say Y here to use the data cache in writethrough mode. Unless you |
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index 90e7594e29b1..e9ac984d2897 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S | |||
@@ -118,12 +118,8 @@ ENTRY(feroceon_flush_kern_cache_all) | |||
118 | mov r2, #VM_EXEC | 118 | mov r2, #VM_EXEC |
119 | mov ip, #0 | 119 | mov ip, #0 |
120 | __flush_whole_cache: | 120 | __flush_whole_cache: |
121 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
122 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | ||
123 | #else | ||
124 | 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate | 121 | 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate |
125 | bne 1b | 122 | bne 1b |
126 | #endif | ||
127 | tst r2, #VM_EXEC | 123 | tst r2, #VM_EXEC |
128 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | 124 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache |
129 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB | 125 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB |
@@ -145,21 +141,12 @@ ENTRY(feroceon_flush_user_cache_range) | |||
145 | cmp r3, #CACHE_DLIMIT | 141 | cmp r3, #CACHE_DLIMIT |
146 | bgt __flush_whole_cache | 142 | bgt __flush_whole_cache |
147 | 1: tst r2, #VM_EXEC | 143 | 1: tst r2, #VM_EXEC |
148 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
149 | mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | ||
150 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | ||
151 | add r0, r0, #CACHE_DLINESIZE | ||
152 | mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | ||
153 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | ||
154 | add r0, r0, #CACHE_DLINESIZE | ||
155 | #else | ||
156 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry | 144 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry |
157 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | 145 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry |
158 | add r0, r0, #CACHE_DLINESIZE | 146 | add r0, r0, #CACHE_DLINESIZE |
159 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry | 147 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry |
160 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | 148 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry |
161 | add r0, r0, #CACHE_DLINESIZE | 149 | add r0, r0, #CACHE_DLINESIZE |
162 | #endif | ||
163 | cmp r0, r1 | 150 | cmp r0, r1 |
164 | blo 1b | 151 | blo 1b |
165 | tst r2, #VM_EXEC | 152 | tst r2, #VM_EXEC |
@@ -232,12 +219,10 @@ ENTRY(feroceon_flush_kern_dcache_page) | |||
232 | * (same as v4wb) | 219 | * (same as v4wb) |
233 | */ | 220 | */ |
234 | ENTRY(feroceon_dma_inv_range) | 221 | ENTRY(feroceon_dma_inv_range) |
235 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
236 | tst r0, #CACHE_DLINESIZE - 1 | 222 | tst r0, #CACHE_DLINESIZE - 1 |
237 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | 223 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
238 | tst r1, #CACHE_DLINESIZE - 1 | 224 | tst r1, #CACHE_DLINESIZE - 1 |
239 | mcrne p15, 0, r1, c7, c10, 1 @ clean D entry | 225 | mcrne p15, 0, r1, c7, c10, 1 @ clean D entry |
240 | #endif | ||
241 | bic r0, r0, #CACHE_DLINESIZE - 1 | 226 | bic r0, r0, #CACHE_DLINESIZE - 1 |
242 | 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | 227 | 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry |
243 | add r0, r0, #CACHE_DLINESIZE | 228 | add r0, r0, #CACHE_DLINESIZE |
@@ -257,13 +242,11 @@ ENTRY(feroceon_dma_inv_range) | |||
257 | * (same as v4wb) | 242 | * (same as v4wb) |
258 | */ | 243 | */ |
259 | ENTRY(feroceon_dma_clean_range) | 244 | ENTRY(feroceon_dma_clean_range) |
260 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
261 | bic r0, r0, #CACHE_DLINESIZE - 1 | 245 | bic r0, r0, #CACHE_DLINESIZE - 1 |
262 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 246 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
263 | add r0, r0, #CACHE_DLINESIZE | 247 | add r0, r0, #CACHE_DLINESIZE |
264 | cmp r0, r1 | 248 | cmp r0, r1 |
265 | blo 1b | 249 | blo 1b |
266 | #endif | ||
267 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | 250 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
268 | mov pc, lr | 251 | mov pc, lr |
269 | 252 | ||
@@ -278,11 +261,7 @@ ENTRY(feroceon_dma_clean_range) | |||
278 | ENTRY(feroceon_dma_flush_range) | 261 | ENTRY(feroceon_dma_flush_range) |
279 | bic r0, r0, #CACHE_DLINESIZE - 1 | 262 | bic r0, r0, #CACHE_DLINESIZE - 1 |
280 | 1: | 263 | 1: |
281 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
282 | mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | 264 | mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry |
283 | #else | ||
284 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | ||
285 | #endif | ||
286 | add r0, r0, #CACHE_DLINESIZE | 265 | add r0, r0, #CACHE_DLINESIZE |
287 | cmp r0, r1 | 266 | cmp r0, r1 |
288 | blo 1b | 267 | blo 1b |
@@ -301,12 +280,10 @@ ENTRY(feroceon_cache_fns) | |||
301 | .long feroceon_dma_flush_range | 280 | .long feroceon_dma_flush_range |
302 | 281 | ||
303 | ENTRY(cpu_feroceon_dcache_clean_area) | 282 | ENTRY(cpu_feroceon_dcache_clean_area) |
304 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
305 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 283 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
306 | add r0, r0, #CACHE_DLINESIZE | 284 | add r0, r0, #CACHE_DLINESIZE |
307 | subs r1, r1, #CACHE_DLINESIZE | 285 | subs r1, r1, #CACHE_DLINESIZE |
308 | bhi 1b | 286 | bhi 1b |
309 | #endif | ||
310 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | 287 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
311 | mov pc, lr | 288 | mov pc, lr |
312 | 289 | ||
@@ -323,13 +300,9 @@ ENTRY(cpu_feroceon_dcache_clean_area) | |||
323 | ENTRY(cpu_feroceon_switch_mm) | 300 | ENTRY(cpu_feroceon_switch_mm) |
324 | #ifdef CONFIG_MMU | 301 | #ifdef CONFIG_MMU |
325 | mov ip, #0 | 302 | mov ip, #0 |
326 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
327 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | ||
328 | #else | ||
329 | @ && 'Clean & Invalidate whole DCache' | 303 | @ && 'Clean & Invalidate whole DCache' |
330 | 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate | 304 | 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate |
331 | bne 1b | 305 | bne 1b |
332 | #endif | ||
333 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache | 306 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache |
334 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | 307 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
335 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer | 308 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer |
@@ -362,16 +335,9 @@ ENTRY(cpu_feroceon_set_pte_ext) | |||
362 | tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? | 335 | tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? |
363 | movne r2, #0 | 336 | movne r2, #0 |
364 | 337 | ||
365 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
366 | eor r3, r2, #0x0a @ C & small page? | ||
367 | tst r3, #0x0b | ||
368 | biceq r2, r2, #4 | ||
369 | #endif | ||
370 | str r2, [r0] @ hardware version | 338 | str r2, [r0] @ hardware version |
371 | mov r0, r0 | 339 | mov r0, r0 |
372 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
373 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 340 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
374 | #endif | ||
375 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | 341 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
376 | #endif | 342 | #endif |
377 | mov pc, lr | 343 | mov pc, lr |
@@ -387,12 +353,6 @@ __feroceon_setup: | |||
387 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 | 353 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 |
388 | #endif | 354 | #endif |
389 | 355 | ||
390 | |||
391 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
392 | mov r0, #4 @ disable write-back on caches explicitly | ||
393 | mcr p15, 7, r0, c15, c0, 0 | ||
394 | #endif | ||
395 | |||
396 | adr r5, feroceon_crval | 356 | adr r5, feroceon_crval |
397 | ldmia r5, {r5, r6} | 357 | ldmia r5, {r5, r6} |
398 | mrc p15, 0, r0, c1, c0 @ get control register v4 | 358 | mrc p15, 0, r0, c1, c0 @ get control register v4 |