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-rw-r--r--arch/arm/mm/Kconfig29
-rw-r--r--arch/arm/mm/Makefile2
-rw-r--r--arch/arm/mm/consistent.c4
-rw-r--r--arch/arm/mm/copypage-xsc3.S97
-rw-r--r--arch/arm/mm/init.c3
-rw-r--r--arch/arm/mm/ioremap.c1
-rw-r--r--arch/arm/mm/mm-armv.c3
-rw-r--r--arch/arm/mm/proc-arm1020.S2
-rw-r--r--arch/arm/mm/proc-arm1020e.S2
-rw-r--r--arch/arm/mm/proc-arm1022.S1
-rw-r--r--arch/arm/mm/proc-arm1026.S1
-rw-r--r--arch/arm/mm/proc-arm6_7.S1
-rw-r--r--arch/arm/mm/proc-arm720.S2
-rw-r--r--arch/arm/mm/proc-arm920.S2
-rw-r--r--arch/arm/mm/proc-arm922.S2
-rw-r--r--arch/arm/mm/proc-arm925.S2
-rw-r--r--arch/arm/mm/proc-arm926.S2
-rw-r--r--arch/arm/mm/proc-sa110.S1
-rw-r--r--arch/arm/mm/proc-sa1100.S1
-rw-r--r--arch/arm/mm/proc-v6.S17
-rw-r--r--arch/arm/mm/proc-xsc3.S499
-rw-r--r--arch/arm/mm/proc-xscale.S2
22 files changed, 654 insertions, 22 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 3b79d0e23455..c55b739e10ba 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -62,7 +62,7 @@ config CPU_ARM720T
62# ARM920T 62# ARM920T
63config CPU_ARM920T 63config CPU_ARM920T
64 bool "Support ARM920T processor" if !ARCH_S3C2410 64 bool "Support ARM920T processor" if !ARCH_S3C2410
65 depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200 65 depends on ARCH_EP93XX || ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
66 default y if ARCH_S3C2410 || ARCH_AT91RM9200 66 default y if ARCH_S3C2410 || ARCH_AT91RM9200
67 select CPU_32v4 67 select CPU_32v4
68 select CPU_ABRT_EV4T 68 select CPU_ABRT_EV4T
@@ -239,6 +239,17 @@ config CPU_XSCALE
239 select CPU_CACHE_VIVT 239 select CPU_CACHE_VIVT
240 select CPU_TLB_V4WBI 240 select CPU_TLB_V4WBI
241 241
242# XScale Core Version 3
243config CPU_XSC3
244 bool
245 depends on ARCH_IXP23XX
246 default y
247 select CPU_32v5
248 select CPU_ABRT_EV5T
249 select CPU_CACHE_VIVT
250 select CPU_TLB_V4WBI
251 select IO_36
252
242# ARMv6 253# ARMv6
243config CPU_V6 254config CPU_V6
244 bool "Support ARM V6 processor" 255 bool "Support ARM V6 processor"
@@ -266,12 +277,18 @@ config CPU_32v6K
266# This defines the compiler instruction set which depends on the machine type. 277# This defines the compiler instruction set which depends on the machine type.
267config CPU_32v3 278config CPU_32v3
268 bool 279 bool
280 select TLS_REG_EMUL if SMP
281 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
269 282
270config CPU_32v4 283config CPU_32v4
271 bool 284 bool
285 select TLS_REG_EMUL if SMP
286 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
272 287
273config CPU_32v5 288config CPU_32v5
274 bool 289 bool
290 select TLS_REG_EMUL if SMP
291 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
275 292
276config CPU_32v6 293config CPU_32v6
277 bool 294 bool
@@ -355,11 +372,17 @@ config CPU_TLB_V4WBI
355config CPU_TLB_V6 372config CPU_TLB_V6
356 bool 373 bool
357 374
375#
376# CPU supports 36-bit I/O
377#
378config IO_36
379 bool
380
358comment "Processor Features" 381comment "Processor Features"
359 382
360config ARM_THUMB 383config ARM_THUMB
361 bool "Support Thumb user binaries" 384 bool "Support Thumb user binaries"
362 depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_V6 385 depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
363 default y 386 default y
364 help 387 help
365 Say Y if you want to include kernel support for running user space 388 Say Y if you want to include kernel support for running user space
@@ -417,7 +440,6 @@ config CPU_BPREDICT_DISABLE
417 440
418config TLS_REG_EMUL 441config TLS_REG_EMUL
419 bool 442 bool
420 default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
421 help 443 help
422 An SMP system using a pre-ARMv6 processor (there are apparently 444 An SMP system using a pre-ARMv6 processor (there are apparently
423 a few prototypes like that in existence) and therefore access to 445 a few prototypes like that in existence) and therefore access to
@@ -436,7 +458,6 @@ config HAS_TLS_REG
436 458
437config NEEDS_SYSCALL_FOR_CMPXCHG 459config NEEDS_SYSCALL_FOR_CMPXCHG
438 bool 460 bool
439 default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
440 help 461 help
441 SMP on a pre-ARMv6 processor? Well OK then. 462 SMP on a pre-ARMv6 processor? Well OK then.
442 Forget about fast user space cmpxchg support. 463 Forget about fast user space cmpxchg support.
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index ffe73ba2bf17..07a538505784 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_CPU_COPY_V4WB) += copypage-v4wb.o
30obj-$(CONFIG_CPU_COPY_V6) += copypage-v6.o mmu.o 30obj-$(CONFIG_CPU_COPY_V6) += copypage-v6.o mmu.o
31obj-$(CONFIG_CPU_SA1100) += copypage-v4mc.o 31obj-$(CONFIG_CPU_SA1100) += copypage-v4mc.o
32obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o 32obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o
33obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o
33 34
34obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o 35obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o
35obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o 36obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o
@@ -51,4 +52,5 @@ obj-$(CONFIG_CPU_ARM1026) += proc-arm1026.o
51obj-$(CONFIG_CPU_SA110) += proc-sa110.o 52obj-$(CONFIG_CPU_SA110) += proc-sa110.o
52obj-$(CONFIG_CPU_SA1100) += proc-sa1100.o 53obj-$(CONFIG_CPU_SA1100) += proc-sa1100.o
53obj-$(CONFIG_CPU_XSCALE) += proc-xscale.o 54obj-$(CONFIG_CPU_XSCALE) += proc-xscale.o
55obj-$(CONFIG_CPU_XSC3) += proc-xsc3.o
54obj-$(CONFIG_CPU_V6) += proc-v6.o 56obj-$(CONFIG_CPU_V6) += proc-v6.o
diff --git a/arch/arm/mm/consistent.c b/arch/arm/mm/consistent.c
index c2ee18d2075e..8a1bfcd50087 100644
--- a/arch/arm/mm/consistent.c
+++ b/arch/arm/mm/consistent.c
@@ -223,6 +223,8 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
223 pte = consistent_pte[idx] + off; 223 pte = consistent_pte[idx] + off;
224 c->vm_pages = page; 224 c->vm_pages = page;
225 225
226 split_page(page, order);
227
226 /* 228 /*
227 * Set the "dma handle" 229 * Set the "dma handle"
228 */ 230 */
@@ -231,7 +233,6 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
231 do { 233 do {
232 BUG_ON(!pte_none(*pte)); 234 BUG_ON(!pte_none(*pte));
233 235
234 set_page_count(page, 1);
235 /* 236 /*
236 * x86 does not mark the pages reserved... 237 * x86 does not mark the pages reserved...
237 */ 238 */
@@ -250,7 +251,6 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
250 * Free the otherwise unused pages. 251 * Free the otherwise unused pages.
251 */ 252 */
252 while (page < end) { 253 while (page < end) {
253 set_page_count(page, 1);
254 __free_page(page); 254 __free_page(page);
255 page++; 255 page++;
256 } 256 }
diff --git a/arch/arm/mm/copypage-xsc3.S b/arch/arm/mm/copypage-xsc3.S
new file mode 100644
index 000000000000..9a2cb4332b4c
--- /dev/null
+++ b/arch/arm/mm/copypage-xsc3.S
@@ -0,0 +1,97 @@
1/*
2 * linux/arch/arm/lib/copypage-xsc3.S
3 *
4 * Copyright (C) 2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Adapted for 3rd gen XScale core, no more mini-dcache
11 * Author: Matt Gilbert (matthew.m.gilbert@intel.com)
12 */
13
14#include <linux/linkage.h>
15#include <linux/init.h>
16#include <asm/asm-offsets.h>
17
18/*
19 * General note:
20 * We don't really want write-allocate cache behaviour for these functions
21 * since that will just eat through 8K of the cache.
22 */
23
24 .text
25 .align 5
26/*
27 * XSC3 optimised copy_user_page
28 * r0 = destination
29 * r1 = source
30 * r2 = virtual user address of ultimate destination page
31 *
32 * The source page may have some clean entries in the cache already, but we
33 * can safely ignore them - break_cow() will flush them out of the cache
34 * if we eventually end up using our copied page.
35 *
36 */
37ENTRY(xsc3_mc_copy_user_page)
38 stmfd sp!, {r4, r5, lr}
39 mov lr, #PAGE_SZ/64-1
40
41 pld [r1, #0]
42 pld [r1, #32]
431: pld [r1, #64]
44 pld [r1, #96]
45
462: ldrd r2, [r1], #8
47 mov ip, r0
48 ldrd r4, [r1], #8
49 mcr p15, 0, ip, c7, c6, 1 @ invalidate
50 strd r2, [r0], #8
51 ldrd r2, [r1], #8
52 strd r4, [r0], #8
53 ldrd r4, [r1], #8
54 strd r2, [r0], #8
55 strd r4, [r0], #8
56 ldrd r2, [r1], #8
57 mov ip, r0
58 ldrd r4, [r1], #8
59 mcr p15, 0, ip, c7, c6, 1 @ invalidate
60 strd r2, [r0], #8
61 ldrd r2, [r1], #8
62 subs lr, lr, #1
63 strd r4, [r0], #8
64 ldrd r4, [r1], #8
65 strd r2, [r0], #8
66 strd r4, [r0], #8
67 bgt 1b
68 beq 2b
69
70 ldmfd sp!, {r4, r5, pc}
71
72 .align 5
73/*
74 * XScale optimised clear_user_page
75 * r0 = destination
76 * r1 = virtual user address of ultimate destination page
77 */
78ENTRY(xsc3_mc_clear_user_page)
79 mov r1, #PAGE_SZ/32
80 mov r2, #0
81 mov r3, #0
821: mcr p15, 0, r0, c7, c6, 1 @ invalidate line
83 strd r2, [r0], #8
84 strd r2, [r0], #8
85 strd r2, [r0], #8
86 strd r2, [r0], #8
87 subs r1, r1, #1
88 bne 1b
89 mov pc, lr
90
91 __INITDATA
92
93 .type xsc3_mc_user_fns, #object
94ENTRY(xsc3_mc_user_fns)
95 .long xsc3_mc_clear_user_page
96 .long xsc3_mc_copy_user_page
97 .size xsc3_mc_user_fns, . - xsc3_mc_user_fns
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 8b276ee38acf..88279124317a 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -19,7 +19,6 @@
19#include <linux/initrd.h> 19#include <linux/initrd.h>
20 20
21#include <asm/mach-types.h> 21#include <asm/mach-types.h>
22#include <asm/hardware.h>
23#include <asm/setup.h> 22#include <asm/setup.h>
24#include <asm/tlb.h> 23#include <asm/tlb.h>
25 24
@@ -531,7 +530,7 @@ static inline void free_area(unsigned long addr, unsigned long end, char *s)
531 for (; addr < end; addr += PAGE_SIZE) { 530 for (; addr < end; addr += PAGE_SIZE) {
532 struct page *page = virt_to_page(addr); 531 struct page *page = virt_to_page(addr);
533 ClearPageReserved(page); 532 ClearPageReserved(page);
534 set_page_count(page, 1); 533 init_page_count(page);
535 free_page(addr); 534 free_page(addr);
536 totalram_pages++; 535 totalram_pages++;
537 } 536 }
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index da9b35974118..25e0ca3e598c 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -26,7 +26,6 @@
26#include <linux/vmalloc.h> 26#include <linux/vmalloc.h>
27 27
28#include <asm/cacheflush.h> 28#include <asm/cacheflush.h>
29#include <asm/hardware.h>
30#include <asm/io.h> 29#include <asm/io.h>
31#include <asm/tlbflush.h> 30#include <asm/tlbflush.h>
32 31
diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
index ef8d30a185a9..5e5d05bcad50 100644
--- a/arch/arm/mm/mm-armv.c
+++ b/arch/arm/mm/mm-armv.c
@@ -557,7 +557,8 @@ void __init create_mapping(struct map_desc *md)
557 * supersections are only allocated for domain 0 regardless 557 * supersections are only allocated for domain 0 regardless
558 * of the actual domain assignments in use. 558 * of the actual domain assignments in use.
559 */ 559 */
560 if (cpu_architecture() >= CPU_ARCH_ARMv6 && domain == 0) { 560 if ((cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())
561 && domain == 0) {
561 /* 562 /*
562 * Align to supersection boundary if !high pages. 563 * Align to supersection boundary if !high pages.
563 * High pages have already been checked for proper 564 * High pages have already been checked for proper
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 82ec954e45b6..959588884fa5 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -29,10 +29,10 @@
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/asm-offsets.h> 31#include <asm/asm-offsets.h>
32#include <asm/pgtable-hwdef.h>
32#include <asm/pgtable.h> 33#include <asm/pgtable.h>
33#include <asm/procinfo.h> 34#include <asm/procinfo.h>
34#include <asm/ptrace.h> 35#include <asm/ptrace.h>
35#include <asm/hardware.h>
36 36
37/* 37/*
38 * This is the maximum size of an area which will be invalidated 38 * This is the maximum size of an area which will be invalidated
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 7375fe930f72..be6d081ff2b7 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -29,10 +29,10 @@
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/asm-offsets.h> 31#include <asm/asm-offsets.h>
32#include <asm/pgtable-hwdef.h>
32#include <asm/pgtable.h> 33#include <asm/pgtable.h>
33#include <asm/procinfo.h> 34#include <asm/procinfo.h>
34#include <asm/ptrace.h> 35#include <asm/ptrace.h>
35#include <asm/hardware.h>
36 36
37/* 37/*
38 * This is the maximum size of an area which will be invalidated 38 * This is the maximum size of an area which will be invalidated
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 6ca639094d6f..f778545d57a2 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -18,6 +18,7 @@
18#include <linux/init.h> 18#include <linux/init.h>
19#include <asm/assembler.h> 19#include <asm/assembler.h>
20#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
21#include <asm/pgtable-hwdef.h>
21#include <asm/pgtable.h> 22#include <asm/pgtable.h>
22#include <asm/procinfo.h> 23#include <asm/procinfo.h>
23#include <asm/ptrace.h> 24#include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 10317e4f55d2..148c111fde73 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -18,6 +18,7 @@
18#include <linux/init.h> 18#include <linux/init.h>
19#include <asm/assembler.h> 19#include <asm/assembler.h>
20#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
21#include <asm/pgtable-hwdef.h>
21#include <asm/pgtable.h> 22#include <asm/pgtable.h>
22#include <asm/procinfo.h> 23#include <asm/procinfo.h>
23#include <asm/ptrace.h> 24#include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 8e7e1e70ab05..540359b475d0 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -14,6 +14,7 @@
14#include <linux/init.h> 14#include <linux/init.h>
15#include <asm/assembler.h> 15#include <asm/assembler.h>
16#include <asm/asm-offsets.h> 16#include <asm/asm-offsets.h>
17#include <asm/pgtable-hwdef.h>
17#include <asm/pgtable.h> 18#include <asm/pgtable.h>
18#include <asm/procinfo.h> 19#include <asm/procinfo.h>
19#include <asm/ptrace.h> 20#include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index a13e0184d343..26f00ee2ad9a 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -34,10 +34,10 @@
34#include <linux/init.h> 34#include <linux/init.h>
35#include <asm/assembler.h> 35#include <asm/assembler.h>
36#include <asm/asm-offsets.h> 36#include <asm/asm-offsets.h>
37#include <asm/pgtable-hwdef.h>
37#include <asm/pgtable.h> 38#include <asm/pgtable.h>
38#include <asm/procinfo.h> 39#include <asm/procinfo.h>
39#include <asm/ptrace.h> 40#include <asm/ptrace.h>
40#include <asm/hardware.h>
41 41
42/* 42/*
43 * Function: arm720_proc_init (void) 43 * Function: arm720_proc_init (void)
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index d16513899999..a17f79e0199c 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -28,9 +28,9 @@
28#include <linux/config.h> 28#include <linux/config.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/pgtable-hwdef.h>
31#include <asm/pgtable.h> 32#include <asm/pgtable.h>
32#include <asm/procinfo.h> 33#include <asm/procinfo.h>
33#include <asm/hardware.h>
34#include <asm/page.h> 34#include <asm/page.h>
35#include <asm/ptrace.h> 35#include <asm/ptrace.h>
36#include "proc-macros.S" 36#include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 23b8ed97f4e3..bbde4a024a48 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -29,9 +29,9 @@
29#include <linux/config.h> 29#include <linux/config.h>
30#include <linux/init.h> 30#include <linux/init.h>
31#include <asm/assembler.h> 31#include <asm/assembler.h>
32#include <asm/pgtable-hwdef.h>
32#include <asm/pgtable.h> 33#include <asm/pgtable.h>
33#include <asm/procinfo.h> 34#include <asm/procinfo.h>
34#include <asm/hardware.h>
35#include <asm/page.h> 35#include <asm/page.h>
36#include <asm/ptrace.h> 36#include <asm/ptrace.h>
37#include "proc-macros.S" 37#include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index ee95c52db513..224ce226a01b 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -51,9 +51,9 @@
51#include <linux/config.h> 51#include <linux/config.h>
52#include <linux/init.h> 52#include <linux/init.h>
53#include <asm/assembler.h> 53#include <asm/assembler.h>
54#include <asm/pgtable-hwdef.h>
54#include <asm/pgtable.h> 55#include <asm/pgtable.h>
55#include <asm/procinfo.h> 56#include <asm/procinfo.h>
56#include <asm/hardware.h>
57#include <asm/page.h> 57#include <asm/page.h>
58#include <asm/ptrace.h> 58#include <asm/ptrace.h>
59#include "proc-macros.S" 59#include "proc-macros.S"
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 7d042dc20c47..4e2a087cf388 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -28,9 +28,9 @@
28#include <linux/config.h> 28#include <linux/config.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <asm/assembler.h> 30#include <asm/assembler.h>
31#include <asm/pgtable-hwdef.h>
31#include <asm/pgtable.h> 32#include <asm/pgtable.h>
32#include <asm/procinfo.h> 33#include <asm/procinfo.h>
33#include <asm/hardware.h>
34#include <asm/page.h> 34#include <asm/page.h>
35#include <asm/ptrace.h> 35#include <asm/ptrace.h>
36#include "proc-macros.S" 36#include "proc-macros.S"
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index bd330c4075a1..c916a6cae404 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -18,6 +18,7 @@
18#include <asm/asm-offsets.h> 18#include <asm/asm-offsets.h>
19#include <asm/procinfo.h> 19#include <asm/procinfo.h>
20#include <asm/hardware.h> 20#include <asm/hardware.h>
21#include <asm/pgtable-hwdef.h>
21#include <asm/pgtable.h> 22#include <asm/pgtable.h>
22#include <asm/ptrace.h> 23#include <asm/ptrace.h>
23 24
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 91b89124c0d7..41f21f2dd8ff 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -23,6 +23,7 @@
23#include <asm/asm-offsets.h> 23#include <asm/asm-offsets.h>
24#include <asm/procinfo.h> 24#include <asm/procinfo.h>
25#include <asm/hardware.h> 25#include <asm/hardware.h>
26#include <asm/pgtable-hwdef.h>
26#include <asm/pgtable.h> 27#include <asm/pgtable.h>
27 28
28/* 29/*
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 92f3ca31b7b9..ee6f15298735 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -14,12 +14,21 @@
14#include <asm/asm-offsets.h> 14#include <asm/asm-offsets.h>
15#include <asm/hardware/arm_scu.h> 15#include <asm/hardware/arm_scu.h>
16#include <asm/procinfo.h> 16#include <asm/procinfo.h>
17#include <asm/pgtable-hwdef.h>
17#include <asm/pgtable.h> 18#include <asm/pgtable.h>
18 19
19#include "proc-macros.S" 20#include "proc-macros.S"
20 21
21#define D_CACHE_LINE_SIZE 32 22#define D_CACHE_LINE_SIZE 32
22 23
24#define TTB_C (1 << 0)
25#define TTB_S (1 << 1)
26#define TTB_IMP (1 << 2)
27#define TTB_RGN_NC (0 << 3)
28#define TTB_RGN_WBWA (1 << 3)
29#define TTB_RGN_WT (2 << 3)
30#define TTB_RGN_WB (3 << 3)
31
23 .macro cpsie, flags 32 .macro cpsie, flags
24 .ifc \flags, f 33 .ifc \flags, f
25 .long 0xf1080040 34 .long 0xf1080040
@@ -114,7 +123,7 @@ ENTRY(cpu_v6_switch_mm)
114 mov r2, #0 123 mov r2, #0
115 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 124 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
116#ifdef CONFIG_SMP 125#ifdef CONFIG_SMP
117 orr r0, r0, #2 @ set shared pgtable 126 orr r0, r0, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable
118#endif 127#endif
119 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 128 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
120 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 129 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
@@ -160,8 +169,8 @@ ENTRY(cpu_v6_set_pte)
160 tst r1, #L_PTE_YOUNG 169 tst r1, #L_PTE_YOUNG
161 biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK 170 biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK
162 171
163@ tst r1, #L_PTE_EXEC 172 tst r1, #L_PTE_EXEC
164@ orreq r2, r2, #PTE_EXT_XN 173 orreq r2, r2, #PTE_EXT_XN
165 174
166 tst r1, #L_PTE_PRESENT 175 tst r1, #L_PTE_PRESENT
167 moveq r2, #0 176 moveq r2, #0
@@ -220,7 +229,7 @@ __v6_setup:
220 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs 229 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
221 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 230 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
222#ifdef CONFIG_SMP 231#ifdef CONFIG_SMP
223 orr r4, r4, #2 @ set shared pgtable 232 orr r4, r4, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable
224#endif 233#endif
225 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 234 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
226#ifdef CONFIG_VFP 235#ifdef CONFIG_VFP
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
new file mode 100644
index 000000000000..b9dfce57c272
--- /dev/null
+++ b/arch/arm/mm/proc-xsc3.S
@@ -0,0 +1,499 @@
1/*
2 * linux/arch/arm/mm/proc-xsc3.S
3 *
4 * Original Author: Matthew Gilbert
5 * Current Maintainer: Deepak Saxena <dsaxena@plexity.net>
6 *
7 * Copyright 2004 (C) Intel Corp.
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * MMU functions for the Intel XScale3 Core (XSC3). The XSC3 core is an
15 * extension to Intel's original XScale core that adds the following
16 * features:
17 *
18 * - ARMv6 Supersections
19 * - Low Locality Reference pages (replaces mini-cache)
20 * - 36-bit addressing
21 * - L2 cache
22 * - Cache-coherency if chipset supports it
23 *
24 * Based on orignal XScale code by Nicolas Pitre
25 */
26
27#include <linux/linkage.h>
28#include <linux/init.h>
29#include <asm/assembler.h>
30#include <asm/procinfo.h>
31#include <asm/hardware.h>
32#include <asm/pgtable.h>
33#include <asm/pgtable-hwdef.h>
34#include <asm/page.h>
35#include <asm/ptrace.h>
36#include "proc-macros.S"
37
38/*
39 * This is the maximum size of an area which will be flushed. If the
40 * area is larger than this, then we flush the whole cache.
41 */
42#define MAX_AREA_SIZE 32768
43
44/*
45 * The cache line size of the I and D cache.
46 */
47#define CACHELINESIZE 32
48
49/*
50 * The size of the data cache.
51 */
52#define CACHESIZE 32768
53
54/*
55 * Run with L2 enabled.
56 */
57#define L2_CACHE_ENABLE 1
58
59/*
60 * Enable the Branch Target Buffer (can cause crashes, see erratum #42.)
61 */
62#define BTB_ENABLE 0
63
64/*
65 * This macro is used to wait for a CP15 write and is needed
66 * when we have to ensure that the last operation to the co-pro
67 * was completed before continuing with operation.
68 */
69 .macro cpwait_ret, lr, rd
70 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
71 sub pc, \lr, \rd, LSR #32 @ wait for completion and
72 @ flush instruction pipeline
73 .endm
74
75/*
76 * This macro cleans & invalidates the entire xsc3 dcache by set & way.
77 */
78
79 .macro clean_d_cache rd, rs
80 mov \rd, #0x1f00
81 orr \rd, \rd, #0x00e0
821: mcr p15, 0, \rd, c7, c14, 2 @ clean/inv set/way
83 adds \rd, \rd, #0x40000000
84 bcc 1b
85 subs \rd, \rd, #0x20
86 bpl 1b
87 .endm
88
89 .text
90
91/*
92 * cpu_xsc3_proc_init()
93 *
94 * Nothing too exciting at the moment
95 */
96ENTRY(cpu_xsc3_proc_init)
97 mov pc, lr
98
99/*
100 * cpu_xsc3_proc_fin()
101 */
102ENTRY(cpu_xsc3_proc_fin)
103 str lr, [sp, #-4]!
104 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
105 msr cpsr_c, r0
106 bl xsc3_flush_kern_cache_all @ clean caches
107 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
108 bic r0, r0, #0x1800 @ ...IZ...........
109 bic r0, r0, #0x0006 @ .............CA.
110 mcr p15, 0, r0, c1, c0, 0 @ disable caches
111 ldr pc, [sp], #4
112
113/*
114 * cpu_xsc3_reset(loc)
115 *
116 * Perform a soft reset of the system. Put the CPU into the
117 * same state as it would be if it had been reset, and branch
118 * to what would be the reset vector.
119 *
120 * loc: location to jump to for soft reset
121 */
122 .align 5
123ENTRY(cpu_xsc3_reset)
124 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
125 msr cpsr_c, r1 @ reset CPSR
126 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
127 bic r1, r1, #0x0086 @ ........B....CA.
128 bic r1, r1, #0x3900 @ ..VIZ..S........
129 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
130 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
131 bic r1, r1, #0x0001 @ ...............M
132 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
133 @ CAUTION: MMU turned off from this point. We count on the pipeline
134 @ already containing those two last instructions to survive.
135 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
136 mov pc, r0
137
138/*
139 * cpu_xsc3_do_idle()
140 *
141 * Cause the processor to idle
142 *
143 * For now we do nothing but go to idle mode for every case
144 *
145 * XScale supports clock switching, but using idle mode support
146 * allows external hardware to react to system state changes.
147
148 MMG: Come back to this one.
149 */
150 .align 5
151
152ENTRY(cpu_xsc3_do_idle)
153 mov r0, #1
154 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
155 mov pc, lr
156
157/* ================================= CACHE ================================ */
158
159/*
160 * flush_user_cache_all()
161 *
162 * Invalidate all cache entries in a particular address
163 * space.
164 */
165ENTRY(xsc3_flush_user_cache_all)
166 /* FALLTHROUGH */
167
168/*
169 * flush_kern_cache_all()
170 *
171 * Clean and invalidate the entire cache.
172 */
173ENTRY(xsc3_flush_kern_cache_all)
174 mov r2, #VM_EXEC
175 mov ip, #0
176__flush_whole_cache:
177 clean_d_cache r0, r1
178 tst r2, #VM_EXEC
179 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
180 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
181 mcrne p15, 0, ip, c7, c5, 4 @ Prefetch Flush
182 mov pc, lr
183
184/*
185 * flush_user_cache_range(start, end, vm_flags)
186 *
187 * Invalidate a range of cache entries in the specified
188 * address space.
189 *
190 * - start - start address (may not be aligned)
191 * - end - end address (exclusive, may not be aligned)
192 * - vma - vma_area_struct describing address space
193 */
194 .align 5
195ENTRY(xsc3_flush_user_cache_range)
196 mov ip, #0
197 sub r3, r1, r0 @ calculate total size
198 cmp r3, #MAX_AREA_SIZE
199 bhs __flush_whole_cache
200
2011: tst r2, #VM_EXEC
202 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
203 mcr p15, 0, r0, c7, c14, 1 @ Clean/invalidate D cache line
204 add r0, r0, #CACHELINESIZE
205 cmp r0, r1
206 blo 1b
207 tst r2, #VM_EXEC
208 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
209 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
210 mcrne p15, 0, ip, c7, c5, 4 @ Prefetch Flush
211 mov pc, lr
212
213/*
214 * coherent_kern_range(start, end)
215 *
216 * Ensure coherency between the Icache and the Dcache in the
217 * region described by start. If you have non-snooping
218 * Harvard caches, you need to implement this function.
219 *
220 * - start - virtual start address
221 * - end - virtual end address
222 *
223 * Note: single I-cache line invalidation isn't used here since
224 * it also trashes the mini I-cache used by JTAG debuggers.
225 */
226ENTRY(xsc3_coherent_kern_range)
227/* FALLTHROUGH */
228ENTRY(xsc3_coherent_user_range)
229 bic r0, r0, #CACHELINESIZE - 1
2301: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
231 add r0, r0, #CACHELINESIZE
232 cmp r0, r1
233 blo 1b
234 mov r0, #0
235 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
236 mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
237 mcr p15, 0, r0, c7, c5, 4 @ Prefetch Flush
238 mov pc, lr
239
240/*
241 * flush_kern_dcache_page(void *page)
242 *
243 * Ensure no D cache aliasing occurs, either with itself or
244 * the I cache
245 *
246 * - addr - page aligned address
247 */
248ENTRY(xsc3_flush_kern_dcache_page)
249 add r1, r0, #PAGE_SZ
2501: mcr p15, 0, r0, c7, c14, 1 @ Clean/Invalidate D Cache line
251 add r0, r0, #CACHELINESIZE
252 cmp r0, r1
253 blo 1b
254 mov r0, #0
255 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
256 mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
257 mcr p15, 0, r0, c7, c5, 4 @ Prefetch Flush
258 mov pc, lr
259
260/*
261 * dma_inv_range(start, end)
262 *
263 * Invalidate (discard) the specified virtual address range.
264 * May not write back any entries. If 'start' or 'end'
265 * are not cache line aligned, those lines must be written
266 * back.
267 *
268 * - start - virtual start address
269 * - end - virtual end address
270 */
271ENTRY(xsc3_dma_inv_range)
272 tst r0, #CACHELINESIZE - 1
273 bic r0, r0, #CACHELINESIZE - 1
274 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D entry
275 mcrne p15, 1, r0, c7, c11, 1 @ clean L2 D entry
276 tst r1, #CACHELINESIZE - 1
277 mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D entry
278 mcrne p15, 1, r1, c7, c11, 1 @ clean L2 D entry
2791: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D entry
280 mcr p15, 1, r0, c7, c7, 1 @ Invalidate L2 D cache line
281 add r0, r0, #CACHELINESIZE
282 cmp r0, r1
283 blo 1b
284 mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
285 mov pc, lr
286
287/*
288 * dma_clean_range(start, end)
289 *
290 * Clean the specified virtual address range.
291 *
292 * - start - virtual start address
293 * - end - virtual end address
294 */
295ENTRY(xsc3_dma_clean_range)
296 bic r0, r0, #CACHELINESIZE - 1
2971: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D entry
298 mcr p15, 1, r0, c7, c11, 1 @ clean L2 D entry
299 add r0, r0, #CACHELINESIZE
300 cmp r0, r1
301 blo 1b
302 mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
303 mov pc, lr
304
305/*
306 * dma_flush_range(start, end)
307 *
308 * Clean and invalidate the specified virtual address range.
309 *
310 * - start - virtual start address
311 * - end - virtual end address
312 */
313ENTRY(xsc3_dma_flush_range)
314 bic r0, r0, #CACHELINESIZE - 1
3151: mcr p15, 0, r0, c7, c14, 1 @ Clean/invalidate L1 D cache line
316 mcr p15, 1, r0, c7, c11, 1 @ Clean L2 D cache line
317 mcr p15, 1, r0, c7, c7, 1 @ Invalidate L2 D cache line
318 add r0, r0, #CACHELINESIZE
319 cmp r0, r1
320 blo 1b
321 mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
322 mov pc, lr
323
324ENTRY(xsc3_cache_fns)
325 .long xsc3_flush_kern_cache_all
326 .long xsc3_flush_user_cache_all
327 .long xsc3_flush_user_cache_range
328 .long xsc3_coherent_kern_range
329 .long xsc3_coherent_user_range
330 .long xsc3_flush_kern_dcache_page
331 .long xsc3_dma_inv_range
332 .long xsc3_dma_clean_range
333 .long xsc3_dma_flush_range
334
335ENTRY(cpu_xsc3_dcache_clean_area)
3361: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
337 add r0, r0, #CACHELINESIZE
338 subs r1, r1, #CACHELINESIZE
339 bhi 1b
340 mov pc, lr
341
342/* =============================== PageTable ============================== */
343
344/*
345 * cpu_xsc3_switch_mm(pgd)
346 *
347 * Set the translation base pointer to be as described by pgd.
348 *
349 * pgd: new page tables
350 */
351 .align 5
352ENTRY(cpu_xsc3_switch_mm)
353 clean_d_cache r1, r2
354 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
355 mcr p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
356 mcr p15, 0, ip, c7, c5, 4 @ Prefetch Flush
357#ifdef L2_CACHE_ENABLE
358 orr r0, r0, #0x18 @ cache the page table in L2
359#endif
360 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
361 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
362 cpwait_ret lr, ip
363
364/*
365 * cpu_xsc3_set_pte(ptep, pte)
366 *
367 * Set a PTE and flush it out
368 *
369 */
370 .align 5
371ENTRY(cpu_xsc3_set_pte)
372 str r1, [r0], #-2048 @ linux version
373
374 bic r2, r1, #0xff0
375 orr r2, r2, #PTE_TYPE_EXT @ extended page
376
377 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
378
379 tst r3, #L_PTE_USER @ User?
380 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
381
382 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
383 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
384 @ combined with user -> user r/w
385
386#if L2_CACHE_ENABLE
387 @ If its cacheable it needs to be in L2 also.
388 eor ip, r1, #L_PTE_CACHEABLE
389 tst ip, #L_PTE_CACHEABLE
390 orreq r2, r2, #PTE_EXT_TEX(0x5)
391#endif
392
393 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
394 movne r2, #0 @ no -> fault
395
396 str r2, [r0] @ hardware version
397 mov ip, #0
398 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line mcr
399 mcr p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
400 mov pc, lr
401
402 .ltorg
403
404 .align
405
406 __INIT
407
408 .type __xsc3_setup, #function
409__xsc3_setup:
410 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
411 msr cpsr_c, r0
412 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
413 mcr p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
414 mcr p15, 0, ip, c7, c5, 4 @ Prefetch Flush
415 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
416#if L2_CACHE_ENABLE
417 orr r4, r4, #0x18 @ cache the page table in L2
418#endif
419 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
420 mov r0, #1 @ Allow access to CP0 and CP13
421 orr r0, r0, #1 << 13 @ Its undefined whether this
422 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
423 mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
424 and r0, r0, #2 @ preserve bit P bit setting
425#if L2_CACHE_ENABLE
426 orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
427#endif
428 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
429 mrc p15, 0, r0, c1, c0, 0 @ get control register
430 bic r0, r0, #0x0200 @ .... ..R. .... ....
431 bic r0, r0, #0x0002 @ .... .... .... ..A.
432 orr r0, r0, #0x0005 @ .... .... .... .C.M
433#if BTB_ENABLE
434 orr r0, r0, #0x3900 @ ..VI Z..S .... ....
435#else
436 orr r0, r0, #0x3100 @ ..VI ...S .... ....
437#endif
438#if L2_CACHE_ENABLE
439 orr r0, r0, #0x4000000 @ L2 enable
440#endif
441 mov pc, lr
442
443 .size __xsc3_setup, . - __xsc3_setup
444
445 __INITDATA
446
447/*
448 * Purpose : Function pointers used to access above functions - all calls
449 * come through these
450 */
451
452 .type xsc3_processor_functions, #object
453ENTRY(xsc3_processor_functions)
454 .word v5t_early_abort
455 .word cpu_xsc3_proc_init
456 .word cpu_xsc3_proc_fin
457 .word cpu_xsc3_reset
458 .word cpu_xsc3_do_idle
459 .word cpu_xsc3_dcache_clean_area
460 .word cpu_xsc3_switch_mm
461 .word cpu_xsc3_set_pte
462 .size xsc3_processor_functions, . - xsc3_processor_functions
463
464 .section ".rodata"
465
466 .type cpu_arch_name, #object
467cpu_arch_name:
468 .asciz "armv5te"
469 .size cpu_arch_name, . - cpu_arch_name
470
471 .type cpu_elf_name, #object
472cpu_elf_name:
473 .asciz "v5"
474 .size cpu_elf_name, . - cpu_elf_name
475
476 .type cpu_xsc3_name, #object
477cpu_xsc3_name:
478 .asciz "XScale-Core3"
479 .size cpu_xsc3_name, . - cpu_xsc3_name
480
481 .align
482
483 .section ".proc.info.init", #alloc, #execinstr
484
485 .type __xsc3_proc_info,#object
486__xsc3_proc_info:
487 .long 0x69056000
488 .long 0xffffe000
489 .long 0x00000c0e
490 b __xsc3_setup
491 .long cpu_arch_name
492 .long cpu_elf_name
493 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
494 .long cpu_xsc3_name
495 .long xsc3_processor_functions
496 .long v4wbi_tlb_fns
497 .long xsc3_mc_user_fns
498 .long xsc3_cache_fns
499 .size __xsc3_proc_info, . - __xsc3_proc_info
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 2d3823ec3153..29bcc4dd6517 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -24,8 +24,8 @@
24#include <linux/init.h> 24#include <linux/init.h>
25#include <asm/assembler.h> 25#include <asm/assembler.h>
26#include <asm/procinfo.h> 26#include <asm/procinfo.h>
27#include <asm/hardware.h>
28#include <asm/pgtable.h> 27#include <asm/pgtable.h>
28#include <asm/pgtable-hwdef.h>
29#include <asm/page.h> 29#include <asm/page.h>
30#include <asm/ptrace.h> 30#include <asm/ptrace.h>
31#include "proc-macros.S" 31#include "proc-macros.S"
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-23 06:14:21 -0500